forked from mirror/uv-k5-firmware
117 lines
3.4 KiB
C
117 lines
3.4 KiB
C
/* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "ARMCM0.h"
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#include "bsp/dp32g030/spi.h"
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#include "bsp/dp32g030/syscon.h"
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#include "bsp/dp32g030/irq.h"
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#include "driver/spi.h"
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void SPI0_Init(void)
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{
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SPI_Config_t Config;
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SPI_Disable(&SPI0->CR);
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Config.TXFIFO_EMPTY = 0;
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Config.RXFIFO_HFULL = 0;
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Config.RXFIFO_FULL = 0;
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Config.RXFIFO_OVF = 0;
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Config.MSTR = 1;
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Config.SPR = 2;
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Config.CPHA = 1;
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Config.CPOL = 1;
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Config.LSB = 0;
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Config.TF_CLR = 0;
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Config.RF_CLR = 0;
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Config.TXFIFO_HFULL = 0;
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SPI_Configure(SPI0, &Config);
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SPI_Enable(&SPI0->CR);
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}
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void SPI_WaitForUndocumentedTxFifoStatusBit(void)
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{
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uint32_t Timeout;
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Timeout = 0;
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do {
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// Undocumented bit!
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if ((SPI0->IF & 0x20) == 0) {
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break;
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}
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Timeout++;
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} while (Timeout <= 100000);
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}
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void SPI_Disable(volatile uint32_t *pCR)
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{
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*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_DISABLE;
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}
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void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig)
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{
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if (pPort == SPI0) {
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SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE;
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} else if (pPort == SPI1) {
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SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE;
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}
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SPI_Disable(&pPort->CR);
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pPort->CR = 0
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| (pPort->CR & ~(SPI_CR_SPR_MASK | SPI_CR_CPHA_MASK | SPI_CR_CPOL_MASK | SPI_CR_MSTR_MASK | SPI_CR_LSB_MASK | SPI_CR_RF_CLR_MASK))
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| ((pConfig->SPR << SPI_CR_SPR_SHIFT) & SPI_CR_SPR_MASK)
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| ((pConfig->CPHA << SPI_CR_CPHA_SHIFT) & SPI_CR_CPHA_MASK)
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| ((pConfig->CPOL << SPI_CR_CPOL_SHIFT) & SPI_CR_CPOL_MASK)
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| ((pConfig->MSTR << SPI_CR_MSTR_SHIFT) & SPI_CR_MSTR_MASK)
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| ((pConfig->LSB << SPI_CR_LSB_SHIFT) & SPI_CR_LSB_MASK)
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| ((pConfig->RF_CLR << SPI_CR_RF_CLR_SHIFT) & SPI_CR_RF_CLR_MASK)
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| ((pConfig->TF_CLR << SPI_CR_TF_CLR_SHIFT) & SPI_CR_TF_CLR_MASK)
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;
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pPort->IE = 0
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| ((pConfig->RXFIFO_OVF << SPI_IE_RXFIFO_OVF_SHIFT) & SPI_IE_RXFIFO_OVF_MASK)
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| ((pConfig->RXFIFO_FULL << SPI_IE_RXFIFO_FULL_SHIFT) & SPI_IE_RXFIFO_FULL_MASK)
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| ((pConfig->RXFIFO_HFULL << SPI_IE_RXFIFO_HFULL_SHIFT) & SPI_IE_RXFIFO_HFULL_MASK)
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| ((pConfig->TXFIFO_EMPTY << SPI_IE_TXFIFO_EMPTY_SHIFT) & SPI_IE_TXFIFO_EMPTY_MASK)
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| ((pConfig->TXFIFO_HFULL << SPI_IE_TXFIFO_HFULL_SHIFT) & SPI_IE_TXFIFO_HFULL_MASK)
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;
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if (pPort->IE) {
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if (pPort == SPI0) {
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NVIC_EnableIRQ(DP32_SPI0_IRQn);
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} else if (pPort == SPI1) {
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NVIC_EnableIRQ(DP32_SPI1_IRQn);
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}
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}
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}
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void SPI_ToggleMasterMode(volatile uint32_t *pCR, bool bIsMaster)
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{
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if (bIsMaster) {
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*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_ENABLE;
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} else {
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*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_DISABLE;
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}
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}
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void SPI_Enable(volatile uint32_t *pCR)
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{
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*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_ENABLE;
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}
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