forked from mirror/uv-k5-firmware
First version.
This commit is contained in:
Dual Tachyon
parent
196886c0c0
commit
fc65cd11a6
3
.gitmodules
vendored
Normal file
3
.gitmodules
vendored
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@ -0,0 +1,3 @@
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[submodule "external/CMSIS_5"]
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path = external/CMSIS_5
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url = https://github.com/ARM-software/CMSIS_5
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104
Makefile
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104
Makefile
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@ -0,0 +1,104 @@
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TARGET = firmware
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OVERLAY = sram-overlay
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BLOB_OVERLAY = blob-overlay
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LINK_OVERLAY = link-overlay
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BSP_DEFINITIONS := $(wildcard hardware/*/*.def)
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BSP_HEADERS := $(patsubst hardware/%,bsp/%,$(BSP_DEFINITIONS))
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BSP_HEADERS := $(patsubst %.def,%.h,$(BSP_HEADERS))
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OBJS =
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# Startup files
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OBJS += start.o
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OBJS += init.o
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OBJS += overlay.o
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OBJS += $(LINK_OVERLAY).o
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OBJS += $(BLOB_OVERLAY).o
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# Drivers
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OBJS += driver/crc.o
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OBJS += driver/eeprom.o
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OBJS += driver/flash.o
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OBJS += driver/gpio.o
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OBJS += driver/i2c.o
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OBJS += driver/spi.o
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OBJS += driver/st7565.o
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OBJS += driver/system.o
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OBJS += driver/systick.o
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OBJS += driver/uart.o
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# Main
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OBJS += board.o
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OBJS += main.o
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TOP := $(shell pwd)
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AS = arm-none-eabi-as
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CC = arm-none-eabi-gcc
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LD = arm-none-eabi-gcc
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OBJCOPY = arm-none-eabi-objcopy
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ASFLAGS = -mcpu=cortex-m0
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CFLAGS = -O2 -Wall -Werror -mcpu=cortex-m0 -fno-builtin -MMD
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LDFLAGS = -mcpu=cortex-m0 -nostartfiles -Wl,-T,firmware.ld
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OVERLAY_CFLAGS = $(CFLAGS) -fno-inline -fno-toplevel-reorder
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OVERLAY_LD = arm-none-eabi-ld
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OVERLAY_LDFLAGS = -T $(OVERLAY).ld -S
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ifeq ($(DEBUG),1)
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ASFLAGS += -g
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CFLAGS += -g
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LDFLAGS += -g
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endif
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INC =
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INC += -I $(TOP)
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INC += -I $(TOP)/external/CMSIS_5/CMSIS/Core/Include/
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INC += -I $(TOP)/external/CMSIS_5/Device/ARM/ARMCM0/Include
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LIBS =
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DEPS = $(OBJS:.o=.d)
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all: $(TARGET)
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$(OBJCOPY) -O binary $< $<.bin
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$(OVERLAY).bin: $(OVERLAY)
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$(OBJCOPY) -O binary $< $@
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$(OVERLAY): $(OVERLAY).o
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$(OVERLAY_LD) $(OVERLAY_LDFLAGS) $< -o $@
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$(OVERLAY).o: $(OVERLAY).c
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$(CC) $(OVERLAY_CFLAGS) $(INC) -c $< -o $@
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$(LINK_OVERLAY).o: $(LINK_OVERLAY).S
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$(AS) $(ASFLAGS) $< -o $@
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$(LINK_OVERLAY).S: $(OVERLAY)
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./gen-overlay-symbols.sh $< $@
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$(BLOB_OVERLAY).o: $(BLOB_OVERLAY).c
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$(BLOB_OVERLAY).c: $(OVERLAY).bin
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echo "const " > $@
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xxd -i $< >> $@
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$(TARGET): $(OBJS)
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$(LD) $(LDFLAGS) $^ -o $@ $(LIBS)
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bsp/dp32g030/%.h: hardware/dp32g030/%.def
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./gen-headers.py --hwdef $< --header $@
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%.o: %.c | $(BSP_HEADERS)
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$(CC) $(CFLAGS) $(INC) -c $< -o $@
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%.o: %.S
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$(AS) $(ASFLAGS) $< -o $@
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-include $(DEPS)
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clean:
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rm -f $(TARGET).bin $(TARGET) $(OBJS) $(DEPS) $(OVERLAY).bin $(OVERLAY) $(OVERLAY).o $(OVERLAY).d $(LINK_OVERLAY).o $(LINK_OVERLAY).S $(BLOB_OVERLAY).o $(BLOB_OVERLAY).c
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21
README.md
Normal file
21
README.md
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@ -0,0 +1,21 @@
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# Open reimplementation of the Quan Sheng UV K5 v2.1.27 firmware
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This currently works for me, but use at your own risk.
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# License
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Copyright 2023 Dual Tachyon
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https://github.com/DualTachyon
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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294
board.c
Normal file
294
board.c
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@ -0,0 +1,294 @@
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/* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#include "board.h"
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#include "bsp/dp32g030/gpio.h"
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#include "bsp/dp32g030/portcon.h"
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#include "driver/crc.h"
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#include "driver/flash.h"
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#include "driver/gpio.h"
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#include "driver/system.h"
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#include "driver/st7565.h"
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#include "sram-overlay.h"
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void BOARD_FLASH_Init(void)
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{
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FLASH_Init(FLASH_READ_MODE_1_CYCLE);
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FLASH_ConfigureTrimValues();
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SYSTEM_ConfigureClocks();
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overlay_FLASH_MainClock = 48000000;
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overlay_FLASH_ClockMultiplier = 48;
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FLASH_Init(FLASH_READ_MODE_2_CYCLE);
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}
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void BOARD_GPIO_Init(void)
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{
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GPIOA->DIR |= 0
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| GPIO_DIR_10_OUTPUT
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| GPIO_DIR_11_OUTPUT
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| GPIO_DIR_12_OUTPUT
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| GPIO_DIR_13_OUTPUT
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;
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GPIOA->DIR &= ~(0
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| GPIO_DIR_3_MASK
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| GPIO_DIR_4_MASK
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| GPIO_DIR_5_MASK
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| GPIO_DIR_6_MASK
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);
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GPIOB->DIR |= 0
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| GPIO_DIR_6_OUTPUT
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| GPIO_DIR_9_OUTPUT
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| GPIO_DIR_11_OUTPUT
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| GPIO_DIR_15_OUTPUT
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;
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GPIOC->DIR |= 0
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| GPIO_DIR_0_OUTPUT
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| GPIO_DIR_1_OUTPUT
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| GPIO_DIR_2_OUTPUT
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| GPIO_DIR_3_OUTPUT
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| GPIO_DIR_4_OUTPUT
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;
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GPIOC->DIR &= ~(0
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| GPIO_DIR_5_MASK
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);
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GPIO_SetBit(&GPIOB->DATA, 15);
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}
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void BOARD_PORTCON_Init(void)
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{
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// TODO: Need to redo these macros to make more sense.
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// PORT A pin selection
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PORTCON_PORTA_SEL0 &= 0
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| PORTCON_PORTA_SEL0_A0_MASK
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| PORTCON_PORTA_SEL0_A1_MASK
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| PORTCON_PORTA_SEL0_A2_MASK
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| PORTCON_PORTA_SEL0_A7_MASK
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;
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PORTCON_PORTA_SEL0 |= 0
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| PORTCON_PORTA_SEL0_A0_GPIOA0
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| PORTCON_PORTA_SEL0_A1_GPIOA1
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| PORTCON_PORTA_SEL0_A2_GPIOA2
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| PORTCON_PORTA_SEL0_A7_UART1_TX
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;
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PORTCON_PORTA_SEL1 &= 0
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| PORTCON_PORTA_SEL1_A8_MASK
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| PORTCON_PORTA_SEL1_A9_MASK
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| PORTCON_PORTA_SEL1_A14_MASK
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| PORTCON_PORTA_SEL1_A15_MASK
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;
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PORTCON_PORTA_SEL1 |= 0
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| PORTCON_PORTA_SEL1_A8_UART1_RX
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| PORTCON_PORTA_SEL1_A9_SARADC_CH4
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| PORTCON_PORTA_SEL1_A14_SARADC_CH9
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| PORTCON_PORTA_SEL1_A15_GPIOA15
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;
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// PORT B pin selection
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PORTCON_PORTB_SEL0 &= 0
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| PORTCON_PORTB_SEL0_B0_MASK
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| PORTCON_PORTB_SEL0_B1_MASK
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| PORTCON_PORTB_SEL0_B2_MASK
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| PORTCON_PORTB_SEL0_B3_MASK
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| PORTCON_PORTB_SEL0_B4_MASK
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| PORTCON_PORTB_SEL0_B5_MASK
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;
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PORTCON_PORTB_SEL0 |= 0
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| PORTCON_PORTB_SEL0_B0_GPIOB0
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| PORTCON_PORTB_SEL0_B1_GPIOB1
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| PORTCON_PORTB_SEL0_B2_GPIOB2
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| PORTCON_PORTB_SEL0_B3_GPIOB3
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| PORTCON_PORTB_SEL0_B4_GPIOB4
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| PORTCON_PORTB_SEL0_B5_GPIOB5
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| PORTCON_PORTB_SEL0_B7_SPI0_SSN
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;
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PORTCON_PORTB_SEL1 &= 0
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| PORTCON_PORTB_SEL1_B8_MASK
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| PORTCON_PORTB_SEL1_B10_MASK
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| PORTCON_PORTB_SEL1_B12_MASK
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| PORTCON_PORTB_SEL1_B13_MASK
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;
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PORTCON_PORTB_SEL1 |= 0
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| PORTCON_PORTB_SEL1_B8_SPI0_CLK
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| PORTCON_PORTB_SEL1_B10_SPI0_MOSI
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| PORTCON_PORTB_SEL1_B11_SWDIO
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| PORTCON_PORTB_SEL1_B12_GPIOB12
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| PORTCON_PORTB_SEL1_B13_GPIOB13
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| PORTCON_PORTB_SEL1_B14_SWCLK
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;
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// PORT C pin selection
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PORTCON_PORTC_SEL0 &= 0
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| PORTCON_PORTC_SEL0_C6_MASK
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| PORTCON_PORTC_SEL0_C7_MASK
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;
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// PORT A pin configuration
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PORTCON_PORTA_IE |= 0
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| PORTCON_PORTA_IE_A3_ENABLE
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| PORTCON_PORTA_IE_A4_ENABLE
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| PORTCON_PORTA_IE_A5_ENABLE
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| PORTCON_PORTA_IE_A6_ENABLE
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| PORTCON_PORTA_IE_A8_ENABLE
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;
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PORTCON_PORTA_IE &= ~(0
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| PORTCON_PORTA_IE_A10_MASK
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| PORTCON_PORTA_IE_A11_MASK
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| PORTCON_PORTA_IE_A12_MASK
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| PORTCON_PORTA_IE_A13_MASK
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);
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PORTCON_PORTA_PU |= 0
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| PORTCON_PORTA_PU_A3_ENABLE
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| PORTCON_PORTA_PU_A4_ENABLE
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| PORTCON_PORTA_PU_A5_ENABLE
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| PORTCON_PORTA_PU_A6_ENABLE
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;
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PORTCON_PORTA_PU &= ~(0
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| PORTCON_PORTA_PU_A10_MASK
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| PORTCON_PORTA_PU_A11_MASK
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| PORTCON_PORTA_PU_A12_MASK
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| PORTCON_PORTA_PU_A13_MASK
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);
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PORTCON_PORTA_PD &= ~(0
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| PORTCON_PORTA_PD_A3_MASK
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| PORTCON_PORTA_PD_A4_MASK
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| PORTCON_PORTA_PD_A5_MASK
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| PORTCON_PORTA_PD_A6_MASK
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| PORTCON_PORTA_PD_A10_MASK
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| PORTCON_PORTA_PD_A11_MASK
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| PORTCON_PORTA_PD_A12_MASK
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| PORTCON_PORTA_PD_A13_MASK
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);
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PORTCON_PORTA_OD |= 0
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| PORTCON_PORTA_OD_A3_ENABLE
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| PORTCON_PORTA_OD_A4_ENABLE
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| PORTCON_PORTA_OD_A5_ENABLE
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| PORTCON_PORTA_OD_A6_ENABLE
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;
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PORTCON_PORTA_OD &= ~(0
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| PORTCON_PORTA_OD_A10_MASK
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| PORTCON_PORTA_OD_A11_MASK
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| PORTCON_PORTA_OD_A12_MASK
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| PORTCON_PORTA_OD_A13_MASK
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);
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// PORT B pin configuration
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PORTCON_PORTB_IE |= 0
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| PORTCON_PORTB_IE_B14_ENABLE
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;
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PORTCON_PORTB_IE &= ~(0
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| PORTCON_PORTB_IE_B6_MASK
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| PORTCON_PORTB_IE_B7_MASK
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| PORTCON_PORTB_IE_B8_MASK
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| PORTCON_PORTB_IE_B9_MASK
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| PORTCON_PORTB_IE_B10_MASK
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| PORTCON_PORTB_IE_B15_MASK
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);
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PORTCON_PORTB_PU &= ~(0
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| PORTCON_PORTB_PU_B6_MASK
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| PORTCON_PORTB_PU_B9_MASK
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| PORTCON_PORTB_PU_B11_MASK
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| PORTCON_PORTB_PU_B14_MASK
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| PORTCON_PORTB_PU_B15_MASK
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);
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PORTCON_PORTB_PD &= ~(0
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| PORTCON_PORTB_PD_B6_MASK
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| PORTCON_PORTB_PD_B9_MASK
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| PORTCON_PORTB_PD_B11_MASK
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| PORTCON_PORTB_PD_B14_MASK
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| PORTCON_PORTB_PD_B15_MASK
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);
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PORTCON_PORTB_OD &= ~(0
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| PORTCON_PORTB_OD_B6_MASK
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| PORTCON_PORTB_OD_B9_MASK
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| PORTCON_PORTB_OD_B11_MASK
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| PORTCON_PORTB_OD_B15_MASK
|
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);
|
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|
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PORTCON_PORTB_OD |= 0
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| PORTCON_PORTB_OD_B14_ENABLE
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;
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|
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// PORT C pin configuration
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|
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PORTCON_PORTC_IE |= 0
|
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| PORTCON_PORTC_IE_C5_ENABLE
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;
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PORTCON_PORTC_IE &= ~(0
|
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| PORTCON_PORTC_IE_C0_MASK
|
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| PORTCON_PORTC_IE_C1_MASK
|
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| PORTCON_PORTC_IE_C2_MASK
|
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| PORTCON_PORTC_IE_C3_MASK
|
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| PORTCON_PORTC_IE_C4_MASK
|
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);
|
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|
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PORTCON_PORTC_PU |= 0
|
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| PORTCON_PORTC_PU_C5_ENABLE
|
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;
|
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PORTCON_PORTC_PU &= ~(0
|
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| PORTCON_PORTC_PU_C0_MASK
|
||||
| PORTCON_PORTC_PU_C1_MASK
|
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| PORTCON_PORTC_PU_C2_MASK
|
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| PORTCON_PORTC_PU_C3_MASK
|
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| PORTCON_PORTC_PU_C4_MASK
|
||||
);
|
||||
|
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PORTCON_PORTC_PD &= ~(0
|
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| PORTCON_PORTC_PD_C0_MASK
|
||||
| PORTCON_PORTC_PD_C1_MASK
|
||||
| PORTCON_PORTC_PD_C2_MASK
|
||||
| PORTCON_PORTC_PD_C3_MASK
|
||||
| PORTCON_PORTC_PD_C4_MASK
|
||||
| PORTCON_PORTC_PD_C5_MASK
|
||||
);
|
||||
|
||||
PORTCON_PORTC_OD &= ~(0
|
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| PORTCON_PORTC_OD_C0_MASK
|
||||
| PORTCON_PORTC_OD_C1_MASK
|
||||
| PORTCON_PORTC_OD_C2_MASK
|
||||
| PORTCON_PORTC_OD_C3_MASK
|
||||
| PORTCON_PORTC_OD_C4_MASK
|
||||
);
|
||||
PORTCON_PORTC_OD |= 0
|
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| PORTCON_PORTC_OD_C5_ENABLE
|
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;
|
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}
|
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|
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void BOARD_Init(void)
|
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{
|
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BOARD_PORTCON_Init();
|
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BOARD_GPIO_Init();
|
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//ADC_Init();
|
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ST7565_Init();
|
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//BK1080_Init(0, false);
|
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CRC_Init();
|
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}
|
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|
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26
board.h
Normal file
26
board.h
Normal file
@ -0,0 +1,26 @@
|
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/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
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|
||||
void BOARD_FLASH_Init(void);
|
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void BOARD_GPIO_Init(void);
|
||||
void BOARD_PORTCON_Init(void);
|
||||
void BOARD_Init(void);
|
||||
|
||||
#endif
|
||||
|
||||
88
bsp/dp32g030/crc.h
Normal file
88
bsp/dp32g030/crc.h
Normal file
@ -0,0 +1,88 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_CRC_H
|
||||
#define HARDWARE_DP32G030_CRC_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- CRC -------- */
|
||||
#define CRC_BASE_ADDR 0x40003000U
|
||||
#define CRC_BASE_SIZE 0x00000800U
|
||||
|
||||
#define CRC_CR_ADDR (CRC_BASE_ADDR + 0x0000U)
|
||||
#define CRC_CR (*(volatile uint32_t *)CRC_CR_ADDR)
|
||||
#define CRC_CR_CRC_EN_SHIFT 0
|
||||
#define CRC_CR_CRC_EN_WIDTH 1
|
||||
#define CRC_CR_CRC_EN_MASK (((1U << CRC_CR_CRC_EN_WIDTH) - 1U) << CRC_CR_CRC_EN_SHIFT)
|
||||
#define CRC_CR_CRC_EN_DISABLE (0U << CRC_CR_CRC_EN_SHIFT)
|
||||
#define CRC_CR_CRC_EN_ENABLE (1U << CRC_CR_CRC_EN_SHIFT)
|
||||
|
||||
#define CRC_CR_INPUT_REV_SHIFT 1
|
||||
#define CRC_CR_INPUT_REV_WIDTH 1
|
||||
#define CRC_CR_INPUT_REV_MASK (((1U << CRC_CR_INPUT_REV_WIDTH) - 1U) << CRC_CR_INPUT_REV_SHIFT)
|
||||
#define CRC_CR_INPUT_REV_NORMAL (0U << CRC_CR_INPUT_REV_SHIFT)
|
||||
#define CRC_CR_INPUT_REV_REVERSED (1U << CRC_CR_INPUT_REV_SHIFT)
|
||||
|
||||
#define CRC_CR_INPUT_INV_SHIFT 2
|
||||
#define CRC_CR_INPUT_INV_WIDTH 2
|
||||
#define CRC_CR_INPUT_INV_MASK (((1U << CRC_CR_INPUT_INV_WIDTH) - 1U) << CRC_CR_INPUT_INV_SHIFT)
|
||||
#define CRC_CR_INPUT_INV_NORMAL (0U << CRC_CR_INPUT_INV_SHIFT)
|
||||
#define CRC_CR_INPUT_INV_BIT_INVERTED (1U << CRC_CR_INPUT_INV_SHIFT)
|
||||
#define CRC_CR_INPUT_INV_BYTE_INVERTED (2U << CRC_CR_INPUT_INV_SHIFT)
|
||||
#define CRC_CR_INPUT_INV_BIT_BYTE_INVERTED (3U << CRC_CR_INPUT_INV_SHIFT)
|
||||
|
||||
#define CRC_CR_OUTPUT_REV_SHIFT 4
|
||||
#define CRC_CR_OUTPUT_REV_WIDTH 1
|
||||
#define CRC_CR_OUTPUT_REV_MASK (((1U << CRC_CR_OUTPUT_REV_WIDTH) - 1U) << CRC_CR_OUTPUT_REV_SHIFT)
|
||||
#define CRC_CR_OUTPUT_REV_NORMAL (0U << CRC_CR_OUTPUT_REV_SHIFT)
|
||||
#define CRC_CR_OUTPUT_REV_REVERSED (1U << CRC_CR_OUTPUT_REV_SHIFT)
|
||||
|
||||
#define CRC_CR_OUTPUT_INV_SHIFT 5
|
||||
#define CRC_CR_OUTPUT_INV_WIDTH 2
|
||||
#define CRC_CR_OUTPUT_INV_MASK (((1U << CRC_CR_OUTPUT_INV_WIDTH) - 1U) << CRC_CR_OUTPUT_INV_SHIFT)
|
||||
#define CRC_CR_OUTPUT_INV_NORMAL (0U << CRC_CR_OUTPUT_INV_SHIFT)
|
||||
#define CRC_CR_OUTPUT_INV_BIT_INVERTED (1U << CRC_CR_OUTPUT_INV_SHIFT)
|
||||
#define CRC_CR_OUTPUT_INV_BYTE_INVERTED (2U << CRC_CR_OUTPUT_INV_SHIFT)
|
||||
#define CRC_CR_OUTPUT_INV_BIT_BYTE_INVERTED (3U << CRC_CR_OUTPUT_INV_SHIFT)
|
||||
|
||||
#define CRC_CR_DATA_WIDTH_SHIFT 7
|
||||
#define CRC_CR_DATA_WIDTH_WIDTH 2
|
||||
#define CRC_CR_DATA_WIDTH_MASK (((1U << CRC_CR_DATA_WIDTH_WIDTH) - 1U) << CRC_CR_DATA_WIDTH_SHIFT)
|
||||
#define CRC_CR_DATA_WIDTH_32 (0U << CRC_CR_DATA_WIDTH_SHIFT)
|
||||
#define CRC_CR_DATA_WIDTH_16 (1U << CRC_CR_DATA_WIDTH_SHIFT)
|
||||
#define CRC_CR_DATA_WIDTH_8 (2U << CRC_CR_DATA_WIDTH_SHIFT)
|
||||
|
||||
#define CRC_CR_CRC_SEL_SHIFT 9
|
||||
#define CRC_CR_CRC_SEL_WIDTH 2
|
||||
#define CRC_CR_CRC_SEL_MASK (((1U << CRC_CR_CRC_SEL_WIDTH) - 1U) << CRC_CR_CRC_SEL_SHIFT)
|
||||
#define CRC_CR_CRC_SEL_CRC_16_CCITT (0U << CRC_CR_CRC_SEL_SHIFT)
|
||||
#define CRC_CR_CRC_SEL_CRC_8_ATM (1U << CRC_CR_CRC_SEL_SHIFT)
|
||||
#define CRC_CR_CRC_SEL_CRC_16 (2U << CRC_CR_CRC_SEL_SHIFT)
|
||||
#define CRC_CR_CRC_SEL_CRC_32_IEEE802_3 (3U << CRC_CR_CRC_SEL_SHIFT)
|
||||
|
||||
#define CRC_IV_ADDR (CRC_BASE_ADDR + 0x0004U)
|
||||
#define CRC_IV (*(volatile uint32_t *)CRC_IV_ADDR)
|
||||
#define CRC_DATAIN_ADDR (CRC_BASE_ADDR + 0x0008U)
|
||||
#define CRC_DATAIN (*(volatile uint32_t *)CRC_DATAIN_ADDR)
|
||||
#define CRC_DATAOUT_ADDR (CRC_BASE_ADDR + 0x000CU)
|
||||
#define CRC_DATAOUT (*(volatile uint32_t *)CRC_DATAOUT_ADDR)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
248
bsp/dp32g030/dma.h
Normal file
248
bsp/dp32g030/dma.h
Normal file
@ -0,0 +1,248 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_DMA_H
|
||||
#define HARDWARE_DP32G030_DMA_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- DMA -------- */
|
||||
#define DMA_BASE_ADDR 0x40001000U
|
||||
#define DMA_BASE_SIZE 0x00000100U
|
||||
|
||||
#define DMA_CTR_ADDR (DMA_BASE_ADDR + 0x0000U)
|
||||
#define DMA_CTR (*(volatile uint32_t *)DMA_CTR_ADDR)
|
||||
#define DMA_CTR_DMAEN_SHIFT 0
|
||||
#define DMA_CTR_DMAEN_WIDTH 1
|
||||
#define DMA_CTR_DMAEN_MASK (((1U << DMA_CTR_DMAEN_WIDTH) - 1U) << DMA_CTR_DMAEN_SHIFT)
|
||||
#define DMA_CTR_DMAEN_DISABLE (0U << DMA_CTR_DMAEN_SHIFT)
|
||||
#define DMA_CTR_DMAEN_ENABLE (1U << DMA_CTR_DMAEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_ADDR (DMA_BASE_ADDR + 0x0004U)
|
||||
#define DMA_INTEN (*(volatile uint32_t *)DMA_INTEN_ADDR)
|
||||
#define DMA_INTEN_CH0_TC_INTEN_SHIFT 0
|
||||
#define DMA_INTEN_CH0_TC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH0_TC_INTEN_MASK (((1U << DMA_INTEN_CH0_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH0_TC_INTEN_DISABLE (0U << DMA_INTEN_CH0_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH0_TC_INTEN_ENABLE (1U << DMA_INTEN_CH0_TC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH1_TC_INTEN_SHIFT 1
|
||||
#define DMA_INTEN_CH1_TC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH1_TC_INTEN_MASK (((1U << DMA_INTEN_CH1_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH1_TC_INTEN_DISABLE (0U << DMA_INTEN_CH1_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH1_TC_INTEN_ENABLE (1U << DMA_INTEN_CH1_TC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH2_TC_INTEN_SHIFT 2
|
||||
#define DMA_INTEN_CH2_TC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH2_TC_INTEN_MASK (((1U << DMA_INTEN_CH2_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH2_TC_INTEN_DISABLE (0U << DMA_INTEN_CH2_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH2_TC_INTEN_ENABLE (1U << DMA_INTEN_CH2_TC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH3_TC_INTEN_SHIFT 3
|
||||
#define DMA_INTEN_CH3_TC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH3_TC_INTEN_MASK (((1U << DMA_INTEN_CH3_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH3_TC_INTEN_DISABLE (0U << DMA_INTEN_CH3_TC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH3_TC_INTEN_ENABLE (1U << DMA_INTEN_CH3_TC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH0_THC_INTEN_SHIFT 8
|
||||
#define DMA_INTEN_CH0_THC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH0_THC_INTEN_MASK (((1U << DMA_INTEN_CH0_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH0_THC_INTEN_DISABLE (0U << DMA_INTEN_CH0_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH0_THC_INTEN_ENABLE (1U << DMA_INTEN_CH0_THC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH1_THC_INTEN_SHIFT 9
|
||||
#define DMA_INTEN_CH1_THC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH1_THC_INTEN_MASK (((1U << DMA_INTEN_CH1_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH1_THC_INTEN_DISABLE (0U << DMA_INTEN_CH1_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH1_THC_INTEN_ENABLE (1U << DMA_INTEN_CH1_THC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH2_THC_INTEN_SHIFT 10
|
||||
#define DMA_INTEN_CH2_THC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH2_THC_INTEN_MASK (((1U << DMA_INTEN_CH2_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH2_THC_INTEN_DISABLE (0U << DMA_INTEN_CH2_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH2_THC_INTEN_ENABLE (1U << DMA_INTEN_CH2_THC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTEN_CH3_THC_INTEN_SHIFT 11
|
||||
#define DMA_INTEN_CH3_THC_INTEN_WIDTH 1
|
||||
#define DMA_INTEN_CH3_THC_INTEN_MASK (((1U << DMA_INTEN_CH3_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH3_THC_INTEN_DISABLE (0U << DMA_INTEN_CH3_THC_INTEN_SHIFT)
|
||||
#define DMA_INTEN_CH3_THC_INTEN_ENABLE (1U << DMA_INTEN_CH3_THC_INTEN_SHIFT)
|
||||
|
||||
#define DMA_INTST_ADDR (DMA_BASE_ADDR + 0x0008U)
|
||||
#define DMA_INTST (*(volatile uint32_t *)DMA_INTST_ADDR)
|
||||
#define DMA_INTST_CH0_TC_INTST_SHIFT 0
|
||||
#define DMA_INTST_CH0_TC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH0_TC_INTST_MASK (((1U << DMA_INTST_CH0_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH0_TC_INTST_NOT_SET (0U << DMA_INTST_CH0_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH0_TC_INTST_SET (1U << DMA_INTST_CH0_TC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH1_TC_INTST_SHIFT 1
|
||||
#define DMA_INTST_CH1_TC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH1_TC_INTST_MASK (((1U << DMA_INTST_CH1_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH1_TC_INTST_NOT_SET (0U << DMA_INTST_CH1_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH1_TC_INTST_SET (1U << DMA_INTST_CH1_TC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH2_TC_INTST_SHIFT 2
|
||||
#define DMA_INTST_CH2_TC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH2_TC_INTST_MASK (((1U << DMA_INTST_CH2_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH2_TC_INTST_NOT_SET (0U << DMA_INTST_CH2_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH2_TC_INTST_SET (1U << DMA_INTST_CH2_TC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH3_TC_INTST_SHIFT 3
|
||||
#define DMA_INTST_CH3_TC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH3_TC_INTST_MASK (((1U << DMA_INTST_CH3_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH3_TC_INTST_NOT_SET (0U << DMA_INTST_CH3_TC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH3_TC_INTST_SET (1U << DMA_INTST_CH3_TC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH0_THC_INTST_SHIFT 8
|
||||
#define DMA_INTST_CH0_THC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH0_THC_INTST_MASK (((1U << DMA_INTST_CH0_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH0_THC_INTST_NOT_SET (0U << DMA_INTST_CH0_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH0_THC_INTST_SET (1U << DMA_INTST_CH0_THC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH1_THC_INTST_SHIFT 9
|
||||
#define DMA_INTST_CH1_THC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH1_THC_INTST_MASK (((1U << DMA_INTST_CH1_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH1_THC_INTST_NOT_SET (0U << DMA_INTST_CH1_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH1_THC_INTST_SET (1U << DMA_INTST_CH1_THC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH2_THC_INTST_SHIFT 10
|
||||
#define DMA_INTST_CH2_THC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH2_THC_INTST_MASK (((1U << DMA_INTST_CH2_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH2_THC_INTST_NOT_SET (0U << DMA_INTST_CH2_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH2_THC_INTST_SET (1U << DMA_INTST_CH2_THC_INTST_SHIFT)
|
||||
|
||||
#define DMA_INTST_CH3_THC_INTST_SHIFT 11
|
||||
#define DMA_INTST_CH3_THC_INTST_WIDTH 1
|
||||
#define DMA_INTST_CH3_THC_INTST_MASK (((1U << DMA_INTST_CH3_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH3_THC_INTST_NOT_SET (0U << DMA_INTST_CH3_THC_INTST_SHIFT)
|
||||
#define DMA_INTST_CH3_THC_INTST_SET (1U << DMA_INTST_CH3_THC_INTST_SHIFT)
|
||||
|
||||
/* -------- DMA_CH0 -------- */
|
||||
#define DMA_CH0_BASE_ADDR 0x40001100U
|
||||
#define DMA_CH0_BASE_SIZE 0x00000020U
|
||||
#define DMA_CH0 ((volatile DMA_Channel_t *)DMA_CH0_BASE_ADDR)
|
||||
|
||||
/* -------- DMA_CH1 -------- */
|
||||
#define DMA_CH1_BASE_ADDR 0x40001120U
|
||||
#define DMA_CH1_BASE_SIZE 0x00000020U
|
||||
#define DMA_CH1 ((volatile DMA_Channel_t *)DMA_CH1_BASE_ADDR)
|
||||
|
||||
/* -------- DMA_CH2 -------- */
|
||||
#define DMA_CH2_BASE_ADDR 0x40001140U
|
||||
#define DMA_CH2_BASE_SIZE 0x00000020U
|
||||
#define DMA_CH2 ((volatile DMA_Channel_t *)DMA_CH2_BASE_ADDR)
|
||||
|
||||
/* -------- DMA_CH3 -------- */
|
||||
#define DMA_CH3_BASE_ADDR 0x40001160U
|
||||
#define DMA_CH3_BASE_SIZE 0x00000020U
|
||||
#define DMA_CH3 ((volatile DMA_Channel_t *)DMA_CH3_BASE_ADDR)
|
||||
|
||||
/* -------- DMA_CH -------- */
|
||||
|
||||
typedef struct {
|
||||
uint32_t CTR;
|
||||
uint32_t MOD;
|
||||
uint32_t MSADDR;
|
||||
uint32_t MDADDR;
|
||||
uint32_t ST;
|
||||
} DMA_Channel_t;
|
||||
|
||||
#define DMA_CH_CTR_CH_EN_SHIFT 0
|
||||
#define DMA_CH_CTR_CH_EN_WIDTH 1
|
||||
#define DMA_CH_CTR_CH_EN_MASK (((1U << DMA_CH_CTR_CH_EN_WIDTH) - 1U) << DMA_CH_CTR_CH_EN_SHIFT)
|
||||
#define DMA_CH_CTR_CH_EN_DISABLE (0U << DMA_CH_CTR_CH_EN_SHIFT)
|
||||
#define DMA_CH_CTR_CH_EN_ENABLE (1U << DMA_CH_CTR_CH_EN_SHIFT)
|
||||
|
||||
#define DMA_CH_CTR_LENGTH_SHIFT 1
|
||||
#define DMA_CH_CTR_LENGTH_WIDTH 12
|
||||
#define DMA_CH_CTR_LENGTH_MASK (((1U << DMA_CH_CTR_LENGTH_WIDTH) - 1U) << DMA_CH_CTR_LENGTH_SHIFT)
|
||||
#define DMA_CH_CTR_LOOP_SHIFT 13
|
||||
#define DMA_CH_CTR_LOOP_WIDTH 1
|
||||
#define DMA_CH_CTR_LOOP_MASK (((1U << DMA_CH_CTR_LOOP_WIDTH) - 1U) << DMA_CH_CTR_LOOP_SHIFT)
|
||||
#define DMA_CH_CTR_LOOP_DISABLE (0U << DMA_CH_CTR_LOOP_SHIFT)
|
||||
#define DMA_CH_CTR_LOOP_ENABLE (1U << DMA_CH_CTR_LOOP_SHIFT)
|
||||
|
||||
#define DMA_CH_CTR_PRI_SHIFT 14
|
||||
#define DMA_CH_CTR_PRI_WIDTH 2
|
||||
#define DMA_CH_CTR_PRI_MASK (((1U << DMA_CH_CTR_PRI_WIDTH) - 1U) << DMA_CH_CTR_PRI_SHIFT)
|
||||
#define DMA_CH_CTR_PRI_LOW (0U << DMA_CH_CTR_PRI_SHIFT)
|
||||
#define DMA_CH_CTR_PRI_MEDIUM (1U << DMA_CH_CTR_PRI_SHIFT)
|
||||
#define DMA_CH_CTR_PRI_HIGH (2U << DMA_CH_CTR_PRI_SHIFT)
|
||||
#define DMA_CH_CTR_PRI_HIGHEST (3U << DMA_CH_CTR_PRI_SHIFT)
|
||||
|
||||
#define DMA_CH_CTR_SWREQ_SHIFT 16
|
||||
#define DMA_CH_CTR_SWREQ_WIDTH 1
|
||||
#define DMA_CH_CTR_SWREQ_MASK (((1U << DMA_CH_CTR_SWREQ_WIDTH) - 1U) << DMA_CH_CTR_SWREQ_SHIFT)
|
||||
#define DMA_CH_CTR_SWREQ_SET (1U << DMA_CH_CTR_SWREQ_SHIFT)
|
||||
|
||||
#define DMA_CH_MOD_MS_ADDMOD_SHIFT 0
|
||||
#define DMA_CH_MOD_MS_ADDMOD_WIDTH 1
|
||||
#define DMA_CH_MOD_MS_ADDMOD_MASK (((1U << DMA_CH_MOD_MS_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MS_ADDMOD_SHIFT)
|
||||
#define DMA_CH_MOD_MS_ADDMOD_NONE (0U << DMA_CH_MOD_MS_ADDMOD_SHIFT)
|
||||
#define DMA_CH_MOD_MS_ADDMOD_INCREMENT (1U << DMA_CH_MOD_MS_ADDMOD_SHIFT)
|
||||
|
||||
#define DMA_CH_MOD_MS_SIZE_SHIFT 1
|
||||
#define DMA_CH_MOD_MS_SIZE_WIDTH 2
|
||||
#define DMA_CH_MOD_MS_SIZE_MASK (((1U << DMA_CH_MOD_MS_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MS_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SIZE_8BIT (0U << DMA_CH_MOD_MS_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SIZE_16BIT (1U << DMA_CH_MOD_MS_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SIZE_32BIT (2U << DMA_CH_MOD_MS_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SIZE_KEEP (3U << DMA_CH_MOD_MS_SIZE_SHIFT)
|
||||
|
||||
#define DMA_CH_MOD_MS_SEL_SHIFT 3
|
||||
#define DMA_CH_MOD_MS_SEL_WIDTH 3
|
||||
#define DMA_CH_MOD_MS_SEL_MASK (((1U << DMA_CH_MOD_MS_SEL_WIDTH) - 1U) << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_SRAM (0U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS0 (1U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS1 (2U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS2 (3U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS3 (4U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS4 (5U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS5 (6U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MS_SEL_HSREQ_MS6 (7U << DMA_CH_MOD_MS_SEL_SHIFT)
|
||||
|
||||
#define DMA_CH_MOD_MD_ADDMOD_SHIFT 8
|
||||
#define DMA_CH_MOD_MD_ADDMOD_WIDTH 1
|
||||
#define DMA_CH_MOD_MD_ADDMOD_MASK (((1U << DMA_CH_MOD_MD_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MD_ADDMOD_SHIFT)
|
||||
#define DMA_CH_MOD_MD_ADDMOD_NONE (0U << DMA_CH_MOD_MD_ADDMOD_SHIFT)
|
||||
#define DMA_CH_MOD_MD_ADDMOD_INCREMENT (1U << DMA_CH_MOD_MD_ADDMOD_SHIFT)
|
||||
|
||||
#define DMA_CH_MOD_MD_SIZE_SHIFT 9
|
||||
#define DMA_CH_MOD_MD_SIZE_WIDTH 2
|
||||
#define DMA_CH_MOD_MD_SIZE_MASK (((1U << DMA_CH_MOD_MD_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MD_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SIZE_8BIT (0U << DMA_CH_MOD_MD_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SIZE_16BIT (1U << DMA_CH_MOD_MD_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SIZE_32BIT (2U << DMA_CH_MOD_MD_SIZE_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SIZE_KEEP (3U << DMA_CH_MOD_MD_SIZE_SHIFT)
|
||||
|
||||
#define DMA_CH_MOD_MD_SEL_SHIFT 11
|
||||
#define DMA_CH_MOD_MD_SEL_WIDTH 3
|
||||
#define DMA_CH_MOD_MD_SEL_MASK (((1U << DMA_CH_MOD_MD_SEL_WIDTH) - 1U) << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_SRAM (0U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS0 (1U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS1 (2U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS2 (3U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS3 (4U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS4 (5U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS5 (6U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
#define DMA_CH_MOD_MD_SEL_HSREQ_MS6 (7U << DMA_CH_MOD_MD_SEL_SHIFT)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
140
bsp/dp32g030/flash.h
Normal file
140
bsp/dp32g030/flash.h
Normal file
@ -0,0 +1,140 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_FLASH_H
|
||||
#define HARDWARE_DP32G030_FLASH_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- FLASH -------- */
|
||||
#define FLASH_BASE_ADDR 0x4006F000U
|
||||
#define FLASH_BASE_SIZE 0x00000800U
|
||||
|
||||
#define FLASH_CFG_ADDR (FLASH_BASE_ADDR + 0x0000U)
|
||||
#define FLASH_CFG (*(volatile uint32_t *)FLASH_CFG_ADDR)
|
||||
#define FLASH_CFG_READ_MD_SHIFT 0
|
||||
#define FLASH_CFG_READ_MD_WIDTH 1
|
||||
#define FLASH_CFG_READ_MD_MASK (((1U << FLASH_CFG_READ_MD_WIDTH) - 1U) << FLASH_CFG_READ_MD_SHIFT)
|
||||
#define FLASH_CFG_READ_MD_1_CYCLE (0U << FLASH_CFG_READ_MD_SHIFT)
|
||||
#define FLASH_CFG_READ_MD_2_CYCLE (1U << FLASH_CFG_READ_MD_SHIFT)
|
||||
|
||||
#define FLASH_CFG_NVR_SEL_SHIFT 1
|
||||
#define FLASH_CFG_NVR_SEL_WIDTH 1
|
||||
#define FLASH_CFG_NVR_SEL_MASK (((1U << FLASH_CFG_NVR_SEL_WIDTH) - 1U) << FLASH_CFG_NVR_SEL_SHIFT)
|
||||
#define FLASH_CFG_NVR_SEL_MAIN (0U << FLASH_CFG_NVR_SEL_SHIFT)
|
||||
#define FLASH_CFG_NVR_SEL_NVR (1U << FLASH_CFG_NVR_SEL_SHIFT)
|
||||
|
||||
#define FLASH_CFG_MODE_SHIFT 2
|
||||
#define FLASH_CFG_MODE_WIDTH 3
|
||||
#define FLASH_CFG_MODE_MASK (((1U << FLASH_CFG_MODE_WIDTH) - 1U) << FLASH_CFG_MODE_SHIFT)
|
||||
#define FLASH_CFG_MODE_READ_AHB (0U << FLASH_CFG_MODE_SHIFT)
|
||||
#define FLASH_CFG_MODE_PROGRAM (1U << FLASH_CFG_MODE_SHIFT)
|
||||
#define FLASH_CFG_MODE_ERASE (2U << FLASH_CFG_MODE_SHIFT)
|
||||
#define FLASH_CFG_MODE_READ_APB (5U << FLASH_CFG_MODE_SHIFT)
|
||||
|
||||
#define FLASH_CFG_DEEP_PD_SHIFT 31
|
||||
#define FLASH_CFG_DEEP_PD_WIDTH 1
|
||||
#define FLASH_CFG_DEEP_PD_MASK (((1U << FLASH_CFG_DEEP_PD_WIDTH) - 1U) << FLASH_CFG_DEEP_PD_SHIFT)
|
||||
#define FLASH_CFG_DEEP_PD_NORMAL (0U << FLASH_CFG_DEEP_PD_SHIFT)
|
||||
#define FLASH_CFG_DEEP_PD_LOW_POWER (1U << FLASH_CFG_DEEP_PD_SHIFT)
|
||||
|
||||
#define FLASH_ADDR_ADDR (FLASH_BASE_ADDR + 0x0004U)
|
||||
#define FLASH_ADDR (*(volatile uint32_t *)FLASH_ADDR_ADDR)
|
||||
#define FLASH_WDATA_ADDR (FLASH_BASE_ADDR + 0x0008U)
|
||||
#define FLASH_WDATA (*(volatile uint32_t *)FLASH_WDATA_ADDR)
|
||||
#define FLASH_RDATA_ADDR (FLASH_BASE_ADDR + 0x000CU)
|
||||
#define FLASH_RDATA (*(volatile uint32_t *)FLASH_RDATA_ADDR)
|
||||
|
||||
#define FLASH_START_ADDR (FLASH_BASE_ADDR + 0x0010U)
|
||||
#define FLASH_START (*(volatile uint32_t *)FLASH_START_ADDR)
|
||||
#define FLASH_START_START_SHIFT 0
|
||||
#define FLASH_START_START_WIDTH 1
|
||||
#define FLASH_START_START_MASK (((1U << FLASH_START_START_WIDTH) - 1U) << FLASH_START_START_SHIFT)
|
||||
#define FLASH_START_START_START (1U << FLASH_START_START_SHIFT)
|
||||
|
||||
#define FLASH_ST_ADDR (FLASH_BASE_ADDR + 0x0014U)
|
||||
#define FLASH_ST (*(volatile uint32_t *)FLASH_ST_ADDR)
|
||||
#define FLASH_ST_INIT_BUSY_SHIFT 0
|
||||
#define FLASH_ST_INIT_BUSY_WIDTH 1
|
||||
#define FLASH_ST_INIT_BUSY_MASK (((1U << FLASH_ST_INIT_BUSY_WIDTH) - 1U) << FLASH_ST_INIT_BUSY_SHIFT)
|
||||
#define FLASH_ST_INIT_BUSY_COMPLETE (0U << FLASH_ST_INIT_BUSY_SHIFT)
|
||||
#define FLASH_ST_INIT_BUSY_BUSY (1U << FLASH_ST_INIT_BUSY_SHIFT)
|
||||
|
||||
#define FLASH_ST_BUSY_SHIFT 1
|
||||
#define FLASH_ST_BUSY_WIDTH 1
|
||||
#define FLASH_ST_BUSY_MASK (((1U << FLASH_ST_BUSY_WIDTH) - 1U) << FLASH_ST_BUSY_SHIFT)
|
||||
#define FLASH_ST_BUSY_READY (0U << FLASH_ST_BUSY_SHIFT)
|
||||
#define FLASH_ST_BUSY_BUSY (1U << FLASH_ST_BUSY_SHIFT)
|
||||
|
||||
#define FLASH_ST_PROG_BUF_EMPTY_SHIFT 2
|
||||
#define FLASH_ST_PROG_BUF_EMPTY_WIDTH 1
|
||||
#define FLASH_ST_PROG_BUF_EMPTY_MASK (((1U << FLASH_ST_PROG_BUF_EMPTY_WIDTH) - 1U) << FLASH_ST_PROG_BUF_EMPTY_SHIFT)
|
||||
#define FLASH_ST_PROG_BUF_EMPTY_NOT_EMPTY (0U << FLASH_ST_PROG_BUF_EMPTY_SHIFT)
|
||||
#define FLASH_ST_PROG_BUF_EMPTY_EMPTY (1U << FLASH_ST_PROG_BUF_EMPTY_SHIFT)
|
||||
|
||||
#define FLASH_LOCK_ADDR (FLASH_BASE_ADDR + 0x0018U)
|
||||
#define FLASH_LOCK (*(volatile uint32_t *)FLASH_LOCK_ADDR)
|
||||
#define FLASH_LOCK_LOCK_SHIFT 0
|
||||
#define FLASH_LOCK_LOCK_WIDTH 8
|
||||
#define FLASH_LOCK_LOCK_MASK (((1U << FLASH_LOCK_LOCK_WIDTH) - 1U) << FLASH_LOCK_LOCK_SHIFT)
|
||||
#define FLASH_LOCK_LOCK_LOCK (85U << FLASH_LOCK_LOCK_SHIFT)
|
||||
|
||||
#define FLASH_UNLOCK_ADDR (FLASH_BASE_ADDR + 0x001CU)
|
||||
#define FLASH_UNLOCK (*(volatile uint32_t *)FLASH_UNLOCK_ADDR)
|
||||
#define FLASH_UNLOCK_UNLOCK_SHIFT 0
|
||||
#define FLASH_UNLOCK_UNLOCK_WIDTH 8
|
||||
#define FLASH_UNLOCK_UNLOCK_MASK (((1U << FLASH_UNLOCK_UNLOCK_WIDTH) - 1U) << FLASH_UNLOCK_UNLOCK_SHIFT)
|
||||
#define FLASH_UNLOCK_UNLOCK_UNLOCK (170U << FLASH_UNLOCK_UNLOCK_SHIFT)
|
||||
|
||||
#define FLASH_MASK_ADDR (FLASH_BASE_ADDR + 0x0020U)
|
||||
#define FLASH_MASK (*(volatile uint32_t *)FLASH_MASK_ADDR)
|
||||
#define FLASH_MASK_SEL_SHIFT 0
|
||||
#define FLASH_MASK_SEL_WIDTH 2
|
||||
#define FLASH_MASK_SEL_MASK (((1U << FLASH_MASK_SEL_WIDTH) - 1U) << FLASH_MASK_SEL_SHIFT)
|
||||
#define FLASH_MASK_SEL_NONE (0U << FLASH_MASK_SEL_SHIFT)
|
||||
#define FLASH_MASK_SEL_2KB (1U << FLASH_MASK_SEL_SHIFT)
|
||||
#define FLASH_MASK_SEL_4KB (2U << FLASH_MASK_SEL_SHIFT)
|
||||
#define FLASH_MASK_SEL_8KB (3U << FLASH_MASK_SEL_SHIFT)
|
||||
|
||||
#define FLASH_MASK_LOCK_SHIFT 2
|
||||
#define FLASH_MASK_LOCK_WIDTH 1
|
||||
#define FLASH_MASK_LOCK_MASK (((1U << FLASH_MASK_LOCK_WIDTH) - 1U) << FLASH_MASK_LOCK_SHIFT)
|
||||
#define FLASH_MASK_LOCK_NOT_SET (0U << FLASH_MASK_LOCK_SHIFT)
|
||||
#define FLASH_MASK_LOCK_SET (1U << FLASH_MASK_LOCK_SHIFT)
|
||||
|
||||
#define FLASH_ERASETIME_ADDR (FLASH_BASE_ADDR + 0x0024U)
|
||||
#define FLASH_ERASETIME (*(volatile uint32_t *)FLASH_ERASETIME_ADDR)
|
||||
#define FLASH_ERASETIME_TERASE_SHIFT 0
|
||||
#define FLASH_ERASETIME_TERASE_WIDTH 19
|
||||
#define FLASH_ERASETIME_TERASE_MASK (((1U << FLASH_ERASETIME_TERASE_WIDTH) - 1U) << FLASH_ERASETIME_TERASE_SHIFT)
|
||||
#define FLASH_ERASETIME_TRCV_SHIFT 19
|
||||
#define FLASH_ERASETIME_TRCV_WIDTH 12
|
||||
#define FLASH_ERASETIME_TRCV_MASK (((1U << FLASH_ERASETIME_TRCV_WIDTH) - 1U) << FLASH_ERASETIME_TRCV_SHIFT)
|
||||
|
||||
#define FLASH_PROGTIME_ADDR (FLASH_BASE_ADDR + 0x0028U)
|
||||
#define FLASH_PROGTIME (*(volatile uint32_t *)FLASH_PROGTIME_ADDR)
|
||||
#define FLASH_PROGTIME_TPROG_SHIFT 0
|
||||
#define FLASH_PROGTIME_TPROG_WIDTH 11
|
||||
#define FLASH_PROGTIME_TPROG_MASK (((1U << FLASH_PROGTIME_TPROG_WIDTH) - 1U) << FLASH_PROGTIME_TPROG_SHIFT)
|
||||
#define FLASH_PROGTIME_TPGS_SHIFT 11
|
||||
#define FLASH_PROGTIME_TPGS_WIDTH 11
|
||||
#define FLASH_PROGTIME_TPGS_MASK (((1U << FLASH_PROGTIME_TPGS_WIDTH) - 1U) << FLASH_PROGTIME_TPGS_SHIFT)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
144
bsp/dp32g030/gpio.h
Normal file
144
bsp/dp32g030/gpio.h
Normal file
@ -0,0 +1,144 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_GPIO_H
|
||||
#define HARDWARE_DP32G030_GPIO_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- GPIOA -------- */
|
||||
#define GPIOA_BASE_ADDR 0x40060000U
|
||||
#define GPIOA_BASE_SIZE 0x00000800U
|
||||
#define GPIOA ((volatile GPIO_Bank_t *)GPIOA_BASE_ADDR)
|
||||
|
||||
/* -------- GPIOB -------- */
|
||||
#define GPIOB_BASE_ADDR 0x40060800U
|
||||
#define GPIOB_BASE_SIZE 0x00000800U
|
||||
#define GPIOB ((volatile GPIO_Bank_t *)GPIOB_BASE_ADDR)
|
||||
|
||||
/* -------- GPIOC -------- */
|
||||
#define GPIOC_BASE_ADDR 0x40061000U
|
||||
#define GPIOC_BASE_SIZE 0x00000800U
|
||||
#define GPIOC ((volatile GPIO_Bank_t *)GPIOC_BASE_ADDR)
|
||||
|
||||
/* -------- GPIO -------- */
|
||||
|
||||
typedef struct {
|
||||
uint32_t DATA;
|
||||
uint32_t DIR;
|
||||
} GPIO_Bank_t;
|
||||
|
||||
#define GPIO_DIR_0_SHIFT 0
|
||||
#define GPIO_DIR_0_WIDTH 1
|
||||
#define GPIO_DIR_0_MASK (((1U << GPIO_DIR_0_WIDTH) - 1U) << GPIO_DIR_0_SHIFT)
|
||||
#define GPIO_DIR_0_INPUT (0U << GPIO_DIR_0_SHIFT)
|
||||
#define GPIO_DIR_0_OUTPUT (1U << GPIO_DIR_0_SHIFT)
|
||||
|
||||
#define GPIO_DIR_1_SHIFT 1
|
||||
#define GPIO_DIR_1_WIDTH 1
|
||||
#define GPIO_DIR_1_MASK (((1U << GPIO_DIR_1_WIDTH) - 1U) << GPIO_DIR_1_SHIFT)
|
||||
#define GPIO_DIR_1_INPUT (0U << GPIO_DIR_1_SHIFT)
|
||||
#define GPIO_DIR_1_OUTPUT (1U << GPIO_DIR_1_SHIFT)
|
||||
|
||||
#define GPIO_DIR_2_SHIFT 2
|
||||
#define GPIO_DIR_2_WIDTH 1
|
||||
#define GPIO_DIR_2_MASK (((1U << GPIO_DIR_2_WIDTH) - 1U) << GPIO_DIR_2_SHIFT)
|
||||
#define GPIO_DIR_2_INPUT (0U << GPIO_DIR_2_SHIFT)
|
||||
#define GPIO_DIR_2_OUTPUT (1U << GPIO_DIR_2_SHIFT)
|
||||
|
||||
#define GPIO_DIR_3_SHIFT 3
|
||||
#define GPIO_DIR_3_WIDTH 1
|
||||
#define GPIO_DIR_3_MASK (((1U << GPIO_DIR_3_WIDTH) - 1U) << GPIO_DIR_3_SHIFT)
|
||||
#define GPIO_DIR_3_INPUT (0U << GPIO_DIR_3_SHIFT)
|
||||
#define GPIO_DIR_3_OUTPUT (1U << GPIO_DIR_3_SHIFT)
|
||||
|
||||
#define GPIO_DIR_4_SHIFT 4
|
||||
#define GPIO_DIR_4_WIDTH 1
|
||||
#define GPIO_DIR_4_MASK (((1U << GPIO_DIR_4_WIDTH) - 1U) << GPIO_DIR_4_SHIFT)
|
||||
#define GPIO_DIR_4_INPUT (0U << GPIO_DIR_4_SHIFT)
|
||||
#define GPIO_DIR_4_OUTPUT (1U << GPIO_DIR_4_SHIFT)
|
||||
|
||||
#define GPIO_DIR_5_SHIFT 5
|
||||
#define GPIO_DIR_5_WIDTH 1
|
||||
#define GPIO_DIR_5_MASK (((1U << GPIO_DIR_5_WIDTH) - 1U) << GPIO_DIR_5_SHIFT)
|
||||
#define GPIO_DIR_5_INPUT (0U << GPIO_DIR_5_SHIFT)
|
||||
#define GPIO_DIR_5_OUTPUT (1U << GPIO_DIR_5_SHIFT)
|
||||
|
||||
#define GPIO_DIR_6_SHIFT 6
|
||||
#define GPIO_DIR_6_WIDTH 1
|
||||
#define GPIO_DIR_6_MASK (((1U << GPIO_DIR_6_WIDTH) - 1U) << GPIO_DIR_6_SHIFT)
|
||||
#define GPIO_DIR_6_INPUT (0U << GPIO_DIR_6_SHIFT)
|
||||
#define GPIO_DIR_6_OUTPUT (1U << GPIO_DIR_6_SHIFT)
|
||||
|
||||
#define GPIO_DIR_7_SHIFT 7
|
||||
#define GPIO_DIR_7_WIDTH 1
|
||||
#define GPIO_DIR_7_MASK (((1U << GPIO_DIR_7_WIDTH) - 1U) << GPIO_DIR_7_SHIFT)
|
||||
#define GPIO_DIR_7_INPUT (0U << GPIO_DIR_7_SHIFT)
|
||||
#define GPIO_DIR_7_OUTPUT (1U << GPIO_DIR_7_SHIFT)
|
||||
|
||||
#define GPIO_DIR_8_SHIFT 8
|
||||
#define GPIO_DIR_8_WIDTH 1
|
||||
#define GPIO_DIR_8_MASK (((1U << GPIO_DIR_8_WIDTH) - 1U) << GPIO_DIR_8_SHIFT)
|
||||
#define GPIO_DIR_8_INPUT (0U << GPIO_DIR_8_SHIFT)
|
||||
#define GPIO_DIR_8_OUTPUT (1U << GPIO_DIR_8_SHIFT)
|
||||
|
||||
#define GPIO_DIR_9_SHIFT 9
|
||||
#define GPIO_DIR_9_WIDTH 1
|
||||
#define GPIO_DIR_9_MASK (((1U << GPIO_DIR_9_WIDTH) - 1U) << GPIO_DIR_9_SHIFT)
|
||||
#define GPIO_DIR_9_INPUT (0U << GPIO_DIR_9_SHIFT)
|
||||
#define GPIO_DIR_9_OUTPUT (1U << GPIO_DIR_9_SHIFT)
|
||||
|
||||
#define GPIO_DIR_10_SHIFT 10
|
||||
#define GPIO_DIR_10_WIDTH 1
|
||||
#define GPIO_DIR_10_MASK (((1U << GPIO_DIR_10_WIDTH) - 1U) << GPIO_DIR_10_SHIFT)
|
||||
#define GPIO_DIR_10_INPUT (0U << GPIO_DIR_10_SHIFT)
|
||||
#define GPIO_DIR_10_OUTPUT (1U << GPIO_DIR_10_SHIFT)
|
||||
|
||||
#define GPIO_DIR_11_SHIFT 11
|
||||
#define GPIO_DIR_11_WIDTH 1
|
||||
#define GPIO_DIR_11_MASK (((1U << GPIO_DIR_11_WIDTH) - 1U) << GPIO_DIR_11_SHIFT)
|
||||
#define GPIO_DIR_11_INPUT (0U << GPIO_DIR_11_SHIFT)
|
||||
#define GPIO_DIR_11_OUTPUT (1U << GPIO_DIR_11_SHIFT)
|
||||
|
||||
#define GPIO_DIR_12_SHIFT 12
|
||||
#define GPIO_DIR_12_WIDTH 1
|
||||
#define GPIO_DIR_12_MASK (((1U << GPIO_DIR_12_WIDTH) - 1U) << GPIO_DIR_12_SHIFT)
|
||||
#define GPIO_DIR_12_INPUT (0U << GPIO_DIR_12_SHIFT)
|
||||
#define GPIO_DIR_12_OUTPUT (1U << GPIO_DIR_12_SHIFT)
|
||||
|
||||
#define GPIO_DIR_13_SHIFT 13
|
||||
#define GPIO_DIR_13_WIDTH 1
|
||||
#define GPIO_DIR_13_MASK (((1U << GPIO_DIR_13_WIDTH) - 1U) << GPIO_DIR_13_SHIFT)
|
||||
#define GPIO_DIR_13_INPUT (0U << GPIO_DIR_13_SHIFT)
|
||||
#define GPIO_DIR_13_OUTPUT (1U << GPIO_DIR_13_SHIFT)
|
||||
|
||||
#define GPIO_DIR_14_SHIFT 14
|
||||
#define GPIO_DIR_14_WIDTH 1
|
||||
#define GPIO_DIR_14_MASK (((1U << GPIO_DIR_14_WIDTH) - 1U) << GPIO_DIR_14_SHIFT)
|
||||
#define GPIO_DIR_14_INPUT (0U << GPIO_DIR_14_SHIFT)
|
||||
#define GPIO_DIR_14_OUTPUT (1U << GPIO_DIR_14_SHIFT)
|
||||
|
||||
#define GPIO_DIR_15_SHIFT 15
|
||||
#define GPIO_DIR_15_WIDTH 1
|
||||
#define GPIO_DIR_15_MASK (((1U << GPIO_DIR_15_WIDTH) - 1U) << GPIO_DIR_15_SHIFT)
|
||||
#define GPIO_DIR_15_INPUT (0U << GPIO_DIR_15_SHIFT)
|
||||
#define GPIO_DIR_15_OUTPUT (1U << GPIO_DIR_15_SHIFT)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
40
bsp/dp32g030/irq.h
Normal file
40
bsp/dp32g030/irq.h
Normal file
@ -0,0 +1,40 @@
|
||||
#ifndef DP32G030_IRQ_H
|
||||
#define DP32G030_IRQ_H
|
||||
|
||||
enum {
|
||||
DP32_WWDT_IRQn = 0,
|
||||
DP32_IWDT_IRQn,
|
||||
DP32_RTC_IRQn,
|
||||
DP32_DMA_IRQn,
|
||||
DP32_SARADC_IRQn,
|
||||
DP32_TIMER_BASE0_IRQn,
|
||||
DP32_TIMER_BASE1_IRQn,
|
||||
DP32_TIMER_PLUS0_IRQn,
|
||||
DP32_TIMER_PLUS1_IRQn,
|
||||
DP32_PWM_BASE0_IRQn,
|
||||
DP32_PWM_BASE1_IRQn,
|
||||
DP32_PWM_PLUS0_IRQn,
|
||||
DP32_PWM_PLUS1_IRQn,
|
||||
DP32_UART0_IRQn,
|
||||
DP32_UART1_IRQn,
|
||||
DP32_UART2_IRQn,
|
||||
DP32_SPI0_IRQn,
|
||||
DP32_SPI1_IRQn,
|
||||
DP32_IIC0_IRQn,
|
||||
DP32_IIC1_IRQn,
|
||||
DP32_CMP_IRQn,
|
||||
DP32_TIMER_BASE2_IRQn,
|
||||
DP32_GPIOA5_IRQn,
|
||||
DP32_GPIOA6_IRQn,
|
||||
DP32_GPIOA7_IRQn,
|
||||
DP32_GPIOB0_IRQn,
|
||||
DP32_GPIOB1_IRQn,
|
||||
DP32_GPIOC0_IRQn,
|
||||
DP32_GPIOC1_IRQn,
|
||||
DP32_GPIOA_IRQn,
|
||||
DP32_GPIOB_IRQn,
|
||||
DP32_GPIOC_IRQn,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
55
bsp/dp32g030/pmu.h
Normal file
55
bsp/dp32g030/pmu.h
Normal file
@ -0,0 +1,55 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_PMU_H
|
||||
#define HARDWARE_DP32G030_PMU_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- PMU -------- */
|
||||
#define PMU_BASE_ADDR 0x40000800U
|
||||
#define PMU_BASE_SIZE 0x00000800U
|
||||
|
||||
#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U)
|
||||
#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR)
|
||||
#define PMU_SRC_CFG_RTC_CLK_SEL_SHIFT 4
|
||||
#define PMU_SRC_CFG_RTC_CLK_SEL_WIDTH 1
|
||||
#define PMU_SRC_CFG_RTC_CLK_SEL_MASK (((1U << PMU_SRC_CFG_RTC_CLK_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT)
|
||||
#define PMU_SRC_CFG_RTC_CLK_SEL_RCLF (0U << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT)
|
||||
#define PMU_SRC_CFG_RTC_CLK_SEL_XTAL (1U << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT)
|
||||
|
||||
#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U)
|
||||
#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR)
|
||||
#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U)
|
||||
#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR)
|
||||
#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U)
|
||||
#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR)
|
||||
#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU)
|
||||
#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR)
|
||||
#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U)
|
||||
#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR)
|
||||
#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U)
|
||||
#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR)
|
||||
#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U)
|
||||
#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR)
|
||||
#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU)
|
||||
#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
1583
bsp/dp32g030/portcon.h
Normal file
1583
bsp/dp32g030/portcon.h
Normal file
File diff suppressed because it is too large
Load Diff
48
bsp/dp32g030/saradc.h
Normal file
48
bsp/dp32g030/saradc.h
Normal file
@ -0,0 +1,48 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_SARADC_H
|
||||
#define HARDWARE_DP32G030_SARADC_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- SARADC -------- */
|
||||
#define SARADC_BASE_ADDR 0x400BA000U
|
||||
#define SARADC_BASE_SIZE 0x00000800U
|
||||
|
||||
#define SARADC_ADC_CALIB_OFFSET_ADDR (SARADC_BASE_ADDR + 0x00F0U)
|
||||
#define SARADC_ADC_CALIB_OFFSET (*(volatile uint32_t *)SARADC_ADC_CALIB_OFFSET_ADDR)
|
||||
#define SARADC_ADC_CALIB_OFFSET_OFFSET_SHIFT 0
|
||||
#define SARADC_ADC_CALIB_OFFSET_OFFSET_WIDTH 8
|
||||
#define SARADC_ADC_CALIB_OFFSET_OFFSET_MASK (((1U << SARADC_ADC_CALIB_OFFSET_OFFSET_WIDTH) - 1U) << SARADC_ADC_CALIB_OFFSET_OFFSET_SHIFT)
|
||||
#define SARADC_ADC_CALIB_OFFSET_OFFSET_VALID_SHIFT 16
|
||||
#define SARADC_ADC_CALIB_OFFSET_OFFSET_VALID_WIDTH 1
|
||||
#define SARADC_ADC_CALIB_OFFSET_OFFSET_VALID_MASK (((1U << SARADC_ADC_CALIB_OFFSET_OFFSET_VALID_WIDTH) - 1U) << SARADC_ADC_CALIB_OFFSET_OFFSET_VALID_SHIFT)
|
||||
|
||||
#define SARADC_ADC_CALIB_KD_ADDR (SARADC_BASE_ADDR + 0x00F4U)
|
||||
#define SARADC_ADC_CALIB_KD (*(volatile uint32_t *)SARADC_ADC_CALIB_KD_ADDR)
|
||||
#define SARADC_ADC_CALIB_KD_KD_SHIFT 0
|
||||
#define SARADC_ADC_CALIB_KD_KD_WIDTH 8
|
||||
#define SARADC_ADC_CALIB_KD_KD_MASK (((1U << SARADC_ADC_CALIB_KD_KD_WIDTH) - 1U) << SARADC_ADC_CALIB_KD_KD_SHIFT)
|
||||
#define SARADC_ADC_CALIB_KD_KD_VALID_SHIFT 16
|
||||
#define SARADC_ADC_CALIB_KD_KD_VALID_WIDTH 1
|
||||
#define SARADC_ADC_CALIB_KD_KD_VALID_MASK (((1U << SARADC_ADC_CALIB_KD_KD_VALID_WIDTH) - 1U) << SARADC_ADC_CALIB_KD_KD_VALID_SHIFT)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
190
bsp/dp32g030/spi.h
Normal file
190
bsp/dp32g030/spi.h
Normal file
@ -0,0 +1,190 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_SPI_H
|
||||
#define HARDWARE_DP32G030_SPI_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- SPI0 -------- */
|
||||
#define SPI0_BASE_ADDR 0x400B8000U
|
||||
#define SPI0_BASE_SIZE 0x00000800U
|
||||
#define SPI0 ((volatile SPI_Port_t *)SPI0_BASE_ADDR)
|
||||
|
||||
/* -------- SPI1 -------- */
|
||||
#define SPI1_BASE_ADDR 0x400B8800U
|
||||
#define SPI1_BASE_SIZE 0x00000800U
|
||||
#define SPI1 ((volatile SPI_Port_t *)SPI1_BASE_ADDR)
|
||||
|
||||
/* -------- SPI -------- */
|
||||
|
||||
typedef struct {
|
||||
uint32_t CR;
|
||||
uint32_t WDR;
|
||||
uint32_t RDR;
|
||||
uint32_t Reserved_000C[1];
|
||||
uint32_t IE;
|
||||
uint32_t IF;
|
||||
uint32_t FIFOST;
|
||||
} SPI_Port_t;
|
||||
|
||||
#define SPI_CR_SPR_SHIFT 0
|
||||
#define SPI_CR_SPR_WIDTH 3
|
||||
#define SPI_CR_SPR_MASK (((1U << SPI_CR_SPR_WIDTH) - 1U) << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_4 (0U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_8 (1U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_16 (2U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_32 (3U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_64 (4U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_128 (5U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_256 (6U << SPI_CR_SPR_SHIFT)
|
||||
#define SPI_CR_SPR_FPCLK_DIV_512 (7U << SPI_CR_SPR_SHIFT)
|
||||
|
||||
#define SPI_CR_SPE_SHIFT 3
|
||||
#define SPI_CR_SPE_WIDTH 1
|
||||
#define SPI_CR_SPE_MASK (((1U << SPI_CR_SPE_WIDTH) - 1U) << SPI_CR_SPE_SHIFT)
|
||||
#define SPI_CR_SPE_DISABLE (0U << SPI_CR_SPE_SHIFT)
|
||||
#define SPI_CR_SPE_ENABLE (1U << SPI_CR_SPE_SHIFT)
|
||||
|
||||
#define SPI_CR_CPHA_SHIFT 4
|
||||
#define SPI_CR_CPHA_WIDTH 1
|
||||
#define SPI_CR_CPHA_MASK (((1U << SPI_CR_CPHA_WIDTH) - 1U) << SPI_CR_CPHA_SHIFT)
|
||||
#define SPI_CR_CPOL_SHIFT 5
|
||||
#define SPI_CR_CPOL_WIDTH 1
|
||||
#define SPI_CR_CPOL_MASK (((1U << SPI_CR_CPOL_WIDTH) - 1U) << SPI_CR_CPOL_SHIFT)
|
||||
#define SPI_CR_MSTR_SHIFT 6
|
||||
#define SPI_CR_MSTR_WIDTH 1
|
||||
#define SPI_CR_MSTR_MASK (((1U << SPI_CR_MSTR_WIDTH) - 1U) << SPI_CR_MSTR_SHIFT)
|
||||
#define SPI_CR_LSB_SHIFT 7
|
||||
#define SPI_CR_LSB_WIDTH 1
|
||||
#define SPI_CR_LSB_MASK (((1U << SPI_CR_LSB_WIDTH) - 1U) << SPI_CR_LSB_SHIFT)
|
||||
#define SPI_CR_CPHA_DATA_HOLD_S_SHIFT 8
|
||||
#define SPI_CR_CPHA_DATA_HOLD_S_WIDTH 4
|
||||
#define SPI_CR_CPHA_DATA_HOLD_S_MASK (((1U << SPI_CR_CPHA_DATA_HOLD_S_WIDTH) - 1U) << SPI_CR_CPHA_DATA_HOLD_S_SHIFT)
|
||||
#define SPI_CR_MSR_SSN_SHIFT 12
|
||||
#define SPI_CR_MSR_SSN_WIDTH 1
|
||||
#define SPI_CR_MSR_SSN_MASK (((1U << SPI_CR_MSR_SSN_WIDTH) - 1U) << SPI_CR_MSR_SSN_SHIFT)
|
||||
#define SPI_CR_MSR_SSN_DISABLE (0U << SPI_CR_MSR_SSN_SHIFT)
|
||||
#define SPI_CR_MSR_SSN_ENABLE (1U << SPI_CR_MSR_SSN_SHIFT)
|
||||
|
||||
#define SPI_CR_RXDMAEN_SHIFT 13
|
||||
#define SPI_CR_RXDMAEN_WIDTH 1
|
||||
#define SPI_CR_RXDMAEN_MASK (((1U << SPI_CR_RXDMAEN_WIDTH) - 1U) << SPI_CR_RXDMAEN_SHIFT)
|
||||
#define SPI_CR_TXDMAEN_SHIFT 14
|
||||
#define SPI_CR_TXDMAEN_WIDTH 1
|
||||
#define SPI_CR_TXDMAEN_MASK (((1U << SPI_CR_TXDMAEN_WIDTH) - 1U) << SPI_CR_TXDMAEN_SHIFT)
|
||||
#define SPI_CR_RF_CLR_SHIFT 15
|
||||
#define SPI_CR_RF_CLR_WIDTH 1
|
||||
#define SPI_CR_RF_CLR_MASK (((1U << SPI_CR_RF_CLR_WIDTH) - 1U) << SPI_CR_RF_CLR_SHIFT)
|
||||
#define SPI_CR_TF_CLR_SHIFT 16
|
||||
#define SPI_CR_TF_CLR_WIDTH 1
|
||||
#define SPI_CR_TF_CLR_MASK (((1U << SPI_CR_TF_CLR_WIDTH) - 1U) << SPI_CR_TF_CLR_SHIFT)
|
||||
|
||||
#define SPI_IE_RXFIFO_OVF_SHIFT 0
|
||||
#define SPI_IE_RXFIFO_OVF_WIDTH 1
|
||||
#define SPI_IE_RXFIFO_OVF_MASK (((1U << SPI_IE_RXFIFO_OVF_WIDTH) - 1U) << SPI_IE_RXFIFO_OVF_SHIFT)
|
||||
#define SPI_IE_RXFIFO_OVF_DISABLE (0U << SPI_IE_RXFIFO_OVF_SHIFT)
|
||||
#define SPI_IE_RXFIFO_OVF_ENABLE (1U << SPI_IE_RXFIFO_OVF_SHIFT)
|
||||
|
||||
#define SPI_IE_RXFIFO_FULL_SHIFT 1
|
||||
#define SPI_IE_RXFIFO_FULL_WIDTH 1
|
||||
#define SPI_IE_RXFIFO_FULL_MASK (((1U << SPI_IE_RXFIFO_FULL_WIDTH) - 1U) << SPI_IE_RXFIFO_FULL_SHIFT)
|
||||
#define SPI_IE_RXFIFO_FULL_DISABLE (0U << SPI_IE_RXFIFO_FULL_SHIFT)
|
||||
#define SPI_IE_RXFIFO_FULL_ENABLE (1U << SPI_IE_RXFIFO_FULL_SHIFT)
|
||||
|
||||
#define SPI_IE_RXFIFO_HFULL_SHIFT 2
|
||||
#define SPI_IE_RXFIFO_HFULL_WIDTH 1
|
||||
#define SPI_IE_RXFIFO_HFULL_MASK (((1U << SPI_IE_RXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_RXFIFO_HFULL_SHIFT)
|
||||
#define SPI_IE_RXFIFO_HFULL_DISABLE (0U << SPI_IE_RXFIFO_HFULL_SHIFT)
|
||||
#define SPI_IE_RXFIFO_HFULL_ENABLE (1U << SPI_IE_RXFIFO_HFULL_SHIFT)
|
||||
|
||||
#define SPI_IE_TXFIFO_EMPTY_SHIFT 3
|
||||
#define SPI_IE_TXFIFO_EMPTY_WIDTH 1
|
||||
#define SPI_IE_TXFIFO_EMPTY_MASK (((1U << SPI_IE_TXFIFO_EMPTY_WIDTH) - 1U) << SPI_IE_TXFIFO_EMPTY_SHIFT)
|
||||
#define SPI_IE_TXFIFO_EMPTY_DISABLE (0U << SPI_IE_TXFIFO_EMPTY_SHIFT)
|
||||
#define SPI_IE_TXFIFO_EMPTY_ENABLE (1U << SPI_IE_TXFIFO_EMPTY_SHIFT)
|
||||
|
||||
#define SPI_IE_TXFIFO_HFULL_SHIFT 4
|
||||
#define SPI_IE_TXFIFO_HFULL_WIDTH 1
|
||||
#define SPI_IE_TXFIFO_HFULL_MASK (((1U << SPI_IE_TXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_TXFIFO_HFULL_SHIFT)
|
||||
#define SPI_IE_TXFIFO_HFULL_DISABLE (0U << SPI_IE_TXFIFO_HFULL_SHIFT)
|
||||
#define SPI_IE_TXFIFO_HFULL_ENABLE (1U << SPI_IE_TXFIFO_HFULL_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_RFE_SHIFT 0
|
||||
#define SPI_FIFOST_RFE_WIDTH 1
|
||||
#define SPI_FIFOST_RFE_MASK (((1U << SPI_FIFOST_RFE_WIDTH) - 1U) << SPI_FIFOST_RFE_SHIFT)
|
||||
#define SPI_FIFOST_RFE_NOT_EMPTY (0U << SPI_FIFOST_RFE_SHIFT)
|
||||
#define SPI_FIFOST_RFE_EMPTY (1U << SPI_FIFOST_RFE_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_RFF_SHIFT 1
|
||||
#define SPI_FIFOST_RFF_WIDTH 1
|
||||
#define SPI_FIFOST_RFF_MASK (((1U << SPI_FIFOST_RFF_WIDTH) - 1U) << SPI_FIFOST_RFF_SHIFT)
|
||||
#define SPI_FIFOST_RFF_NOT_FULL (0U << SPI_FIFOST_RFF_SHIFT)
|
||||
#define SPI_FIFOST_RFF_FULL (1U << SPI_FIFOST_RFF_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_RFHF_SHIFT 2
|
||||
#define SPI_FIFOST_RFHF_WIDTH 1
|
||||
#define SPI_FIFOST_RFHF_MASK (((1U << SPI_FIFOST_RFHF_WIDTH) - 1U) << SPI_FIFOST_RFHF_SHIFT)
|
||||
#define SPI_FIFOST_RFHF_NOT_HALF_FULL (0U << SPI_FIFOST_RFHF_SHIFT)
|
||||
#define SPI_FIFOST_RFHF_HALF_FULL (1U << SPI_FIFOST_RFHF_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_TFE_SHIFT 3
|
||||
#define SPI_FIFOST_TFE_WIDTH 1
|
||||
#define SPI_FIFOST_TFE_MASK (((1U << SPI_FIFOST_TFE_WIDTH) - 1U) << SPI_FIFOST_TFE_SHIFT)
|
||||
#define SPI_FIFOST_TFE_NOT_EMPTY (0U << SPI_FIFOST_TFE_SHIFT)
|
||||
#define SPI_FIFOST_TFE_EMPTY (1U << SPI_FIFOST_TFE_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_TFF_SHIFT 4
|
||||
#define SPI_FIFOST_TFF_WIDTH 1
|
||||
#define SPI_FIFOST_TFF_MASK (((1U << SPI_FIFOST_TFF_WIDTH) - 1U) << SPI_FIFOST_TFF_SHIFT)
|
||||
#define SPI_FIFOST_TFF_NOT_FULL (0U << SPI_FIFOST_TFF_SHIFT)
|
||||
#define SPI_FIFOST_TFF_FULL (1U << SPI_FIFOST_TFF_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_TFHF_SHIFT 5
|
||||
#define SPI_FIFOST_TFHF_WIDTH 1
|
||||
#define SPI_FIFOST_TFHF_MASK (((1U << SPI_FIFOST_TFHF_WIDTH) - 1U) << SPI_FIFOST_TFHF_SHIFT)
|
||||
#define SPI_FIFOST_TFHF_NOT_HALF_FULL (0U << SPI_FIFOST_TFHF_SHIFT)
|
||||
#define SPI_FIFOST_TFHF_HALF_FULL (1U << SPI_FIFOST_TFHF_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_RF_LEVEL_SHIFT 6
|
||||
#define SPI_FIFOST_RF_LEVEL_WIDTH 3
|
||||
#define SPI_FIFOST_RF_LEVEL_MASK (((1U << SPI_FIFOST_RF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_0_BYTE (0U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_1_BYTE (1U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_2_BYTE (2U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_3_BYTE (3U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_4_BYTE (4U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_5_BYTE (5U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_6_BYTE (6U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_RF_LEVEL_7_BYTE (7U << SPI_FIFOST_RF_LEVEL_SHIFT)
|
||||
|
||||
#define SPI_FIFOST_TF_LEVEL_SHIFT 9
|
||||
#define SPI_FIFOST_TF_LEVEL_WIDTH 3
|
||||
#define SPI_FIFOST_TF_LEVEL_MASK (((1U << SPI_FIFOST_TF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_0_BYTE (0U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_1_BYTE (1U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_2_BYTE (2U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_3_BYTE (3U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_4_BYTE (4U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_5_BYTE (5U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_6_BYTE (6U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
#define SPI_FIFOST_TF_LEVEL_7_BYTE (7U << SPI_FIFOST_TF_LEVEL_SHIFT)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
243
bsp/dp32g030/syscon.h
Normal file
243
bsp/dp32g030/syscon.h
Normal file
@ -0,0 +1,243 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_SYSCON_H
|
||||
#define HARDWARE_DP32G030_SYSCON_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- SYSCON -------- */
|
||||
#define SYSCON_BASE_ADDR 0x40000000U
|
||||
#define SYSCON_BASE_SIZE 0x00000800U
|
||||
|
||||
#define SYSCON_CLK_SEL_ADDR (SYSCON_BASE_ADDR + 0x0000U)
|
||||
#define SYSCON_CLK_SEL (*(volatile uint32_t *)SYSCON_CLK_SEL_ADDR)
|
||||
#define SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT 0
|
||||
#define SYSCON_CLK_SEL_SYS_CLK_SEL_WIDTH 1
|
||||
#define SYSCON_CLK_SEL_SYS_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_SYS_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SYS_CLK_SEL_RCHF (0U << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SYS_CLK_SEL_DIV_CLK (1U << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT)
|
||||
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT 1
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_WIDTH 3
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_DIV_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_1 (0U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_2 (1U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_4 (2U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_8 (3U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_16 (4U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_DIV_CLK_SEL_32 (5U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT)
|
||||
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT 4
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_WIDTH 3
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_SRC_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_RCHF (0U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_RCLF (1U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_XTAH (2U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_XTAL (3U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT)
|
||||
#define SYSCON_CLK_SEL_SRC_CLK_SEL_PLL (4U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT)
|
||||
|
||||
#define SYSCON_DIV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0004U)
|
||||
#define SYSCON_DIV_CLK_GATE (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR)
|
||||
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 1
|
||||
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH 1
|
||||
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)
|
||||
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_DISABLE (0U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)
|
||||
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_ENABLE (1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0008U)
|
||||
#define SYSCON_DEV_CLK_GATE (*(volatile uint32_t *)SYSCON_DEV_CLK_GATE_ADDR)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOA_SHIFT 0
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOA_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOA_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOA_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOA_DISABLE (0U << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOA_ENABLE (1U << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOB_SHIFT 1
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOB_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOB_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOB_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOB_DISABLE (0U << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOB_ENABLE (1U << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOC_SHIFT 2
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOC_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOC_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOC_DISABLE (0U << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_GPIOC_ENABLE (1U << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_IIC0_SHIFT 4
|
||||
#define SYSCON_DEV_CLK_GATE_IIC0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_IIC0_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_IIC0_DISABLE (0U << SYSCON_DEV_CLK_GATE_IIC0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_IIC0_ENABLE (1U << SYSCON_DEV_CLK_GATE_IIC0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_IIC1_SHIFT 5
|
||||
#define SYSCON_DEV_CLK_GATE_IIC1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_IIC1_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_IIC1_DISABLE (0U << SYSCON_DEV_CLK_GATE_IIC1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_IIC1_ENABLE (1U << SYSCON_DEV_CLK_GATE_IIC1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_UART0_SHIFT 6
|
||||
#define SYSCON_DEV_CLK_GATE_UART0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_UART0_MASK (((1U << SYSCON_DEV_CLK_GATE_UART0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_UART0_DISABLE (0U << SYSCON_DEV_CLK_GATE_UART0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_UART0_ENABLE (1U << SYSCON_DEV_CLK_GATE_UART0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_UART1_SHIFT 7
|
||||
#define SYSCON_DEV_CLK_GATE_UART1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_UART1_MASK (((1U << SYSCON_DEV_CLK_GATE_UART1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_UART1_DISABLE (0U << SYSCON_DEV_CLK_GATE_UART1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_UART1_ENABLE (1U << SYSCON_DEV_CLK_GATE_UART1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_UART2_SHIFT 8
|
||||
#define SYSCON_DEV_CLK_GATE_UART2_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_UART2_MASK (((1U << SYSCON_DEV_CLK_GATE_UART2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART2_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_UART2_DISABLE (0U << SYSCON_DEV_CLK_GATE_UART2_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_UART2_ENABLE (1U << SYSCON_DEV_CLK_GATE_UART2_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_SPI0_SHIFT 10
|
||||
#define SYSCON_DEV_CLK_GATE_SPI0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_SPI0_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_SPI0_DISABLE (0U << SYSCON_DEV_CLK_GATE_SPI0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_SPI0_ENABLE (1U << SYSCON_DEV_CLK_GATE_SPI0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_SPI1_SHIFT 11
|
||||
#define SYSCON_DEV_CLK_GATE_SPI1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_SPI1_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_SPI1_DISABLE (0U << SYSCON_DEV_CLK_GATE_SPI1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_SPI1_ENABLE (1U << SYSCON_DEV_CLK_GATE_SPI1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT 12
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT 13
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT 14
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT 15
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT 16
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT 17
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE0_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE0_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT 18
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE1_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_BASE1_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT 20
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT 21
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_RTC_SHIFT 22
|
||||
#define SYSCON_DEV_CLK_GATE_RTC_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_RTC_MASK (((1U << SYSCON_DEV_CLK_GATE_RTC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_RTC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_RTC_DISABLE (0U << SYSCON_DEV_CLK_GATE_RTC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_RTC_ENABLE (1U << SYSCON_DEV_CLK_GATE_RTC_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_IWDT_SHIFT 23
|
||||
#define SYSCON_DEV_CLK_GATE_IWDT_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_IWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_IWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IWDT_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_IWDT_DISABLE (0U << SYSCON_DEV_CLK_GATE_IWDT_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_IWDT_ENABLE (1U << SYSCON_DEV_CLK_GATE_IWDT_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_WWDT_SHIFT 24
|
||||
#define SYSCON_DEV_CLK_GATE_WWDT_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_WWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_WWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_WWDT_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_WWDT_DISABLE (0U << SYSCON_DEV_CLK_GATE_WWDT_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_WWDT_ENABLE (1U << SYSCON_DEV_CLK_GATE_WWDT_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_SARADC_SHIFT 25
|
||||
#define SYSCON_DEV_CLK_GATE_SARADC_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_SARADC_MASK (((1U << SYSCON_DEV_CLK_GATE_SARADC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SARADC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_SARADC_DISABLE (0U << SYSCON_DEV_CLK_GATE_SARADC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_SARADC_ENABLE (1U << SYSCON_DEV_CLK_GATE_SARADC_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_CRC_SHIFT 27
|
||||
#define SYSCON_DEV_CLK_GATE_CRC_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_CRC_MASK (((1U << SYSCON_DEV_CLK_GATE_CRC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_CRC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_CRC_DISABLE (0U << SYSCON_DEV_CLK_GATE_CRC_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_CRC_ENABLE (1U << SYSCON_DEV_CLK_GATE_CRC_SHIFT)
|
||||
|
||||
#define SYSCON_DEV_CLK_GATE_AES_SHIFT 28
|
||||
#define SYSCON_DEV_CLK_GATE_AES_WIDTH 1
|
||||
#define SYSCON_DEV_CLK_GATE_AES_MASK (((1U << SYSCON_DEV_CLK_GATE_AES_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_AES_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_AES_DISABLE (0U << SYSCON_DEV_CLK_GATE_AES_SHIFT)
|
||||
#define SYSCON_DEV_CLK_GATE_AES_ENABLE (1U << SYSCON_DEV_CLK_GATE_AES_SHIFT)
|
||||
|
||||
#define SYSCON_RC_FREQ_DELTA_ADDR (SYSCON_BASE_ADDR + 0x0078U)
|
||||
#define SYSCON_RC_FREQ_DELTA (*(volatile uint32_t *)SYSCON_RC_FREQ_DELTA_ADDR)
|
||||
#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT 0
|
||||
#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH 10
|
||||
#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT)
|
||||
#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT 10
|
||||
#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH 1
|
||||
#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT)
|
||||
#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT 11
|
||||
#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH 20
|
||||
#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT)
|
||||
#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT 31
|
||||
#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH 1
|
||||
#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT)
|
||||
|
||||
#define SYSCON_VREF_VOLT_DELTA_ADDR (SYSCON_BASE_ADDR + 0x007CU)
|
||||
#define SYSCON_VREF_VOLT_DELTA (*(volatile uint32_t *)SYSCON_VREF_VOLT_DELTA_ADDR)
|
||||
#define SYSCON_CHIP_ID0_ADDR (SYSCON_BASE_ADDR + 0x0080U)
|
||||
#define SYSCON_CHIP_ID0 (*(volatile uint32_t *)SYSCON_CHIP_ID0_ADDR)
|
||||
#define SYSCON_CHIP_ID1_ADDR (SYSCON_BASE_ADDR + 0x0084U)
|
||||
#define SYSCON_CHIP_ID1 (*(volatile uint32_t *)SYSCON_CHIP_ID1_ADDR)
|
||||
#define SYSCON_CHIP_ID2_ADDR (SYSCON_BASE_ADDR + 0x0088U)
|
||||
#define SYSCON_CHIP_ID2 (*(volatile uint32_t *)SYSCON_CHIP_ID2_ADDR)
|
||||
#define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU)
|
||||
#define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
331
bsp/dp32g030/uart.h
Normal file
331
bsp/dp32g030/uart.h
Normal file
@ -0,0 +1,331 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef HARDWARE_DP32G030_UART_H
|
||||
#define HARDWARE_DP32G030_UART_H
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* -------- UART0 -------- */
|
||||
#define UART0_BASE_ADDR 0x4006B000U
|
||||
#define UART0_BASE_SIZE 0x00000800U
|
||||
#define UART0 ((volatile UART_Port_t *)UART0_BASE_ADDR)
|
||||
|
||||
/* -------- UART1 -------- */
|
||||
#define UART1_BASE_ADDR 0x4006B800U
|
||||
#define UART1_BASE_SIZE 0x00000800U
|
||||
#define UART1 ((volatile UART_Port_t *)UART1_BASE_ADDR)
|
||||
|
||||
/* -------- UART2 -------- */
|
||||
#define UART2_BASE_ADDR 0x4006C000U
|
||||
#define UART2_BASE_SIZE 0x00000800U
|
||||
#define UART2 ((volatile UART_Port_t *)UART2_BASE_ADDR)
|
||||
|
||||
/* -------- UART -------- */
|
||||
|
||||
typedef struct {
|
||||
uint32_t CTRL;
|
||||
uint32_t BAUD;
|
||||
uint32_t TDR;
|
||||
uint32_t RDR;
|
||||
uint32_t IE;
|
||||
uint32_t IF;
|
||||
uint32_t FIFO;
|
||||
uint32_t FC;
|
||||
uint32_t RXTO;
|
||||
} UART_Port_t;
|
||||
|
||||
#define UART_CTRL_UARTEN_SHIFT 0
|
||||
#define UART_CTRL_UARTEN_WIDTH 1
|
||||
#define UART_CTRL_UARTEN_MASK (((1U << UART_CTRL_UARTEN_WIDTH) - 1U) << UART_CTRL_UARTEN_SHIFT)
|
||||
#define UART_CTRL_UARTEN_DISABLE (0U << UART_CTRL_UARTEN_SHIFT)
|
||||
#define UART_CTRL_UARTEN_ENABLE (1U << UART_CTRL_UARTEN_SHIFT)
|
||||
|
||||
#define UART_CTRL_RXEN_SHIFT 1
|
||||
#define UART_CTRL_RXEN_WIDTH 1
|
||||
#define UART_CTRL_RXEN_MASK (((1U << UART_CTRL_RXEN_WIDTH) - 1U) << UART_CTRL_RXEN_SHIFT)
|
||||
#define UART_CTRL_RXEN_DISABLE (0U << UART_CTRL_RXEN_SHIFT)
|
||||
#define UART_CTRL_RXEN_ENABLE (1U << UART_CTRL_RXEN_SHIFT)
|
||||
|
||||
#define UART_CTRL_TXEN_SHIFT 2
|
||||
#define UART_CTRL_TXEN_WIDTH 1
|
||||
#define UART_CTRL_TXEN_MASK (((1U << UART_CTRL_TXEN_WIDTH) - 1U) << UART_CTRL_TXEN_SHIFT)
|
||||
#define UART_CTRL_TXEN_DISABLE (0U << UART_CTRL_TXEN_SHIFT)
|
||||
#define UART_CTRL_TXEN_ENABLE (1U << UART_CTRL_TXEN_SHIFT)
|
||||
|
||||
#define UART_CTRL_RXDMAEN_SHIFT 3
|
||||
#define UART_CTRL_RXDMAEN_WIDTH 1
|
||||
#define UART_CTRL_RXDMAEN_MASK (((1U << UART_CTRL_RXDMAEN_WIDTH) - 1U) << UART_CTRL_RXDMAEN_SHIFT)
|
||||
#define UART_CTRL_RXDMAEN_DISABLE (0U << UART_CTRL_RXDMAEN_SHIFT)
|
||||
#define UART_CTRL_RXDMAEN_ENABLE (1U << UART_CTRL_RXDMAEN_SHIFT)
|
||||
|
||||
#define UART_CTRL_TXDMAEN_SHIFT 4
|
||||
#define UART_CTRL_TXDMAEN_WIDTH 1
|
||||
#define UART_CTRL_TXDMAEN_MASK (((1U << UART_CTRL_TXDMAEN_WIDTH) - 1U) << UART_CTRL_TXDMAEN_SHIFT)
|
||||
#define UART_CTRL_TXDMAEN_DISABLE (0U << UART_CTRL_TXDMAEN_SHIFT)
|
||||
#define UART_CTRL_TXDMAEN_ENABLE (1U << UART_CTRL_TXDMAEN_SHIFT)
|
||||
|
||||
#define UART_CTRL_NINEBIT_SHIFT 5
|
||||
#define UART_CTRL_NINEBIT_WIDTH 1
|
||||
#define UART_CTRL_NINEBIT_MASK (((1U << UART_CTRL_NINEBIT_WIDTH) - 1U) << UART_CTRL_NINEBIT_SHIFT)
|
||||
#define UART_CTRL_NINEBIT_DISABLE (0U << UART_CTRL_NINEBIT_SHIFT)
|
||||
#define UART_CTRL_NINEBIT_ENABLE (1U << UART_CTRL_NINEBIT_SHIFT)
|
||||
|
||||
#define UART_CTRL_PAREN_SHIFT 6
|
||||
#define UART_CTRL_PAREN_WIDTH 1
|
||||
#define UART_CTRL_PAREN_MASK (((1U << UART_CTRL_PAREN_WIDTH) - 1U) << UART_CTRL_PAREN_SHIFT)
|
||||
#define UART_CTRL_PAREN_DISABLE (0U << UART_CTRL_PAREN_SHIFT)
|
||||
#define UART_CTRL_PAREN_ENABLE (1U << UART_CTRL_PAREN_SHIFT)
|
||||
|
||||
#define UART_IE_TXDONE_SHIFT 2
|
||||
#define UART_IE_TXDONE_WIDTH 1
|
||||
#define UART_IE_TXDONE_MASK (((1U << UART_IE_TXDONE_WIDTH) - 1U) << UART_IE_TXDONE_SHIFT)
|
||||
#define UART_IE_TXDONE_DISABLE (0U << UART_IE_TXDONE_SHIFT)
|
||||
#define UART_IE_TXDONE_ENABLE (1U << UART_IE_TXDONE_SHIFT)
|
||||
|
||||
#define UART_IE_PARITYE_SHIFT 3
|
||||
#define UART_IE_PARITYE_WIDTH 1
|
||||
#define UART_IE_PARITYE_MASK (((1U << UART_IE_PARITYE_WIDTH) - 1U) << UART_IE_PARITYE_SHIFT)
|
||||
#define UART_IE_PARITYE_DISABLE (0U << UART_IE_PARITYE_SHIFT)
|
||||
#define UART_IE_PARITYE_ENABLE (1U << UART_IE_PARITYE_SHIFT)
|
||||
|
||||
#define UART_IE_STOPE_SHIFT 4
|
||||
#define UART_IE_STOPE_WIDTH 1
|
||||
#define UART_IE_STOPE_MASK (((1U << UART_IE_STOPE_WIDTH) - 1U) << UART_IE_STOPE_SHIFT)
|
||||
#define UART_IE_STOPE_DISABLE (0U << UART_IE_STOPE_SHIFT)
|
||||
#define UART_IE_STOPE_ENABLE (1U << UART_IE_STOPE_SHIFT)
|
||||
|
||||
#define UART_IE_RXTO_SHIFT 5
|
||||
#define UART_IE_RXTO_WIDTH 1
|
||||
#define UART_IE_RXTO_MASK (((1U << UART_IE_RXTO_WIDTH) - 1U) << UART_IE_RXTO_SHIFT)
|
||||
#define UART_IE_RXTO_DISABLE (0U << UART_IE_RXTO_SHIFT)
|
||||
#define UART_IE_RXTO_ENABLE (1U << UART_IE_RXTO_SHIFT)
|
||||
|
||||
#define UART_IE_RXFIFO_SHIFT 6
|
||||
#define UART_IE_RXFIFO_WIDTH 1
|
||||
#define UART_IE_RXFIFO_MASK (((1U << UART_IE_RXFIFO_WIDTH) - 1U) << UART_IE_RXFIFO_SHIFT)
|
||||
#define UART_IE_RXFIFO_DISABLE (0U << UART_IE_RXFIFO_SHIFT)
|
||||
#define UART_IE_RXFIFO_ENABLE (1U << UART_IE_RXFIFO_SHIFT)
|
||||
|
||||
#define UART_IE_TXFIFO_SHIFT 7
|
||||
#define UART_IE_TXFIFO_WIDTH 1
|
||||
#define UART_IE_TXFIFO_MASK (((1U << UART_IE_TXFIFO_WIDTH) - 1U) << UART_IE_TXFIFO_SHIFT)
|
||||
#define UART_IE_TXFIFO_DISABLE (0U << UART_IE_TXFIFO_SHIFT)
|
||||
#define UART_IE_TXFIFO_ENABLE (1U << UART_IE_TXFIFO_SHIFT)
|
||||
|
||||
#define UART_IE_RXFIFO_OVF_SHIFT 8
|
||||
#define UART_IE_RXFIFO_OVF_WIDTH 1
|
||||
#define UART_IE_RXFIFO_OVF_MASK (((1U << UART_IE_RXFIFO_OVF_WIDTH) - 1U) << UART_IE_RXFIFO_OVF_SHIFT)
|
||||
#define UART_IE_RXFIFO_OVF_DISABLE (0U << UART_IE_RXFIFO_OVF_SHIFT)
|
||||
#define UART_IE_RXFIFO_OVF_ENABLE (1U << UART_IE_RXFIFO_OVF_SHIFT)
|
||||
|
||||
#define UART_IE_ABRD_OVF_SHIFT 9
|
||||
#define UART_IE_ABRD_OVF_WIDTH 1
|
||||
#define UART_IE_ABRD_OVF_MASK (((1U << UART_IE_ABRD_OVF_WIDTH) - 1U) << UART_IE_ABRD_OVF_SHIFT)
|
||||
#define UART_IE_ABRD_OVF_DISABLE (0U << UART_IE_ABRD_OVF_SHIFT)
|
||||
#define UART_IE_ABRD_OVF_ENABLE (1U << UART_IE_ABRD_OVF_SHIFT)
|
||||
|
||||
#define UART_IF_TXDONE_SHIFT 2
|
||||
#define UART_IF_TXDONE_WIDTH 1
|
||||
#define UART_IF_TXDONE_MASK (((1U << UART_IF_TXDONE_WIDTH) - 1U) << UART_IF_TXDONE_SHIFT)
|
||||
#define UART_IF_TXDONE_NOT_SET (0U << UART_IF_TXDONE_SHIFT)
|
||||
#define UART_IF_TXDONE_SET (1U << UART_IF_TXDONE_SHIFT)
|
||||
|
||||
#define UART_IF_PARITYE_SHIFT 3
|
||||
#define UART_IF_PARITYE_WIDTH 1
|
||||
#define UART_IF_PARITYE_MASK (((1U << UART_IF_PARITYE_WIDTH) - 1U) << UART_IF_PARITYE_SHIFT)
|
||||
#define UART_IF_PARITYE_NOT_SET (0U << UART_IF_PARITYE_SHIFT)
|
||||
#define UART_IF_PARITYE_SET (1U << UART_IF_PARITYE_SHIFT)
|
||||
|
||||
#define UART_IF_STOPE_SHIFT 4
|
||||
#define UART_IF_STOPE_WIDTH 1
|
||||
#define UART_IF_STOPE_MASK (((1U << UART_IF_STOPE_WIDTH) - 1U) << UART_IF_STOPE_SHIFT)
|
||||
#define UART_IF_STOPE_NOT_SET (0U << UART_IF_STOPE_SHIFT)
|
||||
#define UART_IF_STOPE_SET (1U << UART_IF_STOPE_SHIFT)
|
||||
|
||||
#define UART_IF_RXTO_SHIFT 5
|
||||
#define UART_IF_RXTO_WIDTH 1
|
||||
#define UART_IF_RXTO_MASK (((1U << UART_IF_RXTO_WIDTH) - 1U) << UART_IF_RXTO_SHIFT)
|
||||
#define UART_IF_RXTO_NOT_SET (0U << UART_IF_RXTO_SHIFT)
|
||||
#define UART_IF_RXTO_SET (1U << UART_IF_RXTO_SHIFT)
|
||||
|
||||
#define UART_IF_RXFIFO_SHIFT 6
|
||||
#define UART_IF_RXFIFO_WIDTH 1
|
||||
#define UART_IF_RXFIFO_MASK (((1U << UART_IF_RXFIFO_WIDTH) - 1U) << UART_IF_RXFIFO_SHIFT)
|
||||
#define UART_IF_RXFIFO_NOT_SET (0U << UART_IF_RXFIFO_SHIFT)
|
||||
#define UART_IF_RXFIFO_SET (1U << UART_IF_RXFIFO_SHIFT)
|
||||
|
||||
#define UART_IF_TXFIFO_SHIFT 7
|
||||
#define UART_IF_TXFIFO_WIDTH 1
|
||||
#define UART_IF_TXFIFO_MASK (((1U << UART_IF_TXFIFO_WIDTH) - 1U) << UART_IF_TXFIFO_SHIFT)
|
||||
#define UART_IF_TXFIFO_NOT_SET (0U << UART_IF_TXFIFO_SHIFT)
|
||||
#define UART_IF_TXFIFO_SET (1U << UART_IF_TXFIFO_SHIFT)
|
||||
|
||||
#define UART_IF_RXFIFO_OVF_SHIFT 8
|
||||
#define UART_IF_RXFIFO_OVF_WIDTH 1
|
||||
#define UART_IF_RXFIFO_OVF_MASK (((1U << UART_IF_RXFIFO_OVF_WIDTH) - 1U) << UART_IF_RXFIFO_OVF_SHIFT)
|
||||
#define UART_IF_RXFIFO_OVF_NOT_SET (0U << UART_IF_RXFIFO_OVF_SHIFT)
|
||||
#define UART_IF_RXFIFO_OVF_SET (1U << UART_IF_RXFIFO_OVF_SHIFT)
|
||||
|
||||
#define UART_IF_ABRD_OVF_SHIFT 9
|
||||
#define UART_IF_ABRD_OVF_WIDTH 1
|
||||
#define UART_IF_ABRD_OVF_MASK (((1U << UART_IF_ABRD_OVF_WIDTH) - 1U) << UART_IF_ABRD_OVF_SHIFT)
|
||||
#define UART_IF_ABRD_OVF_NOT_SET (0U << UART_IF_ABRD_OVF_SHIFT)
|
||||
#define UART_IF_ABRD_OVF_SET (1U << UART_IF_ABRD_OVF_SHIFT)
|
||||
|
||||
#define UART_IF_RXFIFO_EMPTY_SHIFT 10
|
||||
#define UART_IF_RXFIFO_EMPTY_WIDTH 1
|
||||
#define UART_IF_RXFIFO_EMPTY_MASK (((1U << UART_IF_RXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_RXFIFO_EMPTY_SHIFT)
|
||||
#define UART_IF_RXFIFO_EMPTY_NOT_SET (0U << UART_IF_RXFIFO_EMPTY_SHIFT)
|
||||
#define UART_IF_RXFIFO_EMPTY_SET (1U << UART_IF_RXFIFO_EMPTY_SHIFT)
|
||||
|
||||
#define UART_IF_RXFIFO_FULL_SHIFT 11
|
||||
#define UART_IF_RXFIFO_FULL_WIDTH 1
|
||||
#define UART_IF_RXFIFO_FULL_MASK (((1U << UART_IF_RXFIFO_FULL_WIDTH) - 1U) << UART_IF_RXFIFO_FULL_SHIFT)
|
||||
#define UART_IF_RXFIFO_FULL_NOT_SET (0U << UART_IF_RXFIFO_FULL_SHIFT)
|
||||
#define UART_IF_RXFIFO_FULL_SET (1U << UART_IF_RXFIFO_FULL_SHIFT)
|
||||
|
||||
#define UART_IF_RXFIFO_HFULL_SHIFT 12
|
||||
#define UART_IF_RXFIFO_HFULL_WIDTH 1
|
||||
#define UART_IF_RXFIFO_HFULL_MASK (((1U << UART_IF_RXFIFO_HFULL_WIDTH) - 1U) << UART_IF_RXFIFO_HFULL_SHIFT)
|
||||
#define UART_IF_RXFIFO_HFULL_NOT_SET (0U << UART_IF_RXFIFO_HFULL_SHIFT)
|
||||
#define UART_IF_RXFIFO_HFULL_SET (1U << UART_IF_RXFIFO_HFULL_SHIFT)
|
||||
|
||||
#define UART_IF_TXFIFO_EMPTY_SHIFT 13
|
||||
#define UART_IF_TXFIFO_EMPTY_WIDTH 1
|
||||
#define UART_IF_TXFIFO_EMPTY_MASK (((1U << UART_IF_TXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_TXFIFO_EMPTY_SHIFT)
|
||||
#define UART_IF_TXFIFO_EMPTY_NOT_SET (0U << UART_IF_TXFIFO_EMPTY_SHIFT)
|
||||
#define UART_IF_TXFIFO_EMPTY_SET (1U << UART_IF_TXFIFO_EMPTY_SHIFT)
|
||||
|
||||
#define UART_IF_TXFIFO_FULL_SHIFT 14
|
||||
#define UART_IF_TXFIFO_FULL_WIDTH 1
|
||||
#define UART_IF_TXFIFO_FULL_MASK (((1U << UART_IF_TXFIFO_FULL_WIDTH) - 1U) << UART_IF_TXFIFO_FULL_SHIFT)
|
||||
#define UART_IF_TXFIFO_FULL_NOT_SET (0U << UART_IF_TXFIFO_FULL_SHIFT)
|
||||
#define UART_IF_TXFIFO_FULL_SET (1U << UART_IF_TXFIFO_FULL_SHIFT)
|
||||
|
||||
#define UART_IF_TXFIFO_HFULL_SHIFT 15
|
||||
#define UART_IF_TXFIFO_HFULL_WIDTH 1
|
||||
#define UART_IF_TXFIFO_HFULL_MASK (((1U << UART_IF_TXFIFO_HFULL_WIDTH) - 1U) << UART_IF_TXFIFO_HFULL_SHIFT)
|
||||
#define UART_IF_TXFIFO_HFULL_NOT_SET (0U << UART_IF_TXFIFO_HFULL_SHIFT)
|
||||
#define UART_IF_TXFIFO_HFULL_SET (1U << UART_IF_TXFIFO_HFULL_SHIFT)
|
||||
|
||||
#define UART_IF_TXBUSY_SHIFT 16
|
||||
#define UART_IF_TXBUSY_WIDTH 1
|
||||
#define UART_IF_TXBUSY_MASK (((1U << UART_IF_TXBUSY_WIDTH) - 1U) << UART_IF_TXBUSY_SHIFT)
|
||||
#define UART_IF_TXBUSY_NOT_SET (0U << UART_IF_TXBUSY_SHIFT)
|
||||
#define UART_IF_TXBUSY_SET (1U << UART_IF_TXBUSY_SHIFT)
|
||||
|
||||
#define UART_IF_RF_LEVEL_SHIFT 17
|
||||
#define UART_IF_RF_LEVEL_WIDTH 3
|
||||
#define UART_IF_RF_LEVEL_MASK (((1U << UART_IF_RF_LEVEL_WIDTH) - 1U) << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_0_8_BYTE (0U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_1_BYTE (1U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_2_BYTE (2U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_3_BYTE (3U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_4_BYTE (4U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_5_BYTE (5U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_6_BYTE (6U << UART_IF_RF_LEVEL_SHIFT)
|
||||
#define UART_IF_RF_LEVEL_7_BYTE (7U << UART_IF_RF_LEVEL_SHIFT)
|
||||
|
||||
#define UART_IF_TF_LEVEL_SHIFT 20
|
||||
#define UART_IF_TF_LEVEL_WIDTH 3
|
||||
#define UART_IF_TF_LEVEL_MASK (((1U << UART_IF_TF_LEVEL_WIDTH) - 1U) << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_0_8_BYTE (0U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_1_BYTE (1U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_2_BYTE (2U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_3_BYTE (3U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_4_BYTE (4U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_5_BYTE (5U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_6_BYTE (6U << UART_IF_TF_LEVEL_SHIFT)
|
||||
#define UART_IF_TF_LEVEL_7_BYTE (7U << UART_IF_TF_LEVEL_SHIFT)
|
||||
|
||||
#define UART_FIFO_RF_LEVEL_SHIFT 0
|
||||
#define UART_FIFO_RF_LEVEL_WIDTH 3
|
||||
#define UART_FIFO_RF_LEVEL_MASK (((1U << UART_FIFO_RF_LEVEL_WIDTH) - 1U) << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_1_BYTE (0U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_2_BYTE (1U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_3_BYTE (2U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_4_BYTE (3U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_5_BYTE (4U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_6_BYTE (5U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_7_BYTE (6U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_RF_LEVEL_8_BYTE (7U << UART_FIFO_RF_LEVEL_SHIFT)
|
||||
|
||||
#define UART_FIFO_TF_LEVEL_SHIFT 3
|
||||
#define UART_FIFO_TF_LEVEL_WIDTH 3
|
||||
#define UART_FIFO_TF_LEVEL_MASK (((1U << UART_FIFO_TF_LEVEL_WIDTH) - 1U) << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_0_BYTE (0U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_1_BYTE (1U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_2_BYTE (2U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_3_BYTE (3U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_4_BYTE (4U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_5_BYTE (5U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_6_BYTE (6U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
#define UART_FIFO_TF_LEVEL_7_BYTE (7U << UART_FIFO_TF_LEVEL_SHIFT)
|
||||
|
||||
#define UART_FIFO_RF_CLR_SHIFT 6
|
||||
#define UART_FIFO_RF_CLR_WIDTH 1
|
||||
#define UART_FIFO_RF_CLR_MASK (((1U << UART_FIFO_RF_CLR_WIDTH) - 1U) << UART_FIFO_RF_CLR_SHIFT)
|
||||
#define UART_FIFO_RF_CLR_DISABLE (0U << UART_FIFO_RF_CLR_SHIFT)
|
||||
#define UART_FIFO_RF_CLR_ENABLE (1U << UART_FIFO_RF_CLR_SHIFT)
|
||||
|
||||
#define UART_FIFO_TF_CLR_SHIFT 7
|
||||
#define UART_FIFO_TF_CLR_WIDTH 1
|
||||
#define UART_FIFO_TF_CLR_MASK (((1U << UART_FIFO_TF_CLR_WIDTH) - 1U) << UART_FIFO_TF_CLR_SHIFT)
|
||||
#define UART_FIFO_TF_CLR_DISABLE (0U << UART_FIFO_TF_CLR_SHIFT)
|
||||
#define UART_FIFO_TF_CLR_ENABLE (1U << UART_FIFO_TF_CLR_SHIFT)
|
||||
|
||||
#define UART_FC_CTSEN_SHIFT 0
|
||||
#define UART_FC_CTSEN_WIDTH 1
|
||||
#define UART_FC_CTSEN_MASK (((1U << UART_FC_CTSEN_WIDTH) - 1U) << UART_FC_CTSEN_SHIFT)
|
||||
#define UART_FC_CTSEN_DISABLE (0U << UART_FC_CTSEN_SHIFT)
|
||||
#define UART_FC_CTSEN_ENABLE (1U << UART_FC_CTSEN_SHIFT)
|
||||
|
||||
#define UART_FC_RTSEN_SHIFT 1
|
||||
#define UART_FC_RTSEN_WIDTH 1
|
||||
#define UART_FC_RTSEN_MASK (((1U << UART_FC_RTSEN_WIDTH) - 1U) << UART_FC_RTSEN_SHIFT)
|
||||
#define UART_FC_RTSEN_DISABLE (0U << UART_FC_RTSEN_SHIFT)
|
||||
#define UART_FC_RTSEN_ENABLE (1U << UART_FC_RTSEN_SHIFT)
|
||||
|
||||
#define UART_FC_CTSPOL_SHIFT 2
|
||||
#define UART_FC_CTSPOL_WIDTH 1
|
||||
#define UART_FC_CTSPOL_MASK (((1U << UART_FC_CTSPOL_WIDTH) - 1U) << UART_FC_CTSPOL_SHIFT)
|
||||
#define UART_FC_CTSPOL_LOW (0U << UART_FC_CTSPOL_SHIFT)
|
||||
#define UART_FC_CTSPOL_HIGH (1U << UART_FC_CTSPOL_SHIFT)
|
||||
|
||||
#define UART_FC_RTSPOL_SHIFT 3
|
||||
#define UART_FC_RTSPOL_WIDTH 1
|
||||
#define UART_FC_RTSPOL_MASK (((1U << UART_FC_RTSPOL_WIDTH) - 1U) << UART_FC_RTSPOL_SHIFT)
|
||||
#define UART_FC_RTSPOL_LOW (0U << UART_FC_RTSPOL_SHIFT)
|
||||
#define UART_FC_RTSPOL_HIGH (1U << UART_FC_RTSPOL_SHIFT)
|
||||
|
||||
#define UART_FC_CTS_SIGNAL_SHIFT 4
|
||||
#define UART_FC_CTS_SIGNAL_WIDTH 1
|
||||
#define UART_FC_CTS_SIGNAL_MASK (((1U << UART_FC_CTS_SIGNAL_WIDTH) - 1U) << UART_FC_CTS_SIGNAL_SHIFT)
|
||||
#define UART_FC_CTS_SIGNAL_LOW (0U << UART_FC_CTS_SIGNAL_SHIFT)
|
||||
#define UART_FC_CTS_SIGNAL_HIGH (1U << UART_FC_CTS_SIGNAL_SHIFT)
|
||||
|
||||
#define UART_FC_RTS_SIGNAL_SHIFT 5
|
||||
#define UART_FC_RTS_SIGNAL_WIDTH 1
|
||||
#define UART_FC_RTS_SIGNAL_MASK (((1U << UART_FC_RTS_SIGNAL_WIDTH) - 1U) << UART_FC_RTS_SIGNAL_SHIFT)
|
||||
#define UART_FC_RTS_SIGNAL_LOW (0U << UART_FC_RTS_SIGNAL_SHIFT)
|
||||
#define UART_FC_RTS_SIGNAL_HIGH (1U << UART_FC_RTS_SIGNAL_SHIFT)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
50
driver/crc.c
Normal file
50
driver/crc.c
Normal file
@ -0,0 +1,50 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "bsp/dp32g030/crc.h"
|
||||
#include "driver/crc.h"
|
||||
|
||||
void CRC_Init(void)
|
||||
{
|
||||
CRC_CR = 0
|
||||
| CRC_CR_CRC_EN_DISABLE
|
||||
| CRC_CR_INPUT_REV_NORMAL
|
||||
| CRC_CR_INPUT_INV_NORMAL
|
||||
| CRC_CR_OUTPUT_REV_NORMAL
|
||||
| CRC_CR_OUTPUT_INV_NORMAL
|
||||
| CRC_CR_DATA_WIDTH_8
|
||||
| CRC_CR_CRC_SEL_CRC_16_CCITT
|
||||
;
|
||||
CRC_IV = 0;
|
||||
}
|
||||
|
||||
uint16_t CRC_Calculate(const void *pBuffer, uint16_t Size)
|
||||
{
|
||||
const uint8_t *pData = (const uint8_t *)pBuffer;
|
||||
uint16_t i, Crc;
|
||||
|
||||
CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_ENABLE;
|
||||
|
||||
for (i = 0; i < Size; i++) {
|
||||
CRC_DATAIN = pData[i];
|
||||
}
|
||||
Crc = CRC_DATAOUT;
|
||||
|
||||
CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_DISABLE;
|
||||
|
||||
return Crc;
|
||||
}
|
||||
|
||||
26
driver/crc.h
Normal file
26
driver/crc.h
Normal file
@ -0,0 +1,26 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_CRC_H
|
||||
#define DRIVER_CRC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void CRC_Init(void);
|
||||
uint16_t CRC_Calculate(const void *pBuffer, uint16_t Size);
|
||||
|
||||
#endif
|
||||
|
||||
55
driver/eeprom.c
Normal file
55
driver/eeprom.c
Normal file
@ -0,0 +1,55 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "driver/eeprom.h"
|
||||
#include "driver/i2c.h"
|
||||
#include "driver/system.h"
|
||||
|
||||
void EEPROM_ReadBuffer(uint16_t Address, void *pBuffer, uint8_t Size)
|
||||
{
|
||||
I2C_Start();
|
||||
|
||||
I2C_Write(0xA0);
|
||||
|
||||
I2C_Write((Address >> 8) & 0xFF);
|
||||
I2C_Write((Address >> 0) & 0xFF);
|
||||
|
||||
I2C_Start();
|
||||
|
||||
I2C_Write(0xA1);
|
||||
|
||||
I2C_ReadBuffer(pBuffer, Size);
|
||||
|
||||
I2C_Stop();
|
||||
}
|
||||
|
||||
void EEPROM_WriteBuffer(uint16_t Address, const void *pBuffer)
|
||||
|
||||
{
|
||||
I2C_Start();
|
||||
|
||||
I2C_Write(0xA0);
|
||||
|
||||
I2C_Write((Address >> 8) & 0xFF);
|
||||
I2C_Write((Address >> 0) & 0xFF);
|
||||
|
||||
I2C_WriteBuffer(pBuffer, 8);
|
||||
|
||||
I2C_Stop();
|
||||
|
||||
SYSTEM_DelayUs(10);
|
||||
}
|
||||
|
||||
26
driver/eeprom.h
Normal file
26
driver/eeprom.h
Normal file
@ -0,0 +1,26 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_EEPROM_H
|
||||
#define DRIVER_EEPROM_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void EEPROM_ReadBuffer(uint16_t Address, void *pBuffer, uint8_t Size);
|
||||
void EEPROM_WriteBuffer(uint16_t Address, const void *pBuffer);
|
||||
|
||||
#endif
|
||||
|
||||
34
driver/flash.c
Normal file
34
driver/flash.c
Normal file
@ -0,0 +1,34 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "driver/flash.h"
|
||||
#include "sram-overlay.h"
|
||||
|
||||
void FLASH_Init(FLASH_READ_MODE ReadMode)
|
||||
{
|
||||
overlay_FLASH_Init(ReadMode);
|
||||
}
|
||||
|
||||
void FLASH_ConfigureTrimValues(void)
|
||||
{
|
||||
overlay_FLASH_ConfigureTrimValues();
|
||||
}
|
||||
|
||||
uint32_t FLASH_ReadNvrWord(uint32_t Address)
|
||||
{
|
||||
return overlay_FLASH_ReadNvrWord(Address);
|
||||
}
|
||||
|
||||
59
driver/flash.h
Normal file
59
driver/flash.h
Normal file
@ -0,0 +1,59 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_FLASH_H
|
||||
#define DRIVER_FLASH_H
|
||||
|
||||
#include "bsp/dp32g030/flash.h"
|
||||
|
||||
enum FLASH_READ_MODE {
|
||||
FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_1_CYCLE,
|
||||
FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_2_CYCLE,
|
||||
};
|
||||
|
||||
typedef enum FLASH_READ_MODE FLASH_READ_MODE;
|
||||
|
||||
enum FLASH_MASK_SELECTION {
|
||||
FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_NONE,
|
||||
FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_2KB,
|
||||
FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_4KB,
|
||||
FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_8KB,
|
||||
};
|
||||
|
||||
typedef enum FLASH_MASK_SELECTION FLASH_MASK_SELECTION;
|
||||
|
||||
enum FLASH_MODE {
|
||||
FLASH_MODE_READ_AHB = FLASH_CFG_MODE_READ_AHB,
|
||||
FLASH_MODE_PROGRAM = FLASH_CFG_MODE_PROGRAM,
|
||||
FLASH_MODE_ERASE = FLASH_CFG_MODE_ERASE,
|
||||
FLASH_MODE_READ_APB = FLASH_CFG_MODE_READ_APB,
|
||||
};
|
||||
|
||||
typedef enum FLASH_MODE FLASH_MODE;
|
||||
|
||||
enum FLASH_AREA {
|
||||
FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_MAIN,
|
||||
FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_NVR,
|
||||
};
|
||||
|
||||
typedef enum FLASH_AREA FLASH_AREA;
|
||||
|
||||
void FLASH_Init(FLASH_READ_MODE ReadMode);
|
||||
void FLASH_ConfigureTrimValues(void);
|
||||
uint32_t FLASH_ReadNvrWord(uint32_t Address);
|
||||
|
||||
#endif
|
||||
|
||||
38
driver/gpio.c
Normal file
38
driver/gpio.c
Normal file
@ -0,0 +1,38 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "driver/gpio.h"
|
||||
|
||||
void GPIO_ClearBit(volatile uint32_t *pReg, uint8_t Bit)
|
||||
{
|
||||
*pReg &= ~(1U << Bit);
|
||||
}
|
||||
|
||||
uint8_t GPIO_CheckBit(volatile uint32_t *pReg, uint8_t Bit)
|
||||
{
|
||||
return (*pReg >> Bit) & 1U;
|
||||
}
|
||||
|
||||
void GPIO_FlipBit(volatile uint32_t *pReg, uint8_t Bit)
|
||||
{
|
||||
*pReg ^= 1U << Bit;
|
||||
}
|
||||
|
||||
void GPIO_SetBit(volatile uint32_t *pReg, uint8_t Bit)
|
||||
{
|
||||
*pReg |= 1U << Bit;
|
||||
}
|
||||
|
||||
39
driver/gpio.h
Normal file
39
driver/gpio.h
Normal file
@ -0,0 +1,39 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_GPIO_H
|
||||
#define DRIVER_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
enum GPIOA_PINS {
|
||||
GPIOA_I2C_SCL = 10,
|
||||
GPIOA_I2C_SDA = 11,
|
||||
};
|
||||
|
||||
enum GPIOC_PINS {
|
||||
GPIOC_BK4819_0 = 0,
|
||||
GPIOC_BK4819_1 = 1,
|
||||
GPIOC_BK4819_2 = 2,
|
||||
};
|
||||
|
||||
void GPIO_ClearBit(volatile uint32_t *pReg, uint8_t Bit);
|
||||
uint8_t GPIO_CheckBit(volatile uint32_t *pReg, uint8_t Bit);
|
||||
void GPIO_FlipBit(volatile uint32_t *pReg, uint8_t Bit);
|
||||
void GPIO_SetBit(volatile uint32_t *pReg, uint8_t Bit);
|
||||
|
||||
#endif
|
||||
|
||||
169
driver/i2c.c
Normal file
169
driver/i2c.c
Normal file
@ -0,0 +1,169 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "bsp/dp32g030/gpio.h"
|
||||
#include "bsp/dp32g030/portcon.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/i2c.h"
|
||||
#include "driver/systick.h"
|
||||
|
||||
void I2C_Start(void)
|
||||
{
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
}
|
||||
|
||||
void I2C_Stop(void)
|
||||
{
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
SYSTICK_Delay(1);
|
||||
}
|
||||
|
||||
uint8_t I2C_Read(bool bFinal)
|
||||
{
|
||||
uint8_t i, Data;
|
||||
|
||||
PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_ENABLE;
|
||||
PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;
|
||||
GPIOA->DIR &= ~GPIO_DIR_11_MASK;
|
||||
|
||||
Data = 0;
|
||||
for (i = 0; i < 8; i++) {
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
Data <<= 1;
|
||||
SYSTICK_Delay(1);
|
||||
if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_I2C_SDA)) {
|
||||
Data |= 1U;
|
||||
}
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
}
|
||||
|
||||
PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;
|
||||
PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_ENABLE;
|
||||
GPIOA->DIR |= GPIO_DIR_11_OUTPUT;
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
if (bFinal) {
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
} else {
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
}
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
|
||||
return Data;
|
||||
}
|
||||
|
||||
int I2C_Write(uint8_t Data)
|
||||
{
|
||||
uint8_t i;
|
||||
int ret = -1;
|
||||
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
for (i = 0; i < 8; i++) {
|
||||
if ((Data & 0x80) == 0) {
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
} else {
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
}
|
||||
Data <<= 1;
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
}
|
||||
|
||||
PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_ENABLE;
|
||||
PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;
|
||||
GPIOA->DIR &= ~GPIO_DIR_11_MASK;
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
SYSTICK_Delay(1);
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
|
||||
for (i = 0; i < 255; i++) {
|
||||
if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_I2C_SDA) == 0) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_ClearBit(&GPIOA->DATA, GPIOA_I2C_SCL);
|
||||
SYSTICK_Delay(1);
|
||||
PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;
|
||||
PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_ENABLE;
|
||||
GPIOA->DIR |= GPIO_DIR_11_OUTPUT;
|
||||
GPIO_SetBit(&GPIOA->DATA, GPIOA_I2C_SDA);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int I2C_ReadBuffer(void *pBuffer, uint8_t Size)
|
||||
{
|
||||
uint8_t *pData = (uint8_t *)pBuffer;
|
||||
uint8_t i;
|
||||
|
||||
if (Size == 1) {
|
||||
*pData = I2C_Read(true);
|
||||
return 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < Size - 1; i++) {
|
||||
SYSTICK_Delay(1);
|
||||
pData[i] = I2C_Read(false);
|
||||
}
|
||||
|
||||
SYSTICK_Delay(1);
|
||||
pData[i++] = I2C_Read(true);
|
||||
|
||||
return Size;
|
||||
}
|
||||
|
||||
int I2C_WriteBuffer(const void *pBuffer, uint8_t Size)
|
||||
{
|
||||
const uint8_t *pData = (const uint8_t *)pBuffer;
|
||||
uint8_t i;
|
||||
|
||||
for (i = 0; i < Size; i++) {
|
||||
if (I2C_Write(*pData++) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
33
driver/i2c.h
Normal file
33
driver/i2c.h
Normal file
@ -0,0 +1,33 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_I2C_H
|
||||
#define DRIVER_I2C_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void I2C_Start(void);
|
||||
void I2C_Stop(void);
|
||||
|
||||
uint8_t I2C_Read(bool bFinal);
|
||||
int I2C_Write(uint8_t Data);
|
||||
|
||||
int I2C_ReadBuffer(void *pBuffer, uint8_t Size);
|
||||
int I2C_WriteBuffer(const void *pBuffer, uint8_t Size);
|
||||
|
||||
#endif
|
||||
|
||||
116
driver/spi.c
Normal file
116
driver/spi.c
Normal file
@ -0,0 +1,116 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ARMCM0.h"
|
||||
#include "bsp/dp32g030/spi.h"
|
||||
#include "bsp/dp32g030/syscon.h"
|
||||
#include "bsp/dp32g030/irq.h"
|
||||
#include "driver/spi.h"
|
||||
|
||||
void SPI0_Init(void)
|
||||
{
|
||||
SPI_Config_t Config;
|
||||
|
||||
SPI_Disable(&SPI0->CR);
|
||||
|
||||
Config.TXFIFO_EMPTY = 0;
|
||||
Config.RXFIFO_HFULL = 0;
|
||||
Config.RXFIFO_FULL = 0;
|
||||
Config.RXFIFO_OVF = 0;
|
||||
Config.MSTR = 1;
|
||||
Config.SPR = 2;
|
||||
Config.CPHA = 1;
|
||||
Config.CPOL = 1;
|
||||
Config.LSB = 0;
|
||||
Config.TF_CLR = 0;
|
||||
Config.RF_CLR = 0;
|
||||
Config.TXFIFO_HFULL = 0;
|
||||
SPI_Configure(SPI0, &Config);
|
||||
|
||||
SPI_Enable(&SPI0->CR);
|
||||
}
|
||||
|
||||
void SPI_WaitForUndocumentedTxFifoStatusBit(void)
|
||||
{
|
||||
uint32_t Timeout;
|
||||
|
||||
Timeout = 0;
|
||||
do {
|
||||
// Undocumented bit!
|
||||
if ((SPI0->IF & 0x20) == 0) {
|
||||
break;
|
||||
}
|
||||
Timeout++;
|
||||
} while (Timeout <= 100000);
|
||||
}
|
||||
|
||||
void SPI_Disable(volatile uint32_t *pCR)
|
||||
{
|
||||
*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_DISABLE;
|
||||
}
|
||||
|
||||
void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig)
|
||||
{
|
||||
if (pPort == SPI0) {
|
||||
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_ENABLE;
|
||||
} else if (pPort == SPI1) {
|
||||
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_ENABLE;
|
||||
}
|
||||
|
||||
SPI_Disable(&pPort->CR);
|
||||
|
||||
pPort->CR = 0
|
||||
| (pPort->CR & ~(SPI_CR_SPR_MASK | SPI_CR_CPHA_MASK | SPI_CR_CPOL_MASK | SPI_CR_MSTR_MASK | SPI_CR_LSB_MASK | SPI_CR_RF_CLR_MASK))
|
||||
| ((pConfig->SPR << SPI_CR_SPR_SHIFT) & SPI_CR_SPR_MASK)
|
||||
| ((pConfig->CPHA << SPI_CR_CPHA_SHIFT) & SPI_CR_CPHA_MASK)
|
||||
| ((pConfig->CPOL << SPI_CR_CPOL_SHIFT) & SPI_CR_CPOL_MASK)
|
||||
| ((pConfig->MSTR << SPI_CR_MSTR_SHIFT) & SPI_CR_MSTR_MASK)
|
||||
| ((pConfig->LSB << SPI_CR_LSB_SHIFT) & SPI_CR_LSB_MASK)
|
||||
| ((pConfig->RF_CLR << SPI_CR_RF_CLR_SHIFT) & SPI_CR_RF_CLR_MASK)
|
||||
| ((pConfig->TF_CLR << SPI_CR_TF_CLR_SHIFT) & SPI_CR_TF_CLR_MASK)
|
||||
;
|
||||
|
||||
pPort->IE = 0
|
||||
| ((pConfig->RXFIFO_OVF << SPI_IE_RXFIFO_OVF_SHIFT) & SPI_IE_RXFIFO_OVF_MASK)
|
||||
| ((pConfig->RXFIFO_FULL << SPI_IE_RXFIFO_FULL_SHIFT) & SPI_IE_RXFIFO_FULL_MASK)
|
||||
| ((pConfig->RXFIFO_HFULL << SPI_IE_RXFIFO_HFULL_SHIFT) & SPI_IE_RXFIFO_HFULL_MASK)
|
||||
| ((pConfig->TXFIFO_EMPTY << SPI_IE_TXFIFO_EMPTY_SHIFT) & SPI_IE_TXFIFO_EMPTY_MASK)
|
||||
| ((pConfig->TXFIFO_HFULL << SPI_IE_TXFIFO_HFULL_SHIFT) & SPI_IE_TXFIFO_HFULL_MASK)
|
||||
;
|
||||
|
||||
if (pPort->IE) {
|
||||
if (pPort == SPI0) {
|
||||
NVIC_EnableIRQ(DP32_SPI0_IRQn);
|
||||
} else if (pPort == SPI1) {
|
||||
NVIC_EnableIRQ(DP32_SPI1_IRQn);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void SPI_ToggleMasterMode(volatile uint32_t *pCR, bool bIsMaster)
|
||||
{
|
||||
if (bIsMaster) {
|
||||
*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_ENABLE;
|
||||
} else {
|
||||
*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
void SPI_Enable(volatile uint32_t *pCR)
|
||||
{
|
||||
*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_ENABLE;
|
||||
}
|
||||
|
||||
47
driver/spi.h
Normal file
47
driver/spi.h
Normal file
@ -0,0 +1,47 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SPI_H
|
||||
#define DRIVER_SPI_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
uint8_t MSTR;
|
||||
uint8_t SPR;
|
||||
uint8_t CPHA;
|
||||
uint8_t CPOL;
|
||||
uint8_t LSB;
|
||||
uint8_t TF_CLR;
|
||||
uint8_t RF_CLR;
|
||||
uint8_t TXFIFO_HFULL;
|
||||
uint8_t TXFIFO_EMPTY;
|
||||
uint8_t RXFIFO_HFULL;
|
||||
uint8_t RXFIFO_FULL;
|
||||
uint8_t RXFIFO_OVF;
|
||||
} SPI_Config_t;
|
||||
|
||||
void SPI0_Init(void);
|
||||
void SPI_WaitForUndocumentedTxFifoStatusBit(void);
|
||||
|
||||
void SPI_Disable(volatile uint32_t *pCR);
|
||||
void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig);
|
||||
void SPI_ToggleMasterMode(volatile uint32_t *pCr, bool bIsMaster);
|
||||
void SPI_Enable(volatile uint32_t *pCR);
|
||||
|
||||
#endif
|
||||
|
||||
176
driver/st7565.c
Normal file
176
driver/st7565.c
Normal file
@ -0,0 +1,176 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "bsp/dp32g030/gpio.h"
|
||||
#include "bsp/dp32g030/spi.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/spi.h"
|
||||
#include "driver/st7565.h"
|
||||
#include "driver/system.h"
|
||||
|
||||
uint8_t gStatusLine[128];
|
||||
uint8_t gFrameBuffer[7][128];
|
||||
|
||||
void ST7565_DrawLine(uint8_t Column, uint8_t Line, uint16_t Size, const uint8_t *pBitmap, bool bIsClearMode)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
SPI_ToggleMasterMode(&SPI0->CR, false);
|
||||
ST7565_SelectColumnAndLine(Column + 4U, Line);
|
||||
GPIO_SetBit(&GPIOB->DATA, 9);
|
||||
|
||||
if (bIsClearMode == false) {
|
||||
for (i = 0; i < Size; i++) {
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = pBitmap[i];
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < Size; i++) {
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = 0;
|
||||
}
|
||||
}
|
||||
|
||||
SPI_WaitForUndocumentedTxFifoStatusBit();
|
||||
SPI_ToggleMasterMode(&SPI0->CR, true);
|
||||
}
|
||||
|
||||
void ST7565_BlitFullScreen(void)
|
||||
{
|
||||
uint8_t Line;
|
||||
uint8_t Column;
|
||||
|
||||
SPI_ToggleMasterMode(&SPI0->CR,false);
|
||||
ST7565_WriteByte(0x40);
|
||||
|
||||
for (Line = 0; Line < 7; Line++) {
|
||||
ST7565_SelectColumnAndLine(4U, Line + 1U);
|
||||
GPIO_SetBit(&GPIOB->DATA, 9U);
|
||||
for (Column = 0; Column < 128; Column++) {
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = gFrameBuffer[Line][Column];
|
||||
}
|
||||
SPI_WaitForUndocumentedTxFifoStatusBit();
|
||||
}
|
||||
|
||||
SYSTEM_DelayUs(20);
|
||||
SPI_ToggleMasterMode(&SPI0->CR, true);
|
||||
}
|
||||
|
||||
void ST7565_BlitStatusLine(void)
|
||||
{
|
||||
uint8_t i;
|
||||
|
||||
SPI_ToggleMasterMode(&SPI0->CR, false);
|
||||
ST7565_WriteByte(0x40);
|
||||
ST7565_SelectColumnAndLine(4, 0);
|
||||
GPIO_SetBit(&GPIOB->DATA, 9);
|
||||
|
||||
for (i = 0; i < 0x80; i++) {
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = gStatusLine[i];
|
||||
}
|
||||
SPI_WaitForUndocumentedTxFifoStatusBit();
|
||||
SPI_ToggleMasterMode(&SPI0->CR, true);
|
||||
}
|
||||
|
||||
void ST7565_FillScreen(uint8_t Value)
|
||||
{
|
||||
uint8_t i, j;
|
||||
|
||||
SPI_ToggleMasterMode(&SPI0->CR, false);
|
||||
for (i = 0; i < 8; i++) {
|
||||
ST7565_SelectColumnAndLine(0, i);
|
||||
GPIO_SetBit(&GPIOB->DATA, 9);
|
||||
for (j = 0; j < 132; j++) {
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = Value;
|
||||
}
|
||||
SPI_WaitForUndocumentedTxFifoStatusBit();
|
||||
}
|
||||
SPI_ToggleMasterMode(&SPI0->CR, true);
|
||||
}
|
||||
|
||||
void ST7565_Init(void)
|
||||
{
|
||||
SPI0_Init();
|
||||
ST7565_Configure_GPIO_B11();
|
||||
SPI_ToggleMasterMode(&SPI0->CR, false);
|
||||
ST7565_WriteByte(0xE2);
|
||||
SYSTEM_DelayUs(0x78);
|
||||
ST7565_WriteByte(0xA2);
|
||||
ST7565_WriteByte(0xC0);
|
||||
ST7565_WriteByte(0xA1);
|
||||
ST7565_WriteByte(0xA6);
|
||||
ST7565_WriteByte(0xA4);
|
||||
ST7565_WriteByte(0x24);
|
||||
ST7565_WriteByte(0x81);
|
||||
ST7565_WriteByte(0x1F);
|
||||
ST7565_WriteByte(0x2B);
|
||||
SYSTEM_DelayUs(1);
|
||||
ST7565_WriteByte(0x2E);
|
||||
SYSTEM_DelayUs(1);
|
||||
ST7565_WriteByte(0x2F);
|
||||
ST7565_WriteByte(0x2F);
|
||||
ST7565_WriteByte(0x2F);
|
||||
ST7565_WriteByte(0x2F);
|
||||
SYSTEM_DelayUs(0x28);
|
||||
ST7565_WriteByte(0x40);
|
||||
ST7565_WriteByte(0xAF);
|
||||
SPI_WaitForUndocumentedTxFifoStatusBit();
|
||||
SPI_ToggleMasterMode(&SPI0->CR, true);
|
||||
ST7565_FillScreen(0x00);
|
||||
}
|
||||
|
||||
void ST7565_Configure_GPIO_B11(void)
|
||||
{
|
||||
GPIO_SetBit(&GPIOB->DATA, 11);
|
||||
SYSTEM_DelayUs(1);
|
||||
GPIO_ClearBit(&GPIOB->DATA, 11);
|
||||
SYSTEM_DelayUs(20);
|
||||
GPIO_SetBit(&GPIOB->DATA, 11);
|
||||
SYSTEM_DelayUs(120);
|
||||
}
|
||||
|
||||
void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line)
|
||||
{
|
||||
GPIO_ClearBit(&GPIOB->DATA, 9);
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = Line + 0xB0;
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = ((Column >> 4) & 0x0F) | 0x10;
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = ((Column >> 0) & 0x0F);
|
||||
SPI_WaitForUndocumentedTxFifoStatusBit();
|
||||
}
|
||||
|
||||
void ST7565_WriteByte(uint8_t Value)
|
||||
{
|
||||
GPIO_ClearBit(&GPIOB->DATA, 9);
|
||||
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) {
|
||||
}
|
||||
SPI0->WDR = Value;
|
||||
}
|
||||
|
||||
36
driver/st7565.h
Normal file
36
driver/st7565.h
Normal file
@ -0,0 +1,36 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ST7565_H
|
||||
#define DRIVER_ST7565_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint8_t gStatusLine[128];
|
||||
extern uint8_t gFrameBuffer[7][128];
|
||||
|
||||
void ST7565_DrawLine(uint8_t Column, uint8_t Line, uint16_t Size, const uint8_t *pBitmap, bool bIsClearMode);
|
||||
void ST7565_BlitFullScreen(void);
|
||||
void ST7565_BlitStatusLine(void);
|
||||
void ST7565_FillScreen(uint8_t Value);
|
||||
void ST7565_Init(void);
|
||||
void ST7565_Configure_GPIO_B11(void);
|
||||
void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line);
|
||||
void ST7565_WriteByte(uint8_t Value);
|
||||
|
||||
#endif
|
||||
|
||||
38
driver/system.c
Normal file
38
driver/system.c
Normal file
@ -0,0 +1,38 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "bsp/dp32g030/pmu.h"
|
||||
#include "bsp/dp32g030/syscon.h"
|
||||
#include "driver/system.h"
|
||||
#include "driver/systick.h"
|
||||
|
||||
void SYSTEM_DelayUs(uint32_t Delay)
|
||||
{
|
||||
SYSTICK_Delay(Delay * 1000);
|
||||
}
|
||||
|
||||
void SYSTEM_ConfigureClocks(void)
|
||||
{
|
||||
// Set source clock from external crystal
|
||||
PMU_SRC_CFG = (PMU_SRC_CFG & ~PMU_SRC_CFG_RTC_CLK_SEL_MASK) | PMU_SRC_CFG_RTC_CLK_SEL_XTAL;
|
||||
|
||||
// Divide by 2
|
||||
SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_CLK_SEL_2;
|
||||
|
||||
// Disable division clock gate
|
||||
SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_DISABLE;
|
||||
}
|
||||
|
||||
26
driver/system.h
Normal file
26
driver/system.h
Normal file
@ -0,0 +1,26 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SYSTEM_H
|
||||
#define DRIVER_SYSTEM_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void SYSTEM_DelayUs(uint32_t Delay);
|
||||
void SYSTEM_ConfigureClocks(void);
|
||||
|
||||
#endif
|
||||
|
||||
53
driver/systick.c
Normal file
53
driver/systick.c
Normal file
@ -0,0 +1,53 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ARMCM0.h"
|
||||
#include "driver/systick.h"
|
||||
|
||||
// 0x20000324
|
||||
static uint32_t gTickMultiplier;
|
||||
|
||||
void SYSTICK_Init(void)
|
||||
{
|
||||
SysTick_Config(480000);
|
||||
gTickMultiplier = 48;
|
||||
}
|
||||
|
||||
void SYSTICK_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t Start;
|
||||
uint32_t Previous;
|
||||
uint32_t Current;
|
||||
uint32_t Delta;
|
||||
|
||||
i = 0;
|
||||
Start = SysTick->LOAD;
|
||||
Previous = SysTick->VAL;
|
||||
do {
|
||||
do {
|
||||
Current = SysTick->VAL;
|
||||
} while (Current == Previous);
|
||||
if (Current < Previous) {
|
||||
Delta = -Current;
|
||||
} else {
|
||||
Delta = Start - Current;
|
||||
}
|
||||
i += Delta + Previous;
|
||||
Previous = Current;
|
||||
} while (i < Delay * gTickMultiplier);
|
||||
}
|
||||
|
||||
26
driver/systick.h
Normal file
26
driver/systick.h
Normal file
@ -0,0 +1,26 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SYSTICK_H
|
||||
#define DRIVER_SYSTICK_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void SYSTICK_Init(void);
|
||||
void SYSTICK_Delay(uint32_t Delay);
|
||||
|
||||
#endif
|
||||
|
||||
96
driver/uart.c
Normal file
96
driver/uart.c
Normal file
@ -0,0 +1,96 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "bsp/dp32g030/dma.h"
|
||||
#include "bsp/dp32g030/syscon.h"
|
||||
#include "bsp/dp32g030/uart.h"
|
||||
#include "driver/uart.h"
|
||||
|
||||
uint8_t UART_DMA_Buffer[256];
|
||||
|
||||
void UART_Init(void)
|
||||
{
|
||||
uint32_t Delta;
|
||||
uint32_t Positive;
|
||||
uint32_t Frequency;
|
||||
|
||||
UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_DISABLE;
|
||||
Delta = SYSCON_RC_FREQ_DELTA;
|
||||
Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
|
||||
Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
|
||||
if (Positive) {
|
||||
Frequency += 48000000U;
|
||||
} else {
|
||||
Frequency = 48000000U - Frequency;
|
||||
}
|
||||
|
||||
UART1->BAUD = Frequency / 39053U;
|
||||
UART1->CTRL = UART_CTRL_RXEN_ENABLE | UART_CTRL_TXEN_ENABLE | UART_CTRL_RXDMAEN_ENABLE;
|
||||
UART1->RXTO = 4;
|
||||
UART1->FC = 0;
|
||||
UART1->FIFO = UART_FIFO_RF_LEVEL_8_BYTE | UART_FIFO_RF_CLR_ENABLE | UART_FIFO_TF_CLR_ENABLE;
|
||||
UART1->IE = 0;
|
||||
|
||||
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_DISABLE;
|
||||
|
||||
DMA_CH0->MSADDR = (uint32_t)(uintptr_t)&UART1->RDR;
|
||||
DMA_CH0->MDADDR = (uint32_t)(uintptr_t)UART_DMA_Buffer;
|
||||
DMA_CH0->MOD = 0
|
||||
// Source
|
||||
| DMA_CH_MOD_MS_ADDMOD_NONE
|
||||
| DMA_CH_MOD_MS_SIZE_8BIT
|
||||
| DMA_CH_MOD_MS_SEL_HSREQ_MS1
|
||||
// Destination
|
||||
| DMA_CH_MOD_MD_ADDMOD_INCREMENT
|
||||
| DMA_CH_MOD_MD_SIZE_8BIT
|
||||
| DMA_CH_MOD_MD_SEL_SRAM
|
||||
;
|
||||
DMA_INTEN = 0;
|
||||
DMA_INTST = 0
|
||||
| DMA_INTST_CH0_TC_INTST_SET
|
||||
| DMA_INTST_CH1_TC_INTST_SET
|
||||
| DMA_INTST_CH2_TC_INTST_SET
|
||||
| DMA_INTST_CH3_TC_INTST_SET
|
||||
| DMA_INTST_CH0_THC_INTST_SET
|
||||
| DMA_INTST_CH1_THC_INTST_SET
|
||||
| DMA_INTST_CH2_THC_INTST_SET
|
||||
| DMA_INTST_CH3_THC_INTST_SET
|
||||
;
|
||||
DMA_CH0->CTR = 0
|
||||
| DMA_CH_CTR_CH_EN_ENABLE
|
||||
| ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK)
|
||||
| DMA_CH_CTR_LOOP_ENABLE
|
||||
| DMA_CH_CTR_PRI_MEDIUM
|
||||
;
|
||||
UART1->IF = UART_IF_RXTO_SET;
|
||||
|
||||
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_ENABLE;
|
||||
|
||||
UART1->CTRL |= UART_CTRL_UARTEN_ENABLE;
|
||||
}
|
||||
|
||||
void UART_Send(const void *pBuffer, uint32_t Size)
|
||||
{
|
||||
const uint8_t *pData = (const uint8_t *)pBuffer;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < Size; i++) {
|
||||
UART1->TDR = pData[i];
|
||||
while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_NOT_SET) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
29
driver/uart.h
Normal file
29
driver/uart.h
Normal file
@ -0,0 +1,29 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_UART_H
|
||||
#define DRIVER_UART_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint8_t UART_DMA_Buffer[256];
|
||||
|
||||
void UART_Init(void);
|
||||
void UART_Send(const void *pBuffer, uint32_t Size);
|
||||
|
||||
#endif
|
||||
|
||||
1
external/CMSIS_5
vendored
Submodule
1
external/CMSIS_5
vendored
Submodule
@ -0,0 +1 @@
|
||||
Subproject commit a75f01746df18bb5b929dfb8dc6c9407fac3a0f3
|
||||
73
firmware.ld
Normal file
73
firmware.ld
Normal file
@ -0,0 +1,73 @@
|
||||
ENTRY(HandlerReset)
|
||||
|
||||
_estack = 0x20004000; /* end of 16K RAM */
|
||||
|
||||
_Min_Heap_Size = 0; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x80; /* required amount of stack */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 60K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text.isr) /* .text sections of code */
|
||||
*(.text) /* .text sections of code */
|
||||
*(.text*) /* .text* sections of code */
|
||||
*(.rodata) /* .rodata sections */
|
||||
*(.rodata*) /* .rodata* sections */
|
||||
*(.glue_7) /* Glue arm to thumb code */
|
||||
*(.glue_7t) /* Glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP(*(.fini))
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* global symbols at end */
|
||||
} >FLASH
|
||||
|
||||
/* Used by startup code */
|
||||
_sidata = .;
|
||||
|
||||
/* Data sections go into RAM */
|
||||
.data : AT ( _sidata )
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* Global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* Global symbol at data end */
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
_sbss = .; /* Global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* Global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* Check that there is enough RAM */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
}
|
||||
|
||||
67
gen-overlay-symbols.sh
Executable file
67
gen-overlay-symbols.sh
Executable file
@ -0,0 +1,67 @@
|
||||
#!/bin/bash
|
||||
|
||||
usage()
|
||||
{
|
||||
echo "$0 <ELF> <ASM>"
|
||||
exit 1
|
||||
}
|
||||
|
||||
if [ "x$1" == "x" ]
|
||||
then
|
||||
usage
|
||||
return 1
|
||||
fi
|
||||
if [ "x$2" == "x" ]
|
||||
then
|
||||
usage
|
||||
return 1
|
||||
fi
|
||||
|
||||
echo "# .text section" > "$2"
|
||||
echo "" >> "$2"
|
||||
|
||||
arm-none-eabi-nm -g "$1" | grep " T " | sort |
|
||||
while read SYM
|
||||
do
|
||||
ADDR=$(echo $SYM | cut -f 1 -d " ")
|
||||
FUNC=$(echo $SYM | cut -f 3 -d " ")
|
||||
echo ".global $FUNC" >> "$2"
|
||||
if [ "$FUNC" = "overlay_text_start" ] || [ "$FUNC" = "overlay_text_end" ]
|
||||
then
|
||||
echo "$FUNC = 0x$ADDR;" >> "$2"
|
||||
else
|
||||
echo "$FUNC:" >> "$2"
|
||||
echo "push {r4, lr}" >> "$2"
|
||||
echo "ldr r4, =(0x$ADDR + 1)" >> "$2"
|
||||
echo "blx r4" >> "$2"
|
||||
echo "pop {r4, pc}" >> "$2"
|
||||
fi
|
||||
echo "" >> "$2"
|
||||
done
|
||||
|
||||
echo "# .bss section" >> "$2"
|
||||
echo "" >> "$2"
|
||||
|
||||
arm-none-eabi-nm -g sram-overlay | grep " B " | sort |
|
||||
while read SYM
|
||||
do
|
||||
ADDR=$(echo $SYM | cut -f 1 -d " ")
|
||||
DATA=$(echo $SYM | cut -f 3 -d " ")
|
||||
echo ".global $DATA" >> "$2"
|
||||
echo "$DATA = 0x$ADDR;" >> "$2"
|
||||
echo "" >> "$2"
|
||||
done
|
||||
|
||||
echo "# .data section" >> "$2"
|
||||
echo "" >> "$2"
|
||||
|
||||
arm-none-eabi-nm -g sram-overlay | grep " D " | sort |
|
||||
while read SYM
|
||||
do
|
||||
ADDR=$(echo $SYM | cut -f 1 -d " ")
|
||||
DATA=$(echo $SYM | cut -f 3 -d " ")
|
||||
echo ".global $DATA" >> "$2"
|
||||
echo "$DATA = 0x$ADDR;" >> "$2"
|
||||
echo "" >> "$2"
|
||||
done
|
||||
|
||||
58
hardware/dp32g030/crc.def
Normal file
58
hardware/dp32g030/crc.def
Normal file
@ -0,0 +1,58 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[CRC]
|
||||
@ = 0x40003000, 0x800
|
||||
|
||||
CR = 0x0000
|
||||
> CRC_EN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> INPUT_REV, 1, 1
|
||||
= NORMAL, 0
|
||||
= REVERSED, 1
|
||||
|
||||
> INPUT_INV, 2, 2
|
||||
= NORMAL, 0
|
||||
= BIT_INVERTED, 1
|
||||
= BYTE_INVERTED, 2
|
||||
= BIT_BYTE_INVERTED, 3
|
||||
|
||||
> OUTPUT_REV, 4, 1
|
||||
= NORMAL, 0
|
||||
= REVERSED, 1
|
||||
|
||||
> OUTPUT_INV, 5, 2
|
||||
= NORMAL, 0
|
||||
= BIT_INVERTED, 1
|
||||
= BYTE_INVERTED, 2
|
||||
= BIT_BYTE_INVERTED, 3
|
||||
|
||||
> DATA_WIDTH, 7, 2
|
||||
= 32, 0
|
||||
= 16, 1
|
||||
= 8, 2
|
||||
|
||||
> CRC_SEL, 9, 2
|
||||
= CRC_16_CCITT, 0
|
||||
= CRC_8_ATM, 1
|
||||
= CRC_16, 2
|
||||
= CRC_32_IEEE802_3, 3
|
||||
|
||||
IV = 0x0004
|
||||
DATAIN = 0x0008
|
||||
DATAOUT = 0x000C
|
||||
|
||||
169
hardware/dp32g030/dma.def
Normal file
169
hardware/dp32g030/dma.def
Normal file
@ -0,0 +1,169 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[DMA]
|
||||
@ = 0x40001000, 0x100
|
||||
|
||||
CTR = 0x0000
|
||||
> DMAEN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
INTEN = 0x0004
|
||||
> CH0_TC_INTEN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH1_TC_INTEN, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH2_TC_INTEN, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH3_TC_INTEN, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH0_THC_INTEN, 8, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH1_THC_INTEN, 9, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH2_THC_INTEN, 10, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CH3_THC_INTEN, 11, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
INTST = 0x0008
|
||||
> CH0_TC_INTST, 0, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH1_TC_INTST, 1, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH2_TC_INTST, 2, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH3_TC_INTST, 3, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH0_THC_INTST, 8, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH1_THC_INTST, 9, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH2_THC_INTST, 10, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> CH3_THC_INTST, 11, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
[DMA_CH]
|
||||
$ = DMA_Channel_t
|
||||
|
||||
CTR = 0x0000
|
||||
> CH_EN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> LENGTH, 1, 12
|
||||
|
||||
> LOOP, 13, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PRI, 14, 2
|
||||
= LOW, 0
|
||||
= MEDIUM, 1
|
||||
= HIGH, 2
|
||||
= HIGHEST, 3
|
||||
|
||||
> SWREQ, 16, 1
|
||||
= SET, 1
|
||||
|
||||
MOD = 0x0004
|
||||
> MS_ADDMOD, 0, 1
|
||||
= NONE, 0
|
||||
= INCREMENT, 1
|
||||
|
||||
> MS_SIZE, 1, 2
|
||||
= 8BIT, 0
|
||||
= 16BIT, 1
|
||||
= 32BIT, 2
|
||||
= KEEP, 3
|
||||
|
||||
> MS_SEL, 3, 3
|
||||
= SRAM, 0
|
||||
= HSREQ_MS0, 1
|
||||
= HSREQ_MS1, 2
|
||||
= HSREQ_MS2, 3
|
||||
= HSREQ_MS3, 4
|
||||
= HSREQ_MS4, 5
|
||||
= HSREQ_MS5, 6
|
||||
= HSREQ_MS6, 7
|
||||
|
||||
> MD_ADDMOD, 8, 1
|
||||
= NONE, 0
|
||||
= INCREMENT, 1
|
||||
|
||||
> MD_SIZE, 9, 2
|
||||
= 8BIT, 0
|
||||
= 16BIT, 1
|
||||
= 32BIT, 2
|
||||
= KEEP, 3
|
||||
|
||||
> MD_SEL, 11, 3
|
||||
= SRAM, 0
|
||||
= HSREQ_MS0, 1
|
||||
= HSREQ_MS1, 2
|
||||
= HSREQ_MS2, 3
|
||||
= HSREQ_MS3, 4
|
||||
= HSREQ_MS4, 5
|
||||
= HSREQ_MS5, 6
|
||||
= HSREQ_MS6, 7
|
||||
|
||||
MSADDR = 0x0008
|
||||
MDADDR = 0x000C
|
||||
ST = 0x0010
|
||||
|
||||
[DMA_CH0]
|
||||
@ = 0x40001100, 0x20, $DMA_CH
|
||||
|
||||
[DMA_CH1]
|
||||
@ = 0x40001120, 0x20, $DMA_CH
|
||||
|
||||
[DMA_CH2]
|
||||
@ = 0x40001140, 0x20, $DMA_CH
|
||||
|
||||
[DMA_CH3]
|
||||
@ = 0x40001160, 0x20, $DMA_CH
|
||||
|
||||
85
hardware/dp32g030/flash.def
Normal file
85
hardware/dp32g030/flash.def
Normal file
@ -0,0 +1,85 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[FLASH]
|
||||
@ = 0x4006F000, 0x800
|
||||
|
||||
CFG = 0x0000
|
||||
> READ_MD, 0, 1
|
||||
= 1_CYCLE, 0
|
||||
= 2_CYCLE, 1
|
||||
|
||||
> NVR_SEL, 1, 1
|
||||
= MAIN, 0
|
||||
= NVR, 1
|
||||
|
||||
> MODE, 2, 3
|
||||
= READ_AHB, 0
|
||||
= PROGRAM, 1
|
||||
= ERASE, 2
|
||||
= READ_APB, 5
|
||||
|
||||
> DEEP_PD, 31, 1
|
||||
= NORMAL, 0
|
||||
= LOW_POWER, 1
|
||||
|
||||
ADDR = 0x0004
|
||||
WDATA = 0x0008
|
||||
RDATA = 0x000C
|
||||
|
||||
START = 0x0010
|
||||
> START, 0, 1
|
||||
= START, 1
|
||||
|
||||
ST = 0x0014
|
||||
> INIT_BUSY, 0, 1
|
||||
= COMPLETE, 0
|
||||
= BUSY, 1
|
||||
|
||||
> BUSY, 1, 1
|
||||
= READY, 0
|
||||
= BUSY, 1
|
||||
|
||||
> PROG_BUF_EMPTY, 2, 1
|
||||
= NOT_EMPTY, 0
|
||||
= EMPTY, 1
|
||||
|
||||
LOCK = 0x0018
|
||||
> LOCK, 0, 8
|
||||
= LOCK, 0x55
|
||||
|
||||
UNLOCK = 0x001C
|
||||
> UNLOCK, 0, 8
|
||||
= UNLOCK, 0xAA
|
||||
|
||||
MASK = 0x0020
|
||||
> SEL, 0, 2
|
||||
= NONE, 0
|
||||
= 2KB, 1
|
||||
= 4KB, 2
|
||||
= 8KB, 3
|
||||
|
||||
> LOCK, 2, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
ERASETIME = 0x0024
|
||||
> TERASE, 0, 19
|
||||
> TRCV, 19, 12
|
||||
|
||||
PROGTIME = 0x0028
|
||||
> TPROG, 0, 11
|
||||
> TPGS, 11, 11
|
||||
|
||||
93
hardware/dp32g030/gpio.def
Normal file
93
hardware/dp32g030/gpio.def
Normal file
@ -0,0 +1,93 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[GPIO]
|
||||
$ = GPIO_Bank_t
|
||||
|
||||
DATA = 0x0000
|
||||
DIR = 0x0004
|
||||
> 0, 0, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 1, 1, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 2, 2, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 3, 3, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 4, 4, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 5, 5, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 6, 6, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 7, 7, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 8, 8, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 9, 9, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 10, 10, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 11, 11, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 12, 12, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 13, 13, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 14, 14, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
> 15, 15, 1
|
||||
= INPUT, 0
|
||||
= OUTPUT, 1
|
||||
|
||||
[GPIOA]
|
||||
@ = 0x40060000, 0x800, $GPIO
|
||||
|
||||
[GPIOB]
|
||||
@ = 0x40060800, 0x800, $GPIO
|
||||
|
||||
[GPIOC]
|
||||
@ = 0x40061000, 0x800, $GPIO
|
||||
|
||||
33
hardware/dp32g030/pmu.def
Normal file
33
hardware/dp32g030/pmu.def
Normal file
@ -0,0 +1,33 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[PMU]
|
||||
@ = 0x40000800, 0x800
|
||||
|
||||
SRC_CFG = 0x0010
|
||||
> RTC_CLK_SEL, 4, 1
|
||||
= RCLF, 0
|
||||
= XTAL, 1
|
||||
|
||||
TRIM_POW0 = 0x0020
|
||||
TRIM_POW1 = 0x0024
|
||||
TRIM_POW2 = 0x0028
|
||||
TRIM_POW3 = 0x002C
|
||||
|
||||
TRIM_RCHF = 0x0030
|
||||
TRIM_RCLF = 0x0034
|
||||
TRIM_OPA = 0x0038
|
||||
TRIM_PLL = 0x003C
|
||||
|
||||
1090
hardware/dp32g030/portcon.def
Normal file
1090
hardware/dp32g030/portcon.def
Normal file
File diff suppressed because it is too large
Load Diff
26
hardware/dp32g030/saradc.def
Normal file
26
hardware/dp32g030/saradc.def
Normal file
@ -0,0 +1,26 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[SARADC]
|
||||
@ = 0x400BA000, 0x800
|
||||
|
||||
ADC_CALIB_OFFSET = 0x00F0
|
||||
> OFFSET, 0, 8
|
||||
> OFFSET_VALID, 16, 1
|
||||
|
||||
ADC_CALIB_KD = 0x00F4
|
||||
> KD, 0, 8
|
||||
> KD_VALID, 16, 1
|
||||
|
||||
124
hardware/dp32g030/spi.def
Normal file
124
hardware/dp32g030/spi.def
Normal file
@ -0,0 +1,124 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[SPI]
|
||||
$ = SPI_Port_t
|
||||
|
||||
CR = 0x0000
|
||||
> TF_CLR, 16, 1
|
||||
> RF_CLR, 15, 1
|
||||
> TXDMAEN, 14, 1
|
||||
> RXDMAEN, 13, 1
|
||||
|
||||
> MSR_SSN, 12, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CPHA_DATA_HOLD_S, 8, 4
|
||||
> LSB, 7, 1
|
||||
> MSTR, 6, 1
|
||||
> CPOL, 5, 1
|
||||
> CPHA, 4, 1
|
||||
|
||||
> SPE, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SPR, 0, 3
|
||||
= FPCLK_DIV_4, 0
|
||||
= FPCLK_DIV_8, 1
|
||||
= FPCLK_DIV_16, 2
|
||||
= FPCLK_DIV_32, 3
|
||||
= FPCLK_DIV_64, 4
|
||||
= FPCLK_DIV_128, 5
|
||||
= FPCLK_DIV_256, 6
|
||||
= FPCLK_DIV_512, 7
|
||||
|
||||
WDR = 0x0004
|
||||
RDR = 0x0008
|
||||
|
||||
IE = 0x0010
|
||||
> RXFIFO_OVF, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO_FULL, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO_HFULL, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXFIFO_EMPTY, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXFIFO_HFULL, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
IF = 0x0014
|
||||
FIFOST = 0x0018
|
||||
> RFE, 0, 1
|
||||
= NOT_EMPTY, 0
|
||||
= EMPTY, 1
|
||||
|
||||
> RFF, 1, 1
|
||||
= NOT_FULL, 0
|
||||
= FULL, 1
|
||||
|
||||
> RFHF, 2, 1
|
||||
= NOT_HALF_FULL, 0
|
||||
= HALF_FULL, 1
|
||||
|
||||
> TFE, 3, 1
|
||||
= NOT_EMPTY, 0
|
||||
= EMPTY, 1
|
||||
|
||||
> TFF, 4, 1
|
||||
= NOT_FULL, 0
|
||||
= FULL, 1
|
||||
|
||||
> TFHF, 5, 1
|
||||
= NOT_HALF_FULL, 0
|
||||
= HALF_FULL, 1
|
||||
|
||||
> RF_LEVEL, 6, 3
|
||||
= 0_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
> TF_LEVEL, 9, 3
|
||||
= 0_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
[SPI0]
|
||||
@ = 0x400B8000, 0x800, $SPI
|
||||
|
||||
[SPI1]
|
||||
@ = 0x400B8800, 0x800, $SPI
|
||||
|
||||
157
hardware/dp32g030/syscon.def
Normal file
157
hardware/dp32g030/syscon.def
Normal file
@ -0,0 +1,157 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[SYSCON]
|
||||
@ = 0x40000000, 0x800
|
||||
|
||||
CLK_SEL = 0x0000
|
||||
> SYS_CLK_SEL, 0, 1
|
||||
= RCHF, 0
|
||||
= DIV_CLK, 1
|
||||
|
||||
> DIV_CLK_SEL, 1, 3
|
||||
= 1, 0
|
||||
= 2, 1
|
||||
= 4, 2
|
||||
= 8, 3
|
||||
= 16, 4
|
||||
= 32, 5
|
||||
|
||||
> SRC_CLK_SEL, 4, 3
|
||||
= RCHF, 0
|
||||
= RCLF, 1
|
||||
= XTAH, 2
|
||||
= XTAL, 3
|
||||
= PLL, 4
|
||||
|
||||
DIV_CLK_GATE = 0x0004
|
||||
> DIV_CLK_GATE, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
DEV_CLK_GATE = 0x0008
|
||||
> GPIOA, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> GPIOB, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> GPIOC, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> IIC0, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> IIC1, 5, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> UART0, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> UART1, 7, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> UART2, 8, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SPI0, 10, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SPI1, 11, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_BASE0, 12, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_BASE1, 13, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_BASE2, 14, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_PLUS0, 15, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TIMER_PLUS1, 16, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_BASE0, 17, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_BASE1, 18, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_PLUS0, 20, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PWM_PLUS1, 21, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RTC, 22, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> IWDT, 23, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> WWDT, 24, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> SARADC, 25, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CRC, 27, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> AES, 28, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
RC_FREQ_DELTA = 0x0078
|
||||
> RCLF_DELTA, 0, 10
|
||||
> RCLF_SIG, 10, 1
|
||||
> RCHF_DELTA, 11, 20
|
||||
> RCHF_SIG, 31, 1
|
||||
|
||||
VREF_VOLT_DELTA = 0x007C
|
||||
|
||||
CHIP_ID0 = 0x0080
|
||||
CHIP_ID1 = 0x0084
|
||||
CHIP_ID2 = 0x0088
|
||||
CHIP_ID3 = 0x008C
|
||||
|
||||
230
hardware/dp32g030/uart.def
Normal file
230
hardware/dp32g030/uart.def
Normal file
@ -0,0 +1,230 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
[UART]
|
||||
$ = UART_Port_t
|
||||
|
||||
CTRL = 0x0000
|
||||
> UARTEN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXEN, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXEN, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXDMAEN, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXDMAEN, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> NINEBIT, 5, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PAREN, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
BAUD = 0x0004
|
||||
TDR = 0x0008
|
||||
RDR = 0x000C
|
||||
|
||||
IE = 0x0010
|
||||
> TXDONE, 2, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> PARITYE, 3, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> STOPE, 4, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXTO, 5, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TXFIFO, 7, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RXFIFO_OVF, 8, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> ABRD_OVF, 9, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
IF = 0x0014
|
||||
> TXDONE, 2, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> PARITYE, 3, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> STOPE, 4, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXTO, 5, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO, 6, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO, 7, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_OVF, 8, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> ABRD_OVF, 9, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_EMPTY, 10, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_FULL, 11, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RXFIFO_HFULL, 12, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO_EMPTY, 13, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO_FULL, 14, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXFIFO_HFULL, 15, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> TXBUSY, 16, 1
|
||||
= NOT_SET, 0
|
||||
= SET, 1
|
||||
|
||||
> RF_LEVEL, 17, 3
|
||||
= 0_8_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
> TF_LEVEL, 20, 3
|
||||
= 0_8_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
FIFO = 0x0018
|
||||
> RF_LEVEL, 0, 3
|
||||
= 1_BYTE, 0
|
||||
= 2_BYTE, 1
|
||||
= 3_BYTE, 2
|
||||
= 4_BYTE, 3
|
||||
= 5_BYTE, 4
|
||||
= 6_BYTE, 5
|
||||
= 7_BYTE, 6
|
||||
= 8_BYTE, 7
|
||||
|
||||
> TF_LEVEL, 3, 3
|
||||
= 0_BYTE, 0
|
||||
= 1_BYTE, 1
|
||||
= 2_BYTE, 2
|
||||
= 3_BYTE, 3
|
||||
= 4_BYTE, 4
|
||||
= 5_BYTE, 5
|
||||
= 6_BYTE, 6
|
||||
= 7_BYTE, 7
|
||||
|
||||
> RF_CLR, 6, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> TF_CLR, 7, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
FC = 0x001C
|
||||
> CTSEN, 0, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> RTSEN, 1, 1
|
||||
= DISABLE, 0
|
||||
= ENABLE, 1
|
||||
|
||||
> CTSPOL, 2, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
> RTSPOL, 3, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
> CTS_SIGNAL, 4, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
> RTS_SIGNAL, 5, 1
|
||||
= LOW, 0
|
||||
= HIGH, 1
|
||||
|
||||
RXTO = 0x0020
|
||||
|
||||
[UART0]
|
||||
@ = 0x4006B000, 0x800, $UART
|
||||
|
||||
[UART1]
|
||||
@ = 0x4006B800, 0x800, $UART
|
||||
|
||||
[UART2]
|
||||
@ = 0x4006C000, 0x800, $UART
|
||||
|
||||
35
init.c
Normal file
35
init.c
Normal file
@ -0,0 +1,35 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint8_t __bss_start__[];
|
||||
extern uint8_t __bss_end__[];
|
||||
|
||||
void BSS_Init(void)
|
||||
{
|
||||
uint8_t *pBss;
|
||||
|
||||
for (pBss = __bss_start__; pBss < __bss_end__; pBss++) {
|
||||
*pBss = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void DATA_Init(void)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
92
main.c
Normal file
92
main.c
Normal file
@ -0,0 +1,92 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "ARMCM0.h"
|
||||
|
||||
#include "bsp/dp32g030/gpio.h"
|
||||
#include "bsp/dp32g030/portcon.h"
|
||||
#include "bsp/dp32g030/syscon.h"
|
||||
#include "board.h"
|
||||
#include "driver/crc.h"
|
||||
#include "driver/eeprom.h"
|
||||
#include "driver/flash.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/st7565.h"
|
||||
#include "driver/systick.h"
|
||||
#include "driver/uart.h"
|
||||
|
||||
static const char Version[] = "UV-K5 Firmware, v0.01 Open Edition\r\n";
|
||||
|
||||
static void FLASHLIGHT_Init(void)
|
||||
{
|
||||
PORTCON_PORTC_IE = PORTCON_PORTC_IE_C5_ENABLE;
|
||||
PORTCON_PORTC_PU = PORTCON_PORTC_PU_C5_ENABLE;
|
||||
GPIOC->DIR |= GPIO_DIR_3_OUTPUT;
|
||||
|
||||
GPIO_SetBit(&GPIOC->DATA, 10);
|
||||
GPIO_SetBit(&GPIOC->DATA, 11);
|
||||
GPIO_SetBit(&GPIOC->DATA, 12);
|
||||
GPIO_SetBit(&GPIOC->DATA, 13);
|
||||
}
|
||||
|
||||
static void FLASHLIGHT_TurnOn(void)
|
||||
{
|
||||
GPIO_SetBit(&GPIOC->DATA, 3);
|
||||
}
|
||||
|
||||
static void BACKLIGHT_TurnOn(void)
|
||||
{
|
||||
GPIO_SetBit(&GPIOB->DATA, 6);
|
||||
}
|
||||
|
||||
void Main(void)
|
||||
{
|
||||
// Enable clock gating of blocks we need.
|
||||
SYSCON_DEV_CLK_GATE = 0
|
||||
| SYSCON_DEV_CLK_GATE_GPIOA_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_GPIOB_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_GPIOC_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_UART1_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_SPI0_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_SARADC_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_CRC_ENABLE
|
||||
| SYSCON_DEV_CLK_GATE_AES_ENABLE
|
||||
;
|
||||
|
||||
SYSTICK_Init();
|
||||
BOARD_Init();
|
||||
|
||||
UART_Init();
|
||||
UART_Send(Version, sizeof(Version));
|
||||
|
||||
// Show some signs of life
|
||||
FLASHLIGHT_Init();
|
||||
FLASHLIGHT_TurnOn();
|
||||
BACKLIGHT_TurnOn();
|
||||
|
||||
static const uint8_t TestBitmap0[8] = { 0x80, 0x80, 0x80, 0x80, 0x08, 0x08, 0x08, 0x08 };
|
||||
static const uint8_t TestBitmap1[8] = { 0x10, 0x10, 0x10, 0x10, 0x01, 0x01, 0x01, 0x01 };
|
||||
ST7565_DrawLine(16, 1, 8, TestBitmap0, false);
|
||||
ST7565_DrawLine(24, 3, 8, TestBitmap1, false);
|
||||
|
||||
uint8_t Test[8];
|
||||
EEPROM_ReadBuffer(0x0EB0, Test, 8);
|
||||
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
66
overlay.c
Normal file
66
overlay.c
Normal file
@ -0,0 +1,66 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint8_t overlay_text_start[];
|
||||
extern uint8_t overlay_text_end[];
|
||||
|
||||
extern uint8_t overlay_bss_start[];
|
||||
extern uint8_t overlay_bss_end[];
|
||||
|
||||
extern uint8_t overlay_data_start[];
|
||||
extern uint8_t overlay_data_end[];
|
||||
|
||||
extern const uint8_t sram_overlay_bin[];
|
||||
|
||||
void OVERLAY_Install(void)
|
||||
{
|
||||
uint8_t *pStart;
|
||||
uint8_t *pEnd;
|
||||
const uint8_t *pIn;
|
||||
uint8_t *pOut;
|
||||
|
||||
// Text
|
||||
pStart = overlay_text_start;
|
||||
pEnd = overlay_text_end;
|
||||
|
||||
pIn = sram_overlay_bin;
|
||||
|
||||
for (pOut = pStart; pOut < pEnd; ) {
|
||||
*pOut++ = *pIn++;
|
||||
}
|
||||
|
||||
// Data
|
||||
pStart = overlay_data_start;
|
||||
pEnd = overlay_data_end;
|
||||
|
||||
pIn = sram_overlay_bin;
|
||||
pIn += overlay_data_start - overlay_text_start;
|
||||
|
||||
for (pOut = pStart; pOut < pEnd; ) {
|
||||
*pOut++ = *pIn++;
|
||||
}
|
||||
|
||||
// BSS
|
||||
pStart = overlay_bss_start;
|
||||
pEnd = overlay_bss_end;
|
||||
|
||||
for (pOut = pStart; pOut < pEnd; ) {
|
||||
*pOut++ = 0;
|
||||
}
|
||||
}
|
||||
|
||||
23
overlay.h
Normal file
23
overlay.h
Normal file
@ -0,0 +1,23 @@
|
||||
/* Copyright 2023 Dual Tachyon
|
||||
* https://github.com/DualTachyon
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef OVERLAY_H
|
||||
#define OVERLAY_H
|
||||
|
||||
void OVERLAY_Install(void);
|
||||
|
||||
#endif
|
||||
|
||||
195
sram-overlay.c
Normal file
195
sram-overlay.c
Normal file
@ -0,0 +1,195 @@
|
||||
#include "ARMCM0.h"
|
||||
#include "bsp/dp32g030/pmu.h"
|
||||
#include "bsp/dp32g030/saradc.h"
|
||||
#include "bsp/dp32g030/syscon.h"
|
||||
#include "sram-overlay.h"
|
||||
|
||||
uint32_t overlay_FLASH_MainClock;
|
||||
uint32_t overlay_FLASH_ClockMultiplier;
|
||||
uint32_t overlay_0x20000478; // Nothing is using this???
|
||||
|
||||
bool overlay_FLASH_RebootToBootloader(void)
|
||||
{
|
||||
overlay_FLASH_MaskUnlock();
|
||||
overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION_NONE);
|
||||
overlay_FLASH_MaskLock();
|
||||
overlay_SystemReset();
|
||||
|
||||
return (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_READY;
|
||||
}
|
||||
|
||||
bool overlay_FLASH_IsBusy(void)
|
||||
{
|
||||
return (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_READY;
|
||||
}
|
||||
|
||||
bool overlay_FLASH_IsInitComplete(void)
|
||||
{
|
||||
return (FLASH_ST & FLASH_ST_INIT_BUSY_MASK) == FLASH_ST_INIT_BUSY_COMPLETE;
|
||||
}
|
||||
|
||||
void overlay_FLASH_Start(void)
|
||||
{
|
||||
overlay_FLASH_Unlock();
|
||||
FLASH_START |= FLASH_START_START_START;
|
||||
}
|
||||
|
||||
void overlay_FLASH_Init(FLASH_READ_MODE ReadMode)
|
||||
{
|
||||
overlay_FLASH_WakeFromDeepSleep();
|
||||
overlay_FLASH_SetMode(FLASH_MODE_READ_AHB);
|
||||
overlay_FLASH_SetReadMode(ReadMode);
|
||||
overlay_FLASH_SetEraseTime();
|
||||
overlay_FLASH_SetProgramTime();
|
||||
overlay_FLASH_Lock();
|
||||
}
|
||||
|
||||
void overlay_FLASH_MaskLock(void)
|
||||
{
|
||||
FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_SET;
|
||||
}
|
||||
|
||||
void overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION Mask)
|
||||
{
|
||||
FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_SEL_MASK) | (Mask & FLASH_MASK_SEL_MASK);
|
||||
}
|
||||
|
||||
void overlay_FLASH_MaskUnlock(void)
|
||||
{
|
||||
FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_NOT_SET;
|
||||
}
|
||||
|
||||
void overlay_FLASH_Lock(void)
|
||||
{
|
||||
FLASH_LOCK = FLASH_LOCK_LOCK_LOCK;
|
||||
}
|
||||
|
||||
void overlay_FLASH_Unlock(void)
|
||||
{
|
||||
FLASH_UNLOCK = FLASH_UNLOCK_UNLOCK_UNLOCK;
|
||||
}
|
||||
|
||||
uint32_t overlay_FLASH_ReadByAHB(uint32_t Offset)
|
||||
{
|
||||
return *(volatile uint32_t *)(Offset & ~3U);
|
||||
}
|
||||
|
||||
uint32_t overlay_FLASH_ReadByAPB(uint32_t Offset)
|
||||
{
|
||||
uint32_t Data;
|
||||
|
||||
while (overlay_FLASH_IsBusy()) {
|
||||
}
|
||||
|
||||
overlay_FLASH_SetMode(FLASH_MODE_READ_APB);
|
||||
FLASH_ADDR = Offset >> 2;
|
||||
|
||||
overlay_FLASH_Start();
|
||||
|
||||
while (overlay_FLASH_IsBusy()) {
|
||||
}
|
||||
|
||||
Data = FLASH_RDATA;
|
||||
|
||||
overlay_FLASH_SetMode(FLASH_MODE_READ_AHB);
|
||||
overlay_FLASH_Lock();
|
||||
|
||||
return Data;
|
||||
}
|
||||
|
||||
void overlay_FLASH_SetArea(FLASH_AREA Area)
|
||||
{
|
||||
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_NVR_SEL_MASK) | (Area & FLASH_CFG_NVR_SEL_MASK);
|
||||
}
|
||||
|
||||
void overlay_FLASH_SetReadMode(FLASH_READ_MODE Mode)
|
||||
{
|
||||
if (Mode == FLASH_READ_MODE_1_CYCLE) {
|
||||
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_1_CYCLE;
|
||||
} else if (Mode == FLASH_READ_MODE_2_CYCLE) {
|
||||
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_2_CYCLE;
|
||||
}
|
||||
}
|
||||
|
||||
void overlay_FLASH_SetEraseTime(void)
|
||||
{
|
||||
FLASH_ERASETIME = ((overlay_FLASH_ClockMultiplier & 0xFFFFU) * 0x1A00000U) + (overlay_FLASH_ClockMultiplier * 3600U);
|
||||
}
|
||||
|
||||
void overlay_FLASH_WakeFromDeepSleep(void)
|
||||
{
|
||||
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_DEEP_PD_MASK) | FLASH_CFG_DEEP_PD_NORMAL;
|
||||
while (!overlay_FLASH_IsInitComplete()) {
|
||||
}
|
||||
}
|
||||
|
||||
void overlay_FLASH_SetMode(FLASH_MODE Mode)
|
||||
{
|
||||
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_MODE_MASK) | (Mode & FLASH_CFG_MODE_MASK);
|
||||
return;
|
||||
}
|
||||
|
||||
void overlay_FLASH_SetProgramTime(void)
|
||||
{
|
||||
FLASH_PROGTIME = overlay_FLASH_ClockMultiplier * 45074;
|
||||
}
|
||||
|
||||
void overlay_SystemReset(void)
|
||||
{
|
||||
// Lifted from core_cm0.h to preserve function order in the object file.
|
||||
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t overlay_FLASH_ReadNvrWord(uint32_t Offset)
|
||||
{
|
||||
uint32_t Data;
|
||||
|
||||
overlay_FLASH_SetArea(FLASH_AREA_NVR);
|
||||
|
||||
Data = overlay_FLASH_ReadByAHB(Offset);
|
||||
|
||||
overlay_FLASH_SetArea(FLASH_AREA_MAIN);
|
||||
|
||||
return Data;
|
||||
}
|
||||
|
||||
void overlay_FLASH_ConfigureTrimValues(void)
|
||||
{
|
||||
uint32_t Data;
|
||||
|
||||
overlay_FLASH_SetArea(FLASH_AREA_NVR);
|
||||
|
||||
SYSCON_CHIP_ID0 = overlay_FLASH_ReadByAPB(0xF018);
|
||||
SYSCON_CHIP_ID1 = overlay_FLASH_ReadByAPB(0xF01C);
|
||||
SYSCON_CHIP_ID2 = overlay_FLASH_ReadByAPB(0xF020);
|
||||
SYSCON_CHIP_ID3 = overlay_FLASH_ReadByAPB(0xF024);
|
||||
|
||||
SYSCON_RC_FREQ_DELTA = overlay_FLASH_ReadByAHB(0x07C8);
|
||||
SYSCON_VREF_VOLT_DELTA = overlay_FLASH_ReadByAHB(0x07C4);
|
||||
|
||||
PMU_TRIM_POW0 = overlay_FLASH_ReadByAHB(0x07E4);
|
||||
PMU_TRIM_POW1 = overlay_FLASH_ReadByAHB(0x07E0);
|
||||
PMU_TRIM_RCHF = overlay_FLASH_ReadByAHB(0x07D8);
|
||||
PMU_TRIM_RCLF = overlay_FLASH_ReadByAHB(0x07D4);
|
||||
PMU_TRIM_OPA = overlay_FLASH_ReadByAHB(0x07D0);
|
||||
PMU_TRIM_PLL = overlay_FLASH_ReadByAHB(0x07CC);
|
||||
|
||||
overlay_0x20000478 = overlay_FLASH_ReadByAHB(0x07B8);
|
||||
|
||||
Data = overlay_FLASH_ReadByAHB(0x07BC);
|
||||
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_ENABLE;
|
||||
SARADC_ADC_CALIB_OFFSET = ((Data & 0xFFFF) << SARADC_ADC_CALIB_OFFSET_OFFSET_SHIFT) & SARADC_ADC_CALIB_OFFSET_OFFSET_MASK;
|
||||
SARADC_ADC_CALIB_KD = (((Data >> 16) & 0xFFFF) << SARADC_ADC_CALIB_KD_KD_SHIFT) & SARADC_ADC_CALIB_KD_KD_MASK;
|
||||
overlay_FLASH_SetArea(FLASH_AREA_MAIN);
|
||||
}
|
||||
|
||||
35
sram-overlay.h
Normal file
35
sram-overlay.h
Normal file
@ -0,0 +1,35 @@
|
||||
#ifndef OVERLAY_H
|
||||
#define OVERLAY_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "driver/flash.h"
|
||||
|
||||
extern uint32_t overlay_FLASH_MainClock;
|
||||
extern uint32_t overlay_FLASH_ClockMultiplier;
|
||||
extern uint32_t overlay_0x20000478;
|
||||
|
||||
bool overlay_FLASH_RebootToBootloader(void);
|
||||
bool overlay_FLASH_IsBusy(void);
|
||||
bool overlay_FLASH_IsInitComplete(void);
|
||||
void overlay_FLASH_Start(void);
|
||||
void overlay_FLASH_Init(FLASH_READ_MODE ReadMode);
|
||||
void overlay_FLASH_MaskLock(void);
|
||||
void overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION Mask);
|
||||
void overlay_FLASH_MaskUnlock(void);
|
||||
void overlay_FLASH_Lock(void);
|
||||
void overlay_FLASH_Unlock(void);
|
||||
uint32_t overlay_FLASH_ReadByAHB(uint32_t Offset);
|
||||
uint32_t overlay_FLASH_ReadByAPB(uint32_t Offset);
|
||||
void overlay_FLASH_Set_NVR_SEL(FLASH_AREA Area);
|
||||
void overlay_FLASH_SetReadMode(FLASH_READ_MODE Mode);
|
||||
void overlay_FLASH_SetEraseTime(void);
|
||||
void overlay_FLASH_WakeFromDeepSleep(void);
|
||||
void overlay_FLASH_SetMode(FLASH_MODE Mode);
|
||||
void overlay_FLASH_SetProgramTime(void);
|
||||
void overlay_SystemReset(void);
|
||||
uint32_t overlay_FLASH_ReadNvrWord(uint32_t Offset);
|
||||
void overlay_FLASH_ConfigureTrimValues(void);
|
||||
|
||||
#endif
|
||||
|
||||
45
sram-overlay.ld
Normal file
45
sram-overlay.ld
Normal file
@ -0,0 +1,45 @@
|
||||
ENTRY(overlay_FLASH_RebootToBootloader)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
SRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 1K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
overlay_text_start = .;
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
overlay_text_end = .;
|
||||
} >SRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
.data :
|
||||
{
|
||||
overlay_data_start = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
overlay_data_end = .;
|
||||
} >SRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
overlay_bss_start = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
overlay_bss_end = .;
|
||||
} >SRAM
|
||||
}
|
||||
|
||||
251
start.S
Normal file
251
start.S
Normal file
@ -0,0 +1,251 @@
|
||||
# Copyright 2023 Dual Tachyon
|
||||
# https://github.com/DualTachyon
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
.cpu cortex-m0
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Stack
|
||||
.global HandlerReset
|
||||
.global Main
|
||||
|
||||
.global OVERLAY_Install
|
||||
.global BOARD_FLASH_Init
|
||||
.global BSS_Init
|
||||
|
||||
.global SystickHandler
|
||||
.weak SystickHandler
|
||||
|
||||
.section .text.isr
|
||||
|
||||
Stack:
|
||||
.long 0x20003FF0
|
||||
Reset:
|
||||
.long HandlerReset + 1
|
||||
NMI:
|
||||
.long HandlerNMI + 1
|
||||
HardFault:
|
||||
.long HandlerHardFault + 1
|
||||
Reserved_10:
|
||||
.long 0
|
||||
Reserved_14:
|
||||
.long 0
|
||||
Reserved_18:
|
||||
.long 0
|
||||
Reserved_1C:
|
||||
.long 0
|
||||
Reserved_20:
|
||||
.long 0
|
||||
Reserved_24:
|
||||
.long 0
|
||||
Reserved_28:
|
||||
.long 0
|
||||
SVCall:
|
||||
.long HandlerSVCall + 1
|
||||
Reserved_30:
|
||||
.long 0
|
||||
Reserved_34:
|
||||
.long 0
|
||||
PendSV:
|
||||
.long HandlerPendSV + 1
|
||||
SysTick:
|
||||
.long SystickHandler + 1
|
||||
WWDT:
|
||||
.long HandlerWWDT + 1
|
||||
IWDT:
|
||||
.long HandlerIWDT + 1
|
||||
RTC:
|
||||
.long HandlerRTC + 1
|
||||
DMA:
|
||||
.long HandlerDMA + 1
|
||||
SARADC:
|
||||
.long HandlerSARADC + 1
|
||||
TIMER_BASE0:
|
||||
.long HandlerTIMER_BASE0 + 1
|
||||
TIMER_BASE1:
|
||||
.long HandlerTIMER_BASE1 + 1
|
||||
TIMER_PLUS0:
|
||||
.long HandlerTIMER_PLUS0 + 1
|
||||
TIMER_PLUS1:
|
||||
.long HandlerTIMER_PLUS1 + 1
|
||||
PWM_BASE0:
|
||||
.long HandlerPWM_BASE0 + 1
|
||||
PWM_BASE1:
|
||||
.long HandlerPWM_BASE1 + 1
|
||||
PWM_PLUS0:
|
||||
.long HandlerPWM_PLUS0 + 1
|
||||
PWM_PLUS1:
|
||||
.long HandlerPWM_PLUS1 + 1
|
||||
UART0:
|
||||
.long HandlerUART0 + 1
|
||||
UART1:
|
||||
.long HandlerUART1 + 1
|
||||
UART2:
|
||||
.long HandlerUART2 + 1
|
||||
SPI0:
|
||||
.long HandlerSPI0 + 1
|
||||
SPI1:
|
||||
.long HandlerSPI1 + 1
|
||||
IIC0:
|
||||
.long HandlerIIC0 + 1
|
||||
IIC1:
|
||||
.long HandlerIIC1 + 1
|
||||
CMP:
|
||||
.long HandlerCMP + 1
|
||||
TIMER_BASE2:
|
||||
.long HandlerTIMER_BASE2 + 1
|
||||
GPIOA5:
|
||||
.long HandlerGPIOA5 + 1
|
||||
GPIOA6:
|
||||
.long HandlerGPIOA6 + 1
|
||||
GPIOA7:
|
||||
.long HandlerGPIOA7 + 1
|
||||
GPIOB0:
|
||||
.long HandlerGPIOB0 + 1
|
||||
GPIOB1:
|
||||
.long HandlerGPIOB1 + 1
|
||||
GPIOC0:
|
||||
.long HandlerGPIOC0 + 1
|
||||
GPIOC1:
|
||||
.long HandlerGPIOC1 + 1
|
||||
GPIOA:
|
||||
.long HandlerGPIOA + 1
|
||||
GPIOB:
|
||||
.long HandlerGPIOB + 1
|
||||
GPIOC:
|
||||
.long HandlerGPIOC + 1
|
||||
|
||||
.section .text
|
||||
|
||||
HandlerNMI:
|
||||
b .
|
||||
|
||||
HandlerHardFault:
|
||||
b .
|
||||
|
||||
HandlerSVCall:
|
||||
b .
|
||||
|
||||
HandlerPendSV:
|
||||
b .
|
||||
|
||||
SystickHandler:
|
||||
bx lr
|
||||
|
||||
HandlerWWDT:
|
||||
b .
|
||||
|
||||
HandlerIWDT:
|
||||
b .
|
||||
|
||||
HandlerRTC:
|
||||
b .
|
||||
|
||||
HandlerDMA:
|
||||
b .
|
||||
|
||||
HandlerSARADC:
|
||||
b .
|
||||
|
||||
HandlerTIMER_BASE0:
|
||||
b .
|
||||
|
||||
HandlerTIMER_BASE1:
|
||||
b .
|
||||
|
||||
HandlerTIMER_PLUS0:
|
||||
b .
|
||||
|
||||
HandlerTIMER_PLUS1:
|
||||
b .
|
||||
|
||||
HandlerPWM_BASE0:
|
||||
b .
|
||||
|
||||
HandlerPWM_BASE1:
|
||||
b .
|
||||
|
||||
HandlerPWM_PLUS0:
|
||||
b .
|
||||
|
||||
HandlerPWM_PLUS1:
|
||||
b .
|
||||
|
||||
HandlerUART0:
|
||||
b .
|
||||
|
||||
HandlerUART1:
|
||||
b .
|
||||
|
||||
HandlerUART2:
|
||||
b .
|
||||
|
||||
HandlerSPI0:
|
||||
b .
|
||||
|
||||
HandlerSPI1:
|
||||
b .
|
||||
|
||||
HandlerIIC0:
|
||||
b .
|
||||
|
||||
HandlerIIC1:
|
||||
b .
|
||||
|
||||
HandlerCMP:
|
||||
b .
|
||||
|
||||
HandlerTIMER_BASE2:
|
||||
b .
|
||||
|
||||
HandlerGPIOA5:
|
||||
b .
|
||||
|
||||
HandlerGPIOA6:
|
||||
b .
|
||||
|
||||
HandlerGPIOA7:
|
||||
b .
|
||||
|
||||
HandlerGPIOB0:
|
||||
b .
|
||||
|
||||
HandlerGPIOB1:
|
||||
b .
|
||||
|
||||
HandlerGPIOC0:
|
||||
b .
|
||||
|
||||
HandlerGPIOC1:
|
||||
b .
|
||||
|
||||
HandlerGPIOA:
|
||||
b .
|
||||
|
||||
HandlerGPIOB:
|
||||
b .
|
||||
|
||||
HandlerGPIOC:
|
||||
b .
|
||||
|
||||
HandlerReset:
|
||||
ldr r0, =0x20003FF0
|
||||
mov sp, r0
|
||||
bl OVERLAY_Install
|
||||
bl BOARD_FLASH_Init
|
||||
bl BSS_Init
|
||||
bl Main
|
||||
b .
|
||||
|
||||
Loading…
Reference in New Issue
Block a user