From c013f1a7c7948dc111c2998e2a52263b3175c27c Mon Sep 17 00:00:00 2001 From: Dual Tachyon Date: Sat, 12 Aug 2023 20:01:34 +0100 Subject: [PATCH] Fixed previous commit, now we run at 48MHz. --- bsp/dp32g030/pmu.h | 14 +++++++------- driver/system.c | 4 ++-- hardware/dp32g030/pmu.def | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/bsp/dp32g030/pmu.h b/bsp/dp32g030/pmu.h index ca2530f..7727474 100644 --- a/bsp/dp32g030/pmu.h +++ b/bsp/dp32g030/pmu.h @@ -35,13 +35,13 @@ #define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE 1U #define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT) -#define PMU_SRC_CFG_XTAH_EN_SHIFT 2 -#define PMU_SRC_CFG_XTAH_EN_WIDTH 1 -#define PMU_SRC_CFG_XTAH_EN_MASK (((1U << PMU_SRC_CFG_XTAH_EN_WIDTH) - 1U) << PMU_SRC_CFG_XTAH_EN_SHIFT) -#define PMU_SRC_CFG_XTAH_EN_VALUE_DISABLE 0U -#define PMU_SRC_CFG_XTAH_EN_BITS_DISABLE (PMU_SRC_CFG_XTAH_EN_VALUE_DISABLE << PMU_SRC_CFG_XTAH_EN_SHIFT) -#define PMU_SRC_CFG_XTAH_EN_VALUE_ENABLE 1U -#define PMU_SRC_CFG_XTAH_EN_BITS_ENABLE (PMU_SRC_CFG_XTAH_EN_VALUE_ENABLE << PMU_SRC_CFG_XTAH_EN_SHIFT) +#define PMU_SRC_CFG_RCHF_SEL_SHIFT 1 +#define PMU_SRC_CFG_RCHF_SEL_WIDTH 1 +#define PMU_SRC_CFG_RCHF_SEL_MASK (((1U << PMU_SRC_CFG_RCHF_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_SEL_SHIFT) +#define PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ 0U +#define PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT) +#define PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ 1U +#define PMU_SRC_CFG_RCHF_SEL_BITS_24MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT) #define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U) #define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR) diff --git a/driver/system.c b/driver/system.c index 976d1d6..989d2fb 100644 --- a/driver/system.c +++ b/driver/system.c @@ -27,8 +27,8 @@ void SYSTEM_DelayMs(uint32_t Delay) void SYSTEM_ConfigureClocks(void) { // Set source clock from external crystal - PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_XTAH_EN_MASK | PMU_SRC_CFG_RCHF_EN_MASK)) - | PMU_SRC_CFG_XTAH_EN_BITS_DISABLE + PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK)) + | PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ | PMU_SRC_CFG_RCHF_EN_BITS_ENABLE; // Divide by 2 diff --git a/hardware/dp32g030/pmu.def b/hardware/dp32g030/pmu.def index db146ee..b923780 100644 --- a/hardware/dp32g030/pmu.def +++ b/hardware/dp32g030/pmu.def @@ -17,9 +17,9 @@ @ = 0x40000800, 0x800 SRC_CFG = 0x0010 -> XTAH_EN, 2, 1 -= DISABLE, 0 -= ENABLE, 1 +> RCHF_SEL, 1, 1 += 48MHZ, 0 += 24MHZ, 1 > RCHF_EN, 0, 1 = DISABLE, 0