zhangyuheng/custom-uv-k5-firmware
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Fixed previous commit, now we run at 48MHz.

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Dual Tachyon 2023-08-12 20:01:34 +01:00
parent 9367ed2591
commit c013f1a7c7
3 changed files with 12 additions and 12 deletions
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14
bsp/dp32g030/pmu.h
View File

@ -35,13 +35,13 @@
#define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE 1U
#define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)
#define PMU_SRC_CFG_XTAH_EN_SHIFT 2
#define PMU_SRC_CFG_XTAH_EN_WIDTH 1
#define PMU_SRC_CFG_XTAH_EN_MASK (((1U << PMU_SRC_CFG_XTAH_EN_WIDTH) - 1U) << PMU_SRC_CFG_XTAH_EN_SHIFT)
#define PMU_SRC_CFG_XTAH_EN_VALUE_DISABLE 0U
#define PMU_SRC_CFG_XTAH_EN_BITS_DISABLE (PMU_SRC_CFG_XTAH_EN_VALUE_DISABLE << PMU_SRC_CFG_XTAH_EN_SHIFT)
#define PMU_SRC_CFG_XTAH_EN_VALUE_ENABLE 1U
#define PMU_SRC_CFG_XTAH_EN_BITS_ENABLE (PMU_SRC_CFG_XTAH_EN_VALUE_ENABLE << PMU_SRC_CFG_XTAH_EN_SHIFT)
#define PMU_SRC_CFG_RCHF_SEL_SHIFT 1
#define PMU_SRC_CFG_RCHF_SEL_WIDTH 1
#define PMU_SRC_CFG_RCHF_SEL_MASK (((1U << PMU_SRC_CFG_RCHF_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_SEL_SHIFT)
#define PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ 0U
#define PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT)
#define PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ 1U
#define PMU_SRC_CFG_RCHF_SEL_BITS_24MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT)
#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U)
#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR)

4
driver/system.c
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@ -27,8 +27,8 @@ void SYSTEM_DelayMs(uint32_t Delay)
void SYSTEM_ConfigureClocks(void)
{
// Set source clock from external crystal
PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_XTAH_EN_MASK | PMU_SRC_CFG_RCHF_EN_MASK))
| PMU_SRC_CFG_XTAH_EN_BITS_DISABLE
PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK))
| PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ
| PMU_SRC_CFG_RCHF_EN_BITS_ENABLE;
// Divide by 2

6
hardware/dp32g030/pmu.def
View File

@ -17,9 +17,9 @@
@ = 0x40000800, 0x800
SRC_CFG = 0x0010
> XTAH_EN, 2, 1
= DISABLE, 0
= ENABLE, 1
> RCHF_SEL, 1, 1
= 48MHZ, 0
= 24MHZ, 1
> RCHF_EN, 0, 1
= DISABLE, 0