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Fixed 2 bugs with PMU and SYSCON.

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This commit is contained in:
Dual Tachyon 2023-08-12 19:44:09 +01:00
parent 0e4868df43
commit 2dcfd96f8c
5 changed files with 47 additions and 33 deletions
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62
bsp/dp32g030/pmu.h
View File

@ -22,35 +22,43 @@
#endif
/* -------- PMU -------- */
#define PMU_BASE_ADDR 0x40000800U
#define PMU_BASE_SIZE 0x00000800U
#define PMU_BASE_ADDR 0x40000800U
#define PMU_BASE_SIZE 0x00000800U
#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U)
#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR)
#define PMU_SRC_CFG_RTC_CLK_SEL_SHIFT 4
#define PMU_SRC_CFG_RTC_CLK_SEL_WIDTH 1
#define PMU_SRC_CFG_RTC_CLK_SEL_MASK (((1U << PMU_SRC_CFG_RTC_CLK_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT)
#define PMU_SRC_CFG_RTC_CLK_SEL_VALUE_RCLF 0U
#define PMU_SRC_CFG_RTC_CLK_SEL_BITS_RCLF (PMU_SRC_CFG_RTC_CLK_SEL_VALUE_RCLF << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT)
#define PMU_SRC_CFG_RTC_CLK_SEL_VALUE_XTAL 1U
#define PMU_SRC_CFG_RTC_CLK_SEL_BITS_XTAL (PMU_SRC_CFG_RTC_CLK_SEL_VALUE_XTAL << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT)
#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U)
#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR)
#define PMU_SRC_CFG_RCHF_EN_SHIFT 0
#define PMU_SRC_CFG_RCHF_EN_WIDTH 1
#define PMU_SRC_CFG_RCHF_EN_MASK (((1U << PMU_SRC_CFG_RCHF_EN_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_EN_SHIFT)
#define PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE 0U
#define PMU_SRC_CFG_RCHF_EN_BITS_DISABLE (PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)
#define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE 1U
#define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)
#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U)
#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR)
#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U)
#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR)
#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U)
#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR)
#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU)
#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR)
#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U)
#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR)
#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U)
#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR)
#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U)
#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR)
#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU)
#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR)
#define PMU_SRC_CFG_XTAH_EN_SHIFT 2
#define PMU_SRC_CFG_XTAH_EN_WIDTH 1
#define PMU_SRC_CFG_XTAH_EN_MASK (((1U << PMU_SRC_CFG_XTAH_EN_WIDTH) - 1U) << PMU_SRC_CFG_XTAH_EN_SHIFT)
#define PMU_SRC_CFG_XTAH_EN_VALUE_DISABLE 0U
#define PMU_SRC_CFG_XTAH_EN_BITS_DISABLE (PMU_SRC_CFG_XTAH_EN_VALUE_DISABLE << PMU_SRC_CFG_XTAH_EN_SHIFT)
#define PMU_SRC_CFG_XTAH_EN_VALUE_ENABLE 1U
#define PMU_SRC_CFG_XTAH_EN_BITS_ENABLE (PMU_SRC_CFG_XTAH_EN_VALUE_ENABLE << PMU_SRC_CFG_XTAH_EN_SHIFT)
#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U)
#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR)
#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U)
#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR)
#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U)
#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR)
#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU)
#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR)
#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U)
#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR)
#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U)
#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR)
#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U)
#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR)
#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU)
#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR)
#endif

2
bsp/dp32g030/syscon.h
View File

@ -107,7 +107,7 @@
#define SYSCON_DIV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0004U)
#define SYSCON_DIV_CLK_GATE (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR)
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 1
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 0
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH 1
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)
#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE 0U

4
driver/system.c
View File

@ -27,7 +27,9 @@ void SYSTEM_DelayMs(uint32_t Delay)
void SYSTEM_ConfigureClocks(void)
{
// Set source clock from external crystal
PMU_SRC_CFG = (PMU_SRC_CFG & ~PMU_SRC_CFG_RTC_CLK_SEL_MASK) | PMU_SRC_CFG_RTC_CLK_SEL_BITS_XTAL;
PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_XTAH_EN_MASK | PMU_SRC_CFG_RCHF_EN_MASK))
| PMU_SRC_CFG_XTAH_EN_BITS_DISABLE
| PMU_SRC_CFG_RCHF_EN_BITS_ENABLE;
// Divide by 2
SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_BITS_2;

10
hardware/dp32g030/pmu.def
View File

@ -17,9 +17,13 @@
@ = 0x40000800, 0x800
SRC_CFG = 0x0010
> RTC_CLK_SEL, 4, 1
= RCLF, 0
= XTAL, 1
> XTAH_EN, 2, 1
= DISABLE, 0
= ENABLE, 1
> RCHF_EN, 0, 1
= DISABLE, 0
= ENABLE, 1
TRIM_POW0 = 0x0020
TRIM_POW1 = 0x0024

2
hardware/dp32g030/syscon.def
View File

@ -58,7 +58,7 @@ CLK_SEL = 0x0000
= XTAH, 1
DIV_CLK_GATE = 0x0004
> DIV_CLK_GATE, 1, 1
> DIV_CLK_GATE, 0, 1
= DISABLE, 0
= ENABLE, 1