diff --git a/board.c b/board.c index 639b6a1..38fcdf4 100644 --- a/board.c +++ b/board.c @@ -38,10 +38,10 @@ void BOARD_FLASH_Init(void) void BOARD_GPIO_Init(void) { GPIOA->DIR |= 0 - | GPIO_DIR_10_OUTPUT - | GPIO_DIR_11_OUTPUT - | GPIO_DIR_12_OUTPUT - | GPIO_DIR_13_OUTPUT + | GPIO_DIR_10_BITS_OUTPUT + | GPIO_DIR_11_BITS_OUTPUT + | GPIO_DIR_12_BITS_OUTPUT + | GPIO_DIR_13_BITS_OUTPUT ; GPIOA->DIR &= ~(0 | GPIO_DIR_3_MASK @@ -50,17 +50,17 @@ void BOARD_GPIO_Init(void) | GPIO_DIR_6_MASK ); GPIOB->DIR |= 0 - | GPIO_DIR_6_OUTPUT - | GPIO_DIR_9_OUTPUT - | GPIO_DIR_11_OUTPUT - | GPIO_DIR_15_OUTPUT + | GPIO_DIR_6_BITS_OUTPUT + | GPIO_DIR_9_BITS_OUTPUT + | GPIO_DIR_11_BITS_OUTPUT + | GPIO_DIR_15_BITS_OUTPUT ; GPIOC->DIR |= 0 - | GPIO_DIR_0_OUTPUT - | GPIO_DIR_1_OUTPUT - | GPIO_DIR_2_OUTPUT - | GPIO_DIR_3_OUTPUT - | GPIO_DIR_4_OUTPUT + | GPIO_DIR_0_BITS_OUTPUT + | GPIO_DIR_1_BITS_OUTPUT + | GPIO_DIR_2_BITS_OUTPUT + | GPIO_DIR_3_BITS_OUTPUT + | GPIO_DIR_4_BITS_OUTPUT ; GPIOC->DIR &= ~(0 | GPIO_DIR_5_MASK @@ -82,10 +82,10 @@ void BOARD_PORTCON_Init(void) | PORTCON_PORTA_SEL0_A7_MASK ; PORTCON_PORTA_SEL0 |= 0 - | PORTCON_PORTA_SEL0_A0_GPIOA0 - | PORTCON_PORTA_SEL0_A1_GPIOA1 - | PORTCON_PORTA_SEL0_A2_GPIOA2 - | PORTCON_PORTA_SEL0_A7_UART1_TX + | PORTCON_PORTA_SEL0_A0_BITS_GPIOA0 + | PORTCON_PORTA_SEL0_A1_BITS_GPIOA1 + | PORTCON_PORTA_SEL0_A2_BITS_GPIOA2 + | PORTCON_PORTA_SEL0_A7_BITS_UART1_TX ; PORTCON_PORTA_SEL1 &= 0 @@ -95,10 +95,10 @@ void BOARD_PORTCON_Init(void) | PORTCON_PORTA_SEL1_A15_MASK ; PORTCON_PORTA_SEL1 |= 0 - | PORTCON_PORTA_SEL1_A8_UART1_RX - | PORTCON_PORTA_SEL1_A9_SARADC_CH4 - | PORTCON_PORTA_SEL1_A14_SARADC_CH9 - | PORTCON_PORTA_SEL1_A15_GPIOA15 + | PORTCON_PORTA_SEL1_A8_BITS_UART1_RX + | PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4 + | PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9 + | PORTCON_PORTA_SEL1_A15_BITS_GPIOA15 ; // PORT B pin selection @@ -112,13 +112,13 @@ void BOARD_PORTCON_Init(void) | PORTCON_PORTB_SEL0_B5_MASK ; PORTCON_PORTB_SEL0 |= 0 - | PORTCON_PORTB_SEL0_B0_GPIOB0 - | PORTCON_PORTB_SEL0_B1_GPIOB1 - | PORTCON_PORTB_SEL0_B2_GPIOB2 - | PORTCON_PORTB_SEL0_B3_GPIOB3 - | PORTCON_PORTB_SEL0_B4_GPIOB4 - | PORTCON_PORTB_SEL0_B5_GPIOB5 - | PORTCON_PORTB_SEL0_B7_SPI0_SSN + | PORTCON_PORTB_SEL0_B0_BITS_GPIOB0 + | PORTCON_PORTB_SEL0_B1_BITS_GPIOB1 + | PORTCON_PORTB_SEL0_B2_BITS_GPIOB2 + | PORTCON_PORTB_SEL0_B3_BITS_GPIOB3 + | PORTCON_PORTB_SEL0_B4_BITS_GPIOB4 + | PORTCON_PORTB_SEL0_B5_BITS_GPIOB5 + | PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN ; PORTCON_PORTB_SEL1 &= 0 @@ -128,12 +128,12 @@ void BOARD_PORTCON_Init(void) | PORTCON_PORTB_SEL1_B13_MASK ; PORTCON_PORTB_SEL1 |= 0 - | PORTCON_PORTB_SEL1_B8_SPI0_CLK - | PORTCON_PORTB_SEL1_B10_SPI0_MOSI - | PORTCON_PORTB_SEL1_B11_SWDIO - | PORTCON_PORTB_SEL1_B12_GPIOB12 - | PORTCON_PORTB_SEL1_B13_GPIOB13 - | PORTCON_PORTB_SEL1_B14_SWCLK + | PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK + | PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI + | PORTCON_PORTB_SEL1_B11_BITS_SWDIO + | PORTCON_PORTB_SEL1_B12_BITS_GPIOB12 + | PORTCON_PORTB_SEL1_B13_BITS_GPIOB13 + | PORTCON_PORTB_SEL1_B14_BITS_SWCLK ; // PORT C pin selection @@ -146,11 +146,11 @@ void BOARD_PORTCON_Init(void) // PORT A pin configuration PORTCON_PORTA_IE |= 0 - | PORTCON_PORTA_IE_A3_ENABLE - | PORTCON_PORTA_IE_A4_ENABLE - | PORTCON_PORTA_IE_A5_ENABLE - | PORTCON_PORTA_IE_A6_ENABLE - | PORTCON_PORTA_IE_A8_ENABLE + | PORTCON_PORTA_IE_A3_BITS_ENABLE + | PORTCON_PORTA_IE_A4_BITS_ENABLE + | PORTCON_PORTA_IE_A5_BITS_ENABLE + | PORTCON_PORTA_IE_A6_BITS_ENABLE + | PORTCON_PORTA_IE_A8_BITS_ENABLE ; PORTCON_PORTA_IE &= ~(0 | PORTCON_PORTA_IE_A10_MASK @@ -160,10 +160,10 @@ void BOARD_PORTCON_Init(void) ); PORTCON_PORTA_PU |= 0 - | PORTCON_PORTA_PU_A3_ENABLE - | PORTCON_PORTA_PU_A4_ENABLE - | PORTCON_PORTA_PU_A5_ENABLE - | PORTCON_PORTA_PU_A6_ENABLE + | PORTCON_PORTA_PU_A3_BITS_ENABLE + | PORTCON_PORTA_PU_A4_BITS_ENABLE + | PORTCON_PORTA_PU_A5_BITS_ENABLE + | PORTCON_PORTA_PU_A6_BITS_ENABLE ; PORTCON_PORTA_PU &= ~(0 | PORTCON_PORTA_PU_A10_MASK @@ -184,10 +184,10 @@ void BOARD_PORTCON_Init(void) ); PORTCON_PORTA_OD |= 0 - | PORTCON_PORTA_OD_A3_ENABLE - | PORTCON_PORTA_OD_A4_ENABLE - | PORTCON_PORTA_OD_A5_ENABLE - | PORTCON_PORTA_OD_A6_ENABLE + | PORTCON_PORTA_OD_A3_BITS_ENABLE + | PORTCON_PORTA_OD_A4_BITS_ENABLE + | PORTCON_PORTA_OD_A5_BITS_ENABLE + | PORTCON_PORTA_OD_A6_BITS_ENABLE ; PORTCON_PORTA_OD &= ~(0 | PORTCON_PORTA_OD_A10_MASK @@ -199,7 +199,7 @@ void BOARD_PORTCON_Init(void) // PORT B pin configuration PORTCON_PORTB_IE |= 0 - | PORTCON_PORTB_IE_B14_ENABLE + | PORTCON_PORTB_IE_B14_BITS_ENABLE ; PORTCON_PORTB_IE &= ~(0 | PORTCON_PORTB_IE_B6_MASK @@ -234,13 +234,13 @@ void BOARD_PORTCON_Init(void) ); PORTCON_PORTB_OD |= 0 - | PORTCON_PORTB_OD_B14_ENABLE + | PORTCON_PORTB_OD_B14_BITS_ENABLE ; // PORT C pin configuration PORTCON_PORTC_IE |= 0 - | PORTCON_PORTC_IE_C5_ENABLE + | PORTCON_PORTC_IE_C5_BITS_ENABLE ; PORTCON_PORTC_IE &= ~(0 | PORTCON_PORTC_IE_C0_MASK @@ -251,7 +251,7 @@ void BOARD_PORTCON_Init(void) ); PORTCON_PORTC_PU |= 0 - | PORTCON_PORTC_PU_C5_ENABLE + | PORTCON_PORTC_PU_C5_BITS_ENABLE ; PORTCON_PORTC_PU &= ~(0 | PORTCON_PORTC_PU_C0_MASK @@ -278,7 +278,7 @@ void BOARD_PORTCON_Init(void) | PORTCON_PORTC_OD_C4_MASK ); PORTCON_PORTC_OD |= 0 - | PORTCON_PORTC_OD_C5_ENABLE + | PORTCON_PORTC_OD_C5_BITS_ENABLE ; } diff --git a/bsp/dp32g030/crc.h b/bsp/dp32g030/crc.h index 1cc4c53..83c9a7a 100644 --- a/bsp/dp32g030/crc.h +++ b/bsp/dp32g030/crc.h @@ -22,66 +22,87 @@ #endif /* -------- CRC -------- */ -#define CRC_BASE_ADDR 0x40003000U -#define CRC_BASE_SIZE 0x00000800U +#define CRC_BASE_ADDR 0x40003000U +#define CRC_BASE_SIZE 0x00000800U -#define CRC_CR_ADDR (CRC_BASE_ADDR + 0x0000U) -#define CRC_CR (*(volatile uint32_t *)CRC_CR_ADDR) -#define CRC_CR_CRC_EN_SHIFT 0 -#define CRC_CR_CRC_EN_WIDTH 1 -#define CRC_CR_CRC_EN_MASK (((1U << CRC_CR_CRC_EN_WIDTH) - 1U) << CRC_CR_CRC_EN_SHIFT) -#define CRC_CR_CRC_EN_DISABLE (0U << CRC_CR_CRC_EN_SHIFT) -#define CRC_CR_CRC_EN_ENABLE (1U << CRC_CR_CRC_EN_SHIFT) +#define CRC_CR_ADDR (CRC_BASE_ADDR + 0x0000U) +#define CRC_CR (*(volatile uint32_t *)CRC_CR_ADDR) +#define CRC_CR_CRC_EN_SHIFT 0 +#define CRC_CR_CRC_EN_WIDTH 1 +#define CRC_CR_CRC_EN_MASK (((1U << CRC_CR_CRC_EN_WIDTH) - 1U) << CRC_CR_CRC_EN_SHIFT) +#define CRC_CR_CRC_EN_VALUE_DISABLE 0U +#define CRC_CR_CRC_EN_BITS_DISABLE (CRC_CR_CRC_EN_VALUE_DISABLE << CRC_CR_CRC_EN_SHIFT) +#define CRC_CR_CRC_EN_VALUE_ENABLE 1U +#define CRC_CR_CRC_EN_BITS_ENABLE (CRC_CR_CRC_EN_VALUE_ENABLE << CRC_CR_CRC_EN_SHIFT) -#define CRC_CR_INPUT_REV_SHIFT 1 -#define CRC_CR_INPUT_REV_WIDTH 1 -#define CRC_CR_INPUT_REV_MASK (((1U << CRC_CR_INPUT_REV_WIDTH) - 1U) << CRC_CR_INPUT_REV_SHIFT) -#define CRC_CR_INPUT_REV_NORMAL (0U << CRC_CR_INPUT_REV_SHIFT) -#define CRC_CR_INPUT_REV_REVERSED (1U << CRC_CR_INPUT_REV_SHIFT) +#define CRC_CR_INPUT_REV_SHIFT 1 +#define CRC_CR_INPUT_REV_WIDTH 1 +#define CRC_CR_INPUT_REV_MASK (((1U << CRC_CR_INPUT_REV_WIDTH) - 1U) << CRC_CR_INPUT_REV_SHIFT) +#define CRC_CR_INPUT_REV_VALUE_NORMAL 0U +#define CRC_CR_INPUT_REV_BITS_NORMAL (CRC_CR_INPUT_REV_VALUE_NORMAL << CRC_CR_INPUT_REV_SHIFT) +#define CRC_CR_INPUT_REV_VALUE_REVERSED 1U +#define CRC_CR_INPUT_REV_BITS_REVERSED (CRC_CR_INPUT_REV_VALUE_REVERSED << CRC_CR_INPUT_REV_SHIFT) -#define CRC_CR_INPUT_INV_SHIFT 2 -#define CRC_CR_INPUT_INV_WIDTH 2 -#define CRC_CR_INPUT_INV_MASK (((1U << CRC_CR_INPUT_INV_WIDTH) - 1U) << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_NORMAL (0U << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_BIT_INVERTED (1U << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_BYTE_INVERTED (2U << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_BIT_BYTE_INVERTED (3U << CRC_CR_INPUT_INV_SHIFT) +#define CRC_CR_INPUT_INV_SHIFT 2 +#define CRC_CR_INPUT_INV_WIDTH 2 +#define CRC_CR_INPUT_INV_MASK (((1U << CRC_CR_INPUT_INV_WIDTH) - 1U) << CRC_CR_INPUT_INV_SHIFT) +#define CRC_CR_INPUT_INV_VALUE_NORMAL 0U +#define CRC_CR_INPUT_INV_BITS_NORMAL (CRC_CR_INPUT_INV_VALUE_NORMAL << CRC_CR_INPUT_INV_SHIFT) +#define CRC_CR_INPUT_INV_VALUE_BIT_INVERTED 1U +#define CRC_CR_INPUT_INV_BITS_BIT_INVERTED (CRC_CR_INPUT_INV_VALUE_BIT_INVERTED << CRC_CR_INPUT_INV_SHIFT) +#define CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED 2U +#define CRC_CR_INPUT_INV_BITS_BYTE_INVERTED (CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT) +#define CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED 3U +#define CRC_CR_INPUT_INV_BITS_BIT_BYTE_INVERTED (CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_REV_SHIFT 4 -#define CRC_CR_OUTPUT_REV_WIDTH 1 -#define CRC_CR_OUTPUT_REV_MASK (((1U << CRC_CR_OUTPUT_REV_WIDTH) - 1U) << CRC_CR_OUTPUT_REV_SHIFT) -#define CRC_CR_OUTPUT_REV_NORMAL (0U << CRC_CR_OUTPUT_REV_SHIFT) -#define CRC_CR_OUTPUT_REV_REVERSED (1U << CRC_CR_OUTPUT_REV_SHIFT) +#define CRC_CR_OUTPUT_REV_SHIFT 4 +#define CRC_CR_OUTPUT_REV_WIDTH 1 +#define CRC_CR_OUTPUT_REV_MASK (((1U << CRC_CR_OUTPUT_REV_WIDTH) - 1U) << CRC_CR_OUTPUT_REV_SHIFT) +#define CRC_CR_OUTPUT_REV_VALUE_NORMAL 0U +#define CRC_CR_OUTPUT_REV_BITS_NORMAL (CRC_CR_OUTPUT_REV_VALUE_NORMAL << CRC_CR_OUTPUT_REV_SHIFT) +#define CRC_CR_OUTPUT_REV_VALUE_REVERSED 1U +#define CRC_CR_OUTPUT_REV_BITS_REVERSED (CRC_CR_OUTPUT_REV_VALUE_REVERSED << CRC_CR_OUTPUT_REV_SHIFT) -#define CRC_CR_OUTPUT_INV_SHIFT 5 -#define CRC_CR_OUTPUT_INV_WIDTH 2 -#define CRC_CR_OUTPUT_INV_MASK (((1U << CRC_CR_OUTPUT_INV_WIDTH) - 1U) << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_NORMAL (0U << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_BIT_INVERTED (1U << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_BYTE_INVERTED (2U << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_BIT_BYTE_INVERTED (3U << CRC_CR_OUTPUT_INV_SHIFT) +#define CRC_CR_OUTPUT_INV_SHIFT 5 +#define CRC_CR_OUTPUT_INV_WIDTH 2 +#define CRC_CR_OUTPUT_INV_MASK (((1U << CRC_CR_OUTPUT_INV_WIDTH) - 1U) << CRC_CR_OUTPUT_INV_SHIFT) +#define CRC_CR_OUTPUT_INV_VALUE_NORMAL 0U +#define CRC_CR_OUTPUT_INV_BITS_NORMAL (CRC_CR_OUTPUT_INV_VALUE_NORMAL << CRC_CR_OUTPUT_INV_SHIFT) +#define CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED 1U +#define CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) +#define CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED 2U +#define CRC_CR_OUTPUT_INV_BITS_BYTE_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) +#define CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED 3U +#define CRC_CR_OUTPUT_INV_BITS_BIT_BYTE_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_DATA_WIDTH_SHIFT 7 -#define CRC_CR_DATA_WIDTH_WIDTH 2 -#define CRC_CR_DATA_WIDTH_MASK (((1U << CRC_CR_DATA_WIDTH_WIDTH) - 1U) << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_DATA_WIDTH_32 (0U << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_DATA_WIDTH_16 (1U << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_DATA_WIDTH_8 (2U << CRC_CR_DATA_WIDTH_SHIFT) +#define CRC_CR_DATA_WIDTH_SHIFT 7 +#define CRC_CR_DATA_WIDTH_WIDTH 2 +#define CRC_CR_DATA_WIDTH_MASK (((1U << CRC_CR_DATA_WIDTH_WIDTH) - 1U) << CRC_CR_DATA_WIDTH_SHIFT) +#define CRC_CR_DATA_WIDTH_VALUE_32 0U +#define CRC_CR_DATA_WIDTH_BITS_32 (CRC_CR_DATA_WIDTH_VALUE_32 << CRC_CR_DATA_WIDTH_SHIFT) +#define CRC_CR_DATA_WIDTH_VALUE_16 1U +#define CRC_CR_DATA_WIDTH_BITS_16 (CRC_CR_DATA_WIDTH_VALUE_16 << CRC_CR_DATA_WIDTH_SHIFT) +#define CRC_CR_DATA_WIDTH_VALUE_8 2U +#define CRC_CR_DATA_WIDTH_BITS_8 (CRC_CR_DATA_WIDTH_VALUE_8 << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_CRC_SEL_SHIFT 9 -#define CRC_CR_CRC_SEL_WIDTH 2 -#define CRC_CR_CRC_SEL_MASK (((1U << CRC_CR_CRC_SEL_WIDTH) - 1U) << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_CRC_16_CCITT (0U << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_CRC_8_ATM (1U << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_CRC_16 (2U << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_CRC_32_IEEE802_3 (3U << CRC_CR_CRC_SEL_SHIFT) +#define CRC_CR_CRC_SEL_SHIFT 9 +#define CRC_CR_CRC_SEL_WIDTH 2 +#define CRC_CR_CRC_SEL_MASK (((1U << CRC_CR_CRC_SEL_WIDTH) - 1U) << CRC_CR_CRC_SEL_SHIFT) +#define CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT 0U +#define CRC_CR_CRC_SEL_BITS_CRC_16_CCITT (CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT << CRC_CR_CRC_SEL_SHIFT) +#define CRC_CR_CRC_SEL_VALUE_CRC_8_ATM 1U +#define CRC_CR_CRC_SEL_BITS_CRC_8_ATM (CRC_CR_CRC_SEL_VALUE_CRC_8_ATM << CRC_CR_CRC_SEL_SHIFT) +#define CRC_CR_CRC_SEL_VALUE_CRC_16 2U +#define CRC_CR_CRC_SEL_BITS_CRC_16 (CRC_CR_CRC_SEL_VALUE_CRC_16 << CRC_CR_CRC_SEL_SHIFT) +#define CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 3U +#define CRC_CR_CRC_SEL_BITS_CRC_32_IEEE802_3 (CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 << CRC_CR_CRC_SEL_SHIFT) -#define CRC_IV_ADDR (CRC_BASE_ADDR + 0x0004U) -#define CRC_IV (*(volatile uint32_t *)CRC_IV_ADDR) -#define CRC_DATAIN_ADDR (CRC_BASE_ADDR + 0x0008U) -#define CRC_DATAIN (*(volatile uint32_t *)CRC_DATAIN_ADDR) -#define CRC_DATAOUT_ADDR (CRC_BASE_ADDR + 0x000CU) -#define CRC_DATAOUT (*(volatile uint32_t *)CRC_DATAOUT_ADDR) +#define CRC_IV_ADDR (CRC_BASE_ADDR + 0x0004U) +#define CRC_IV (*(volatile uint32_t *)CRC_IV_ADDR) +#define CRC_DATAIN_ADDR (CRC_BASE_ADDR + 0x0008U) +#define CRC_DATAIN (*(volatile uint32_t *)CRC_DATAIN_ADDR) +#define CRC_DATAOUT_ADDR (CRC_BASE_ADDR + 0x000CU) +#define CRC_DATAOUT (*(volatile uint32_t *)CRC_DATAOUT_ADDR) #endif diff --git a/bsp/dp32g030/dma.h b/bsp/dp32g030/dma.h index a093aa2..4ec67b6 100644 --- a/bsp/dp32g030/dma.h +++ b/bsp/dp32g030/dma.h @@ -22,136 +22,170 @@ #endif /* -------- DMA -------- */ -#define DMA_BASE_ADDR 0x40001000U -#define DMA_BASE_SIZE 0x00000100U +#define DMA_BASE_ADDR 0x40001000U +#define DMA_BASE_SIZE 0x00000100U -#define DMA_CTR_ADDR (DMA_BASE_ADDR + 0x0000U) -#define DMA_CTR (*(volatile uint32_t *)DMA_CTR_ADDR) -#define DMA_CTR_DMAEN_SHIFT 0 -#define DMA_CTR_DMAEN_WIDTH 1 -#define DMA_CTR_DMAEN_MASK (((1U << DMA_CTR_DMAEN_WIDTH) - 1U) << DMA_CTR_DMAEN_SHIFT) -#define DMA_CTR_DMAEN_DISABLE (0U << DMA_CTR_DMAEN_SHIFT) -#define DMA_CTR_DMAEN_ENABLE (1U << DMA_CTR_DMAEN_SHIFT) +#define DMA_CTR_ADDR (DMA_BASE_ADDR + 0x0000U) +#define DMA_CTR (*(volatile uint32_t *)DMA_CTR_ADDR) +#define DMA_CTR_DMAEN_SHIFT 0 +#define DMA_CTR_DMAEN_WIDTH 1 +#define DMA_CTR_DMAEN_MASK (((1U << DMA_CTR_DMAEN_WIDTH) - 1U) << DMA_CTR_DMAEN_SHIFT) +#define DMA_CTR_DMAEN_VALUE_DISABLE 0U +#define DMA_CTR_DMAEN_BITS_DISABLE (DMA_CTR_DMAEN_VALUE_DISABLE << DMA_CTR_DMAEN_SHIFT) +#define DMA_CTR_DMAEN_VALUE_ENABLE 1U +#define DMA_CTR_DMAEN_BITS_ENABLE (DMA_CTR_DMAEN_VALUE_ENABLE << DMA_CTR_DMAEN_SHIFT) -#define DMA_INTEN_ADDR (DMA_BASE_ADDR + 0x0004U) -#define DMA_INTEN (*(volatile uint32_t *)DMA_INTEN_ADDR) -#define DMA_INTEN_CH0_TC_INTEN_SHIFT 0 -#define DMA_INTEN_CH0_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH0_TC_INTEN_MASK (((1U << DMA_INTEN_CH0_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_TC_INTEN_SHIFT) -#define DMA_INTEN_CH0_TC_INTEN_DISABLE (0U << DMA_INTEN_CH0_TC_INTEN_SHIFT) -#define DMA_INTEN_CH0_TC_INTEN_ENABLE (1U << DMA_INTEN_CH0_TC_INTEN_SHIFT) +#define DMA_INTEN_ADDR (DMA_BASE_ADDR + 0x0004U) +#define DMA_INTEN (*(volatile uint32_t *)DMA_INTEN_ADDR) +#define DMA_INTEN_CH0_TC_INTEN_SHIFT 0 +#define DMA_INTEN_CH0_TC_INTEN_WIDTH 1 +#define DMA_INTEN_CH0_TC_INTEN_MASK (((1U << DMA_INTEN_CH0_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_TC_INTEN_SHIFT) +#define DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH0_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT) +#define DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH0_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT) -#define DMA_INTEN_CH1_TC_INTEN_SHIFT 1 -#define DMA_INTEN_CH1_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH1_TC_INTEN_MASK (((1U << DMA_INTEN_CH1_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_TC_INTEN_SHIFT) -#define DMA_INTEN_CH1_TC_INTEN_DISABLE (0U << DMA_INTEN_CH1_TC_INTEN_SHIFT) -#define DMA_INTEN_CH1_TC_INTEN_ENABLE (1U << DMA_INTEN_CH1_TC_INTEN_SHIFT) +#define DMA_INTEN_CH1_TC_INTEN_SHIFT 1 +#define DMA_INTEN_CH1_TC_INTEN_WIDTH 1 +#define DMA_INTEN_CH1_TC_INTEN_MASK (((1U << DMA_INTEN_CH1_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_TC_INTEN_SHIFT) +#define DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH1_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT) +#define DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH1_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT) -#define DMA_INTEN_CH2_TC_INTEN_SHIFT 2 -#define DMA_INTEN_CH2_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH2_TC_INTEN_MASK (((1U << DMA_INTEN_CH2_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_TC_INTEN_SHIFT) -#define DMA_INTEN_CH2_TC_INTEN_DISABLE (0U << DMA_INTEN_CH2_TC_INTEN_SHIFT) -#define DMA_INTEN_CH2_TC_INTEN_ENABLE (1U << DMA_INTEN_CH2_TC_INTEN_SHIFT) +#define DMA_INTEN_CH2_TC_INTEN_SHIFT 2 +#define DMA_INTEN_CH2_TC_INTEN_WIDTH 1 +#define DMA_INTEN_CH2_TC_INTEN_MASK (((1U << DMA_INTEN_CH2_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_TC_INTEN_SHIFT) +#define DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH2_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT) +#define DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH2_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT) -#define DMA_INTEN_CH3_TC_INTEN_SHIFT 3 -#define DMA_INTEN_CH3_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH3_TC_INTEN_MASK (((1U << DMA_INTEN_CH3_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_TC_INTEN_SHIFT) -#define DMA_INTEN_CH3_TC_INTEN_DISABLE (0U << DMA_INTEN_CH3_TC_INTEN_SHIFT) -#define DMA_INTEN_CH3_TC_INTEN_ENABLE (1U << DMA_INTEN_CH3_TC_INTEN_SHIFT) +#define DMA_INTEN_CH3_TC_INTEN_SHIFT 3 +#define DMA_INTEN_CH3_TC_INTEN_WIDTH 1 +#define DMA_INTEN_CH3_TC_INTEN_MASK (((1U << DMA_INTEN_CH3_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_TC_INTEN_SHIFT) +#define DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH3_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT) +#define DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH3_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT) -#define DMA_INTEN_CH0_THC_INTEN_SHIFT 8 -#define DMA_INTEN_CH0_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH0_THC_INTEN_MASK (((1U << DMA_INTEN_CH0_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_THC_INTEN_SHIFT) -#define DMA_INTEN_CH0_THC_INTEN_DISABLE (0U << DMA_INTEN_CH0_THC_INTEN_SHIFT) -#define DMA_INTEN_CH0_THC_INTEN_ENABLE (1U << DMA_INTEN_CH0_THC_INTEN_SHIFT) +#define DMA_INTEN_CH0_THC_INTEN_SHIFT 8 +#define DMA_INTEN_CH0_THC_INTEN_WIDTH 1 +#define DMA_INTEN_CH0_THC_INTEN_MASK (((1U << DMA_INTEN_CH0_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_THC_INTEN_SHIFT) +#define DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH0_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT) +#define DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH0_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT) -#define DMA_INTEN_CH1_THC_INTEN_SHIFT 9 -#define DMA_INTEN_CH1_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH1_THC_INTEN_MASK (((1U << DMA_INTEN_CH1_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_THC_INTEN_SHIFT) -#define DMA_INTEN_CH1_THC_INTEN_DISABLE (0U << DMA_INTEN_CH1_THC_INTEN_SHIFT) -#define DMA_INTEN_CH1_THC_INTEN_ENABLE (1U << DMA_INTEN_CH1_THC_INTEN_SHIFT) +#define DMA_INTEN_CH1_THC_INTEN_SHIFT 9 +#define DMA_INTEN_CH1_THC_INTEN_WIDTH 1 +#define DMA_INTEN_CH1_THC_INTEN_MASK (((1U << DMA_INTEN_CH1_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_THC_INTEN_SHIFT) +#define DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH1_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT) +#define DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH1_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT) -#define DMA_INTEN_CH2_THC_INTEN_SHIFT 10 -#define DMA_INTEN_CH2_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH2_THC_INTEN_MASK (((1U << DMA_INTEN_CH2_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_THC_INTEN_SHIFT) -#define DMA_INTEN_CH2_THC_INTEN_DISABLE (0U << DMA_INTEN_CH2_THC_INTEN_SHIFT) -#define DMA_INTEN_CH2_THC_INTEN_ENABLE (1U << DMA_INTEN_CH2_THC_INTEN_SHIFT) +#define DMA_INTEN_CH2_THC_INTEN_SHIFT 10 +#define DMA_INTEN_CH2_THC_INTEN_WIDTH 1 +#define DMA_INTEN_CH2_THC_INTEN_MASK (((1U << DMA_INTEN_CH2_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_THC_INTEN_SHIFT) +#define DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH2_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT) +#define DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH2_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT) -#define DMA_INTEN_CH3_THC_INTEN_SHIFT 11 -#define DMA_INTEN_CH3_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH3_THC_INTEN_MASK (((1U << DMA_INTEN_CH3_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_THC_INTEN_SHIFT) -#define DMA_INTEN_CH3_THC_INTEN_DISABLE (0U << DMA_INTEN_CH3_THC_INTEN_SHIFT) -#define DMA_INTEN_CH3_THC_INTEN_ENABLE (1U << DMA_INTEN_CH3_THC_INTEN_SHIFT) +#define DMA_INTEN_CH3_THC_INTEN_SHIFT 11 +#define DMA_INTEN_CH3_THC_INTEN_WIDTH 1 +#define DMA_INTEN_CH3_THC_INTEN_MASK (((1U << DMA_INTEN_CH3_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_THC_INTEN_SHIFT) +#define DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE 0U +#define DMA_INTEN_CH3_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT) +#define DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE 1U +#define DMA_INTEN_CH3_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT) -#define DMA_INTST_ADDR (DMA_BASE_ADDR + 0x0008U) -#define DMA_INTST (*(volatile uint32_t *)DMA_INTST_ADDR) -#define DMA_INTST_CH0_TC_INTST_SHIFT 0 -#define DMA_INTST_CH0_TC_INTST_WIDTH 1 -#define DMA_INTST_CH0_TC_INTST_MASK (((1U << DMA_INTST_CH0_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_TC_INTST_SHIFT) -#define DMA_INTST_CH0_TC_INTST_NOT_SET (0U << DMA_INTST_CH0_TC_INTST_SHIFT) -#define DMA_INTST_CH0_TC_INTST_SET (1U << DMA_INTST_CH0_TC_INTST_SHIFT) +#define DMA_INTST_ADDR (DMA_BASE_ADDR + 0x0008U) +#define DMA_INTST (*(volatile uint32_t *)DMA_INTST_ADDR) +#define DMA_INTST_CH0_TC_INTST_SHIFT 0 +#define DMA_INTST_CH0_TC_INTST_WIDTH 1 +#define DMA_INTST_CH0_TC_INTST_MASK (((1U << DMA_INTST_CH0_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_TC_INTST_SHIFT) +#define DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH0_TC_INTST_BITS_NOT_SET (DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_TC_INTST_SHIFT) +#define DMA_INTST_CH0_TC_INTST_VALUE_SET 1U +#define DMA_INTST_CH0_TC_INTST_BITS_SET (DMA_INTST_CH0_TC_INTST_VALUE_SET << DMA_INTST_CH0_TC_INTST_SHIFT) -#define DMA_INTST_CH1_TC_INTST_SHIFT 1 -#define DMA_INTST_CH1_TC_INTST_WIDTH 1 -#define DMA_INTST_CH1_TC_INTST_MASK (((1U << DMA_INTST_CH1_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_TC_INTST_SHIFT) -#define DMA_INTST_CH1_TC_INTST_NOT_SET (0U << DMA_INTST_CH1_TC_INTST_SHIFT) -#define DMA_INTST_CH1_TC_INTST_SET (1U << DMA_INTST_CH1_TC_INTST_SHIFT) +#define DMA_INTST_CH1_TC_INTST_SHIFT 1 +#define DMA_INTST_CH1_TC_INTST_WIDTH 1 +#define DMA_INTST_CH1_TC_INTST_MASK (((1U << DMA_INTST_CH1_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_TC_INTST_SHIFT) +#define DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH1_TC_INTST_BITS_NOT_SET (DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_TC_INTST_SHIFT) +#define DMA_INTST_CH1_TC_INTST_VALUE_SET 1U +#define DMA_INTST_CH1_TC_INTST_BITS_SET (DMA_INTST_CH1_TC_INTST_VALUE_SET << DMA_INTST_CH1_TC_INTST_SHIFT) -#define DMA_INTST_CH2_TC_INTST_SHIFT 2 -#define DMA_INTST_CH2_TC_INTST_WIDTH 1 -#define DMA_INTST_CH2_TC_INTST_MASK (((1U << DMA_INTST_CH2_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_TC_INTST_SHIFT) -#define DMA_INTST_CH2_TC_INTST_NOT_SET (0U << DMA_INTST_CH2_TC_INTST_SHIFT) -#define DMA_INTST_CH2_TC_INTST_SET (1U << DMA_INTST_CH2_TC_INTST_SHIFT) +#define DMA_INTST_CH2_TC_INTST_SHIFT 2 +#define DMA_INTST_CH2_TC_INTST_WIDTH 1 +#define DMA_INTST_CH2_TC_INTST_MASK (((1U << DMA_INTST_CH2_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_TC_INTST_SHIFT) +#define DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH2_TC_INTST_BITS_NOT_SET (DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_TC_INTST_SHIFT) +#define DMA_INTST_CH2_TC_INTST_VALUE_SET 1U +#define DMA_INTST_CH2_TC_INTST_BITS_SET (DMA_INTST_CH2_TC_INTST_VALUE_SET << DMA_INTST_CH2_TC_INTST_SHIFT) -#define DMA_INTST_CH3_TC_INTST_SHIFT 3 -#define DMA_INTST_CH3_TC_INTST_WIDTH 1 -#define DMA_INTST_CH3_TC_INTST_MASK (((1U << DMA_INTST_CH3_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_TC_INTST_SHIFT) -#define DMA_INTST_CH3_TC_INTST_NOT_SET (0U << DMA_INTST_CH3_TC_INTST_SHIFT) -#define DMA_INTST_CH3_TC_INTST_SET (1U << DMA_INTST_CH3_TC_INTST_SHIFT) +#define DMA_INTST_CH3_TC_INTST_SHIFT 3 +#define DMA_INTST_CH3_TC_INTST_WIDTH 1 +#define DMA_INTST_CH3_TC_INTST_MASK (((1U << DMA_INTST_CH3_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_TC_INTST_SHIFT) +#define DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH3_TC_INTST_BITS_NOT_SET (DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_TC_INTST_SHIFT) +#define DMA_INTST_CH3_TC_INTST_VALUE_SET 1U +#define DMA_INTST_CH3_TC_INTST_BITS_SET (DMA_INTST_CH3_TC_INTST_VALUE_SET << DMA_INTST_CH3_TC_INTST_SHIFT) -#define DMA_INTST_CH0_THC_INTST_SHIFT 8 -#define DMA_INTST_CH0_THC_INTST_WIDTH 1 -#define DMA_INTST_CH0_THC_INTST_MASK (((1U << DMA_INTST_CH0_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_THC_INTST_SHIFT) -#define DMA_INTST_CH0_THC_INTST_NOT_SET (0U << DMA_INTST_CH0_THC_INTST_SHIFT) -#define DMA_INTST_CH0_THC_INTST_SET (1U << DMA_INTST_CH0_THC_INTST_SHIFT) +#define DMA_INTST_CH0_THC_INTST_SHIFT 8 +#define DMA_INTST_CH0_THC_INTST_WIDTH 1 +#define DMA_INTST_CH0_THC_INTST_MASK (((1U << DMA_INTST_CH0_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_THC_INTST_SHIFT) +#define DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH0_THC_INTST_BITS_NOT_SET (DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_THC_INTST_SHIFT) +#define DMA_INTST_CH0_THC_INTST_VALUE_SET 1U +#define DMA_INTST_CH0_THC_INTST_BITS_SET (DMA_INTST_CH0_THC_INTST_VALUE_SET << DMA_INTST_CH0_THC_INTST_SHIFT) -#define DMA_INTST_CH1_THC_INTST_SHIFT 9 -#define DMA_INTST_CH1_THC_INTST_WIDTH 1 -#define DMA_INTST_CH1_THC_INTST_MASK (((1U << DMA_INTST_CH1_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_THC_INTST_SHIFT) -#define DMA_INTST_CH1_THC_INTST_NOT_SET (0U << DMA_INTST_CH1_THC_INTST_SHIFT) -#define DMA_INTST_CH1_THC_INTST_SET (1U << DMA_INTST_CH1_THC_INTST_SHIFT) +#define DMA_INTST_CH1_THC_INTST_SHIFT 9 +#define DMA_INTST_CH1_THC_INTST_WIDTH 1 +#define DMA_INTST_CH1_THC_INTST_MASK (((1U << DMA_INTST_CH1_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_THC_INTST_SHIFT) +#define DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH1_THC_INTST_BITS_NOT_SET (DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_THC_INTST_SHIFT) +#define DMA_INTST_CH1_THC_INTST_VALUE_SET 1U +#define DMA_INTST_CH1_THC_INTST_BITS_SET (DMA_INTST_CH1_THC_INTST_VALUE_SET << DMA_INTST_CH1_THC_INTST_SHIFT) -#define DMA_INTST_CH2_THC_INTST_SHIFT 10 -#define DMA_INTST_CH2_THC_INTST_WIDTH 1 -#define DMA_INTST_CH2_THC_INTST_MASK (((1U << DMA_INTST_CH2_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_THC_INTST_SHIFT) -#define DMA_INTST_CH2_THC_INTST_NOT_SET (0U << DMA_INTST_CH2_THC_INTST_SHIFT) -#define DMA_INTST_CH2_THC_INTST_SET (1U << DMA_INTST_CH2_THC_INTST_SHIFT) +#define DMA_INTST_CH2_THC_INTST_SHIFT 10 +#define DMA_INTST_CH2_THC_INTST_WIDTH 1 +#define DMA_INTST_CH2_THC_INTST_MASK (((1U << DMA_INTST_CH2_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_THC_INTST_SHIFT) +#define DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH2_THC_INTST_BITS_NOT_SET (DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_THC_INTST_SHIFT) +#define DMA_INTST_CH2_THC_INTST_VALUE_SET 1U +#define DMA_INTST_CH2_THC_INTST_BITS_SET (DMA_INTST_CH2_THC_INTST_VALUE_SET << DMA_INTST_CH2_THC_INTST_SHIFT) -#define DMA_INTST_CH3_THC_INTST_SHIFT 11 -#define DMA_INTST_CH3_THC_INTST_WIDTH 1 -#define DMA_INTST_CH3_THC_INTST_MASK (((1U << DMA_INTST_CH3_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_THC_INTST_SHIFT) -#define DMA_INTST_CH3_THC_INTST_NOT_SET (0U << DMA_INTST_CH3_THC_INTST_SHIFT) -#define DMA_INTST_CH3_THC_INTST_SET (1U << DMA_INTST_CH3_THC_INTST_SHIFT) +#define DMA_INTST_CH3_THC_INTST_SHIFT 11 +#define DMA_INTST_CH3_THC_INTST_WIDTH 1 +#define DMA_INTST_CH3_THC_INTST_MASK (((1U << DMA_INTST_CH3_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_THC_INTST_SHIFT) +#define DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET 0U +#define DMA_INTST_CH3_THC_INTST_BITS_NOT_SET (DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_THC_INTST_SHIFT) +#define DMA_INTST_CH3_THC_INTST_VALUE_SET 1U +#define DMA_INTST_CH3_THC_INTST_BITS_SET (DMA_INTST_CH3_THC_INTST_VALUE_SET << DMA_INTST_CH3_THC_INTST_SHIFT) /* -------- DMA_CH0 -------- */ -#define DMA_CH0_BASE_ADDR 0x40001100U -#define DMA_CH0_BASE_SIZE 0x00000020U -#define DMA_CH0 ((volatile DMA_Channel_t *)DMA_CH0_BASE_ADDR) +#define DMA_CH0_BASE_ADDR 0x40001100U +#define DMA_CH0_BASE_SIZE 0x00000020U +#define DMA_CH0 ((volatile DMA_Channel_t *)DMA_CH0_BASE_ADDR) /* -------- DMA_CH1 -------- */ -#define DMA_CH1_BASE_ADDR 0x40001120U -#define DMA_CH1_BASE_SIZE 0x00000020U -#define DMA_CH1 ((volatile DMA_Channel_t *)DMA_CH1_BASE_ADDR) +#define DMA_CH1_BASE_ADDR 0x40001120U +#define DMA_CH1_BASE_SIZE 0x00000020U +#define DMA_CH1 ((volatile DMA_Channel_t *)DMA_CH1_BASE_ADDR) /* -------- DMA_CH2 -------- */ -#define DMA_CH2_BASE_ADDR 0x40001140U -#define DMA_CH2_BASE_SIZE 0x00000020U -#define DMA_CH2 ((volatile DMA_Channel_t *)DMA_CH2_BASE_ADDR) +#define DMA_CH2_BASE_ADDR 0x40001140U +#define DMA_CH2_BASE_SIZE 0x00000020U +#define DMA_CH2 ((volatile DMA_Channel_t *)DMA_CH2_BASE_ADDR) /* -------- DMA_CH3 -------- */ -#define DMA_CH3_BASE_ADDR 0x40001160U -#define DMA_CH3_BASE_SIZE 0x00000020U -#define DMA_CH3 ((volatile DMA_Channel_t *)DMA_CH3_BASE_ADDR) +#define DMA_CH3_BASE_ADDR 0x40001160U +#define DMA_CH3_BASE_SIZE 0x00000020U +#define DMA_CH3 ((volatile DMA_Channel_t *)DMA_CH3_BASE_ADDR) /* -------- DMA_CH -------- */ @@ -163,85 +197,122 @@ typedef struct { uint32_t ST; } DMA_Channel_t; -#define DMA_CH_CTR_CH_EN_SHIFT 0 -#define DMA_CH_CTR_CH_EN_WIDTH 1 -#define DMA_CH_CTR_CH_EN_MASK (((1U << DMA_CH_CTR_CH_EN_WIDTH) - 1U) << DMA_CH_CTR_CH_EN_SHIFT) -#define DMA_CH_CTR_CH_EN_DISABLE (0U << DMA_CH_CTR_CH_EN_SHIFT) -#define DMA_CH_CTR_CH_EN_ENABLE (1U << DMA_CH_CTR_CH_EN_SHIFT) +#define DMA_CH_CTR_CH_EN_SHIFT 0 +#define DMA_CH_CTR_CH_EN_WIDTH 1 +#define DMA_CH_CTR_CH_EN_MASK (((1U << DMA_CH_CTR_CH_EN_WIDTH) - 1U) << DMA_CH_CTR_CH_EN_SHIFT) +#define DMA_CH_CTR_CH_EN_VALUE_DISABLE 0U +#define DMA_CH_CTR_CH_EN_BITS_DISABLE (DMA_CH_CTR_CH_EN_VALUE_DISABLE << DMA_CH_CTR_CH_EN_SHIFT) +#define DMA_CH_CTR_CH_EN_VALUE_ENABLE 1U +#define DMA_CH_CTR_CH_EN_BITS_ENABLE (DMA_CH_CTR_CH_EN_VALUE_ENABLE << DMA_CH_CTR_CH_EN_SHIFT) -#define DMA_CH_CTR_LENGTH_SHIFT 1 -#define DMA_CH_CTR_LENGTH_WIDTH 12 -#define DMA_CH_CTR_LENGTH_MASK (((1U << DMA_CH_CTR_LENGTH_WIDTH) - 1U) << DMA_CH_CTR_LENGTH_SHIFT) -#define DMA_CH_CTR_LOOP_SHIFT 13 -#define DMA_CH_CTR_LOOP_WIDTH 1 -#define DMA_CH_CTR_LOOP_MASK (((1U << DMA_CH_CTR_LOOP_WIDTH) - 1U) << DMA_CH_CTR_LOOP_SHIFT) -#define DMA_CH_CTR_LOOP_DISABLE (0U << DMA_CH_CTR_LOOP_SHIFT) -#define DMA_CH_CTR_LOOP_ENABLE (1U << DMA_CH_CTR_LOOP_SHIFT) +#define DMA_CH_CTR_LENGTH_SHIFT 1 +#define DMA_CH_CTR_LENGTH_WIDTH 12 +#define DMA_CH_CTR_LENGTH_MASK (((1U << DMA_CH_CTR_LENGTH_WIDTH) - 1U) << DMA_CH_CTR_LENGTH_SHIFT) +#define DMA_CH_CTR_LOOP_SHIFT 13 +#define DMA_CH_CTR_LOOP_WIDTH 1 +#define DMA_CH_CTR_LOOP_MASK (((1U << DMA_CH_CTR_LOOP_WIDTH) - 1U) << DMA_CH_CTR_LOOP_SHIFT) +#define DMA_CH_CTR_LOOP_VALUE_DISABLE 0U +#define DMA_CH_CTR_LOOP_BITS_DISABLE (DMA_CH_CTR_LOOP_VALUE_DISABLE << DMA_CH_CTR_LOOP_SHIFT) +#define DMA_CH_CTR_LOOP_VALUE_ENABLE 1U +#define DMA_CH_CTR_LOOP_BITS_ENABLE (DMA_CH_CTR_LOOP_VALUE_ENABLE << DMA_CH_CTR_LOOP_SHIFT) -#define DMA_CH_CTR_PRI_SHIFT 14 -#define DMA_CH_CTR_PRI_WIDTH 2 -#define DMA_CH_CTR_PRI_MASK (((1U << DMA_CH_CTR_PRI_WIDTH) - 1U) << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_LOW (0U << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_MEDIUM (1U << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_HIGH (2U << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_HIGHEST (3U << DMA_CH_CTR_PRI_SHIFT) +#define DMA_CH_CTR_PRI_SHIFT 14 +#define DMA_CH_CTR_PRI_WIDTH 2 +#define DMA_CH_CTR_PRI_MASK (((1U << DMA_CH_CTR_PRI_WIDTH) - 1U) << DMA_CH_CTR_PRI_SHIFT) +#define DMA_CH_CTR_PRI_VALUE_LOW 0U +#define DMA_CH_CTR_PRI_BITS_LOW (DMA_CH_CTR_PRI_VALUE_LOW << DMA_CH_CTR_PRI_SHIFT) +#define DMA_CH_CTR_PRI_VALUE_MEDIUM 1U +#define DMA_CH_CTR_PRI_BITS_MEDIUM (DMA_CH_CTR_PRI_VALUE_MEDIUM << DMA_CH_CTR_PRI_SHIFT) +#define DMA_CH_CTR_PRI_VALUE_HIGH 2U +#define DMA_CH_CTR_PRI_BITS_HIGH (DMA_CH_CTR_PRI_VALUE_HIGH << DMA_CH_CTR_PRI_SHIFT) +#define DMA_CH_CTR_PRI_VALUE_HIGHEST 3U +#define DMA_CH_CTR_PRI_BITS_HIGHEST (DMA_CH_CTR_PRI_VALUE_HIGHEST << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_SWREQ_SHIFT 16 -#define DMA_CH_CTR_SWREQ_WIDTH 1 -#define DMA_CH_CTR_SWREQ_MASK (((1U << DMA_CH_CTR_SWREQ_WIDTH) - 1U) << DMA_CH_CTR_SWREQ_SHIFT) -#define DMA_CH_CTR_SWREQ_SET (1U << DMA_CH_CTR_SWREQ_SHIFT) +#define DMA_CH_CTR_SWREQ_SHIFT 16 +#define DMA_CH_CTR_SWREQ_WIDTH 1 +#define DMA_CH_CTR_SWREQ_MASK (((1U << DMA_CH_CTR_SWREQ_WIDTH) - 1U) << DMA_CH_CTR_SWREQ_SHIFT) +#define DMA_CH_CTR_SWREQ_VALUE_SET 1U +#define DMA_CH_CTR_SWREQ_BITS_SET (DMA_CH_CTR_SWREQ_VALUE_SET << DMA_CH_CTR_SWREQ_SHIFT) -#define DMA_CH_MOD_MS_ADDMOD_SHIFT 0 -#define DMA_CH_MOD_MS_ADDMOD_WIDTH 1 -#define DMA_CH_MOD_MS_ADDMOD_MASK (((1U << DMA_CH_MOD_MS_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MS_ADDMOD_SHIFT) -#define DMA_CH_MOD_MS_ADDMOD_NONE (0U << DMA_CH_MOD_MS_ADDMOD_SHIFT) -#define DMA_CH_MOD_MS_ADDMOD_INCREMENT (1U << DMA_CH_MOD_MS_ADDMOD_SHIFT) +#define DMA_CH_MOD_MS_ADDMOD_SHIFT 0 +#define DMA_CH_MOD_MS_ADDMOD_WIDTH 1 +#define DMA_CH_MOD_MS_ADDMOD_MASK (((1U << DMA_CH_MOD_MS_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MS_ADDMOD_SHIFT) +#define DMA_CH_MOD_MS_ADDMOD_VALUE_NONE 0U +#define DMA_CH_MOD_MS_ADDMOD_BITS_NONE (DMA_CH_MOD_MS_ADDMOD_VALUE_NONE << DMA_CH_MOD_MS_ADDMOD_SHIFT) +#define DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT 1U +#define DMA_CH_MOD_MS_ADDMOD_BITS_INCREMENT (DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MS_ADDMOD_SHIFT) -#define DMA_CH_MOD_MS_SIZE_SHIFT 1 -#define DMA_CH_MOD_MS_SIZE_WIDTH 2 -#define DMA_CH_MOD_MS_SIZE_MASK (((1U << DMA_CH_MOD_MS_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_8BIT (0U << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_16BIT (1U << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_32BIT (2U << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_KEEP (3U << DMA_CH_MOD_MS_SIZE_SHIFT) +#define DMA_CH_MOD_MS_SIZE_SHIFT 1 +#define DMA_CH_MOD_MS_SIZE_WIDTH 2 +#define DMA_CH_MOD_MS_SIZE_MASK (((1U << DMA_CH_MOD_MS_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MS_SIZE_SHIFT) +#define DMA_CH_MOD_MS_SIZE_VALUE_8BIT 0U +#define DMA_CH_MOD_MS_SIZE_BITS_8BIT (DMA_CH_MOD_MS_SIZE_VALUE_8BIT << DMA_CH_MOD_MS_SIZE_SHIFT) +#define DMA_CH_MOD_MS_SIZE_VALUE_16BIT 1U +#define DMA_CH_MOD_MS_SIZE_BITS_16BIT (DMA_CH_MOD_MS_SIZE_VALUE_16BIT << DMA_CH_MOD_MS_SIZE_SHIFT) +#define DMA_CH_MOD_MS_SIZE_VALUE_32BIT 2U +#define DMA_CH_MOD_MS_SIZE_BITS_32BIT (DMA_CH_MOD_MS_SIZE_VALUE_32BIT << DMA_CH_MOD_MS_SIZE_SHIFT) +#define DMA_CH_MOD_MS_SIZE_VALUE_KEEP 3U +#define DMA_CH_MOD_MS_SIZE_BITS_KEEP (DMA_CH_MOD_MS_SIZE_VALUE_KEEP << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SEL_SHIFT 3 -#define DMA_CH_MOD_MS_SEL_WIDTH 3 -#define DMA_CH_MOD_MS_SEL_MASK (((1U << DMA_CH_MOD_MS_SEL_WIDTH) - 1U) << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_SRAM (0U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS0 (1U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS1 (2U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS2 (3U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS3 (4U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS4 (5U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS5 (6U << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_HSREQ_MS6 (7U << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_SHIFT 3 +#define DMA_CH_MOD_MS_SEL_WIDTH 3 +#define DMA_CH_MOD_MS_SEL_MASK (((1U << DMA_CH_MOD_MS_SEL_WIDTH) - 1U) << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_SRAM 0U +#define DMA_CH_MOD_MS_SEL_BITS_SRAM (DMA_CH_MOD_MS_SEL_VALUE_SRAM << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 1U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS0 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 2U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 3U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS2 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 4U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS3 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 5U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS4 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 6U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS5 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MS_SEL_SHIFT) +#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 7U +#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS6 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MD_ADDMOD_SHIFT 8 -#define DMA_CH_MOD_MD_ADDMOD_WIDTH 1 -#define DMA_CH_MOD_MD_ADDMOD_MASK (((1U << DMA_CH_MOD_MD_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MD_ADDMOD_SHIFT) -#define DMA_CH_MOD_MD_ADDMOD_NONE (0U << DMA_CH_MOD_MD_ADDMOD_SHIFT) -#define DMA_CH_MOD_MD_ADDMOD_INCREMENT (1U << DMA_CH_MOD_MD_ADDMOD_SHIFT) +#define DMA_CH_MOD_MD_ADDMOD_SHIFT 8 +#define DMA_CH_MOD_MD_ADDMOD_WIDTH 1 +#define DMA_CH_MOD_MD_ADDMOD_MASK (((1U << DMA_CH_MOD_MD_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MD_ADDMOD_SHIFT) +#define DMA_CH_MOD_MD_ADDMOD_VALUE_NONE 0U +#define DMA_CH_MOD_MD_ADDMOD_BITS_NONE (DMA_CH_MOD_MD_ADDMOD_VALUE_NONE << DMA_CH_MOD_MD_ADDMOD_SHIFT) +#define DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT 1U +#define DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT (DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MD_ADDMOD_SHIFT) -#define DMA_CH_MOD_MD_SIZE_SHIFT 9 -#define DMA_CH_MOD_MD_SIZE_WIDTH 2 -#define DMA_CH_MOD_MD_SIZE_MASK (((1U << DMA_CH_MOD_MD_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_8BIT (0U << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_16BIT (1U << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_32BIT (2U << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_KEEP (3U << DMA_CH_MOD_MD_SIZE_SHIFT) +#define DMA_CH_MOD_MD_SIZE_SHIFT 9 +#define DMA_CH_MOD_MD_SIZE_WIDTH 2 +#define DMA_CH_MOD_MD_SIZE_MASK (((1U << DMA_CH_MOD_MD_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MD_SIZE_SHIFT) +#define DMA_CH_MOD_MD_SIZE_VALUE_8BIT 0U +#define DMA_CH_MOD_MD_SIZE_BITS_8BIT (DMA_CH_MOD_MD_SIZE_VALUE_8BIT << DMA_CH_MOD_MD_SIZE_SHIFT) +#define DMA_CH_MOD_MD_SIZE_VALUE_16BIT 1U +#define DMA_CH_MOD_MD_SIZE_BITS_16BIT (DMA_CH_MOD_MD_SIZE_VALUE_16BIT << DMA_CH_MOD_MD_SIZE_SHIFT) +#define DMA_CH_MOD_MD_SIZE_VALUE_32BIT 2U +#define DMA_CH_MOD_MD_SIZE_BITS_32BIT (DMA_CH_MOD_MD_SIZE_VALUE_32BIT << DMA_CH_MOD_MD_SIZE_SHIFT) +#define DMA_CH_MOD_MD_SIZE_VALUE_KEEP 3U +#define DMA_CH_MOD_MD_SIZE_BITS_KEEP (DMA_CH_MOD_MD_SIZE_VALUE_KEEP << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SEL_SHIFT 11 -#define DMA_CH_MOD_MD_SEL_WIDTH 3 -#define DMA_CH_MOD_MD_SEL_MASK (((1U << DMA_CH_MOD_MD_SEL_WIDTH) - 1U) << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_SRAM (0U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS0 (1U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS1 (2U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS2 (3U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS3 (4U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS4 (5U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS5 (6U << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_HSREQ_MS6 (7U << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_SHIFT 11 +#define DMA_CH_MOD_MD_SEL_WIDTH 3 +#define DMA_CH_MOD_MD_SEL_MASK (((1U << DMA_CH_MOD_MD_SEL_WIDTH) - 1U) << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_SRAM 0U +#define DMA_CH_MOD_MD_SEL_BITS_SRAM (DMA_CH_MOD_MD_SEL_VALUE_SRAM << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 1U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS0 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 2U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS1 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 3U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS2 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 4U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS3 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 5U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS4 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 6U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS5 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MD_SEL_SHIFT) +#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 7U +#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS6 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MD_SEL_SHIFT) #endif diff --git a/bsp/dp32g030/flash.h b/bsp/dp32g030/flash.h index 5f36ea1..f17b3d0 100644 --- a/bsp/dp32g030/flash.h +++ b/bsp/dp32g030/flash.h @@ -22,118 +22,143 @@ #endif /* -------- FLASH -------- */ -#define FLASH_BASE_ADDR 0x4006F000U -#define FLASH_BASE_SIZE 0x00000800U +#define FLASH_BASE_ADDR 0x4006F000U +#define FLASH_BASE_SIZE 0x00000800U -#define FLASH_CFG_ADDR (FLASH_BASE_ADDR + 0x0000U) -#define FLASH_CFG (*(volatile uint32_t *)FLASH_CFG_ADDR) -#define FLASH_CFG_READ_MD_SHIFT 0 -#define FLASH_CFG_READ_MD_WIDTH 1 -#define FLASH_CFG_READ_MD_MASK (((1U << FLASH_CFG_READ_MD_WIDTH) - 1U) << FLASH_CFG_READ_MD_SHIFT) -#define FLASH_CFG_READ_MD_1_CYCLE (0U << FLASH_CFG_READ_MD_SHIFT) -#define FLASH_CFG_READ_MD_2_CYCLE (1U << FLASH_CFG_READ_MD_SHIFT) +#define FLASH_CFG_ADDR (FLASH_BASE_ADDR + 0x0000U) +#define FLASH_CFG (*(volatile uint32_t *)FLASH_CFG_ADDR) +#define FLASH_CFG_READ_MD_SHIFT 0 +#define FLASH_CFG_READ_MD_WIDTH 1 +#define FLASH_CFG_READ_MD_MASK (((1U << FLASH_CFG_READ_MD_WIDTH) - 1U) << FLASH_CFG_READ_MD_SHIFT) +#define FLASH_CFG_READ_MD_VALUE_1_CYCLE 0U +#define FLASH_CFG_READ_MD_BITS_1_CYCLE (FLASH_CFG_READ_MD_VALUE_1_CYCLE << FLASH_CFG_READ_MD_SHIFT) +#define FLASH_CFG_READ_MD_VALUE_2_CYCLE 1U +#define FLASH_CFG_READ_MD_BITS_2_CYCLE (FLASH_CFG_READ_MD_VALUE_2_CYCLE << FLASH_CFG_READ_MD_SHIFT) -#define FLASH_CFG_NVR_SEL_SHIFT 1 -#define FLASH_CFG_NVR_SEL_WIDTH 1 -#define FLASH_CFG_NVR_SEL_MASK (((1U << FLASH_CFG_NVR_SEL_WIDTH) - 1U) << FLASH_CFG_NVR_SEL_SHIFT) -#define FLASH_CFG_NVR_SEL_MAIN (0U << FLASH_CFG_NVR_SEL_SHIFT) -#define FLASH_CFG_NVR_SEL_NVR (1U << FLASH_CFG_NVR_SEL_SHIFT) +#define FLASH_CFG_NVR_SEL_SHIFT 1 +#define FLASH_CFG_NVR_SEL_WIDTH 1 +#define FLASH_CFG_NVR_SEL_MASK (((1U << FLASH_CFG_NVR_SEL_WIDTH) - 1U) << FLASH_CFG_NVR_SEL_SHIFT) +#define FLASH_CFG_NVR_SEL_VALUE_MAIN 0U +#define FLASH_CFG_NVR_SEL_BITS_MAIN (FLASH_CFG_NVR_SEL_VALUE_MAIN << FLASH_CFG_NVR_SEL_SHIFT) +#define FLASH_CFG_NVR_SEL_VALUE_NVR 1U +#define FLASH_CFG_NVR_SEL_BITS_NVR (FLASH_CFG_NVR_SEL_VALUE_NVR << FLASH_CFG_NVR_SEL_SHIFT) -#define FLASH_CFG_MODE_SHIFT 2 -#define FLASH_CFG_MODE_WIDTH 3 -#define FLASH_CFG_MODE_MASK (((1U << FLASH_CFG_MODE_WIDTH) - 1U) << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_READ_AHB (0U << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_PROGRAM (1U << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_ERASE (2U << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_READ_APB (5U << FLASH_CFG_MODE_SHIFT) +#define FLASH_CFG_MODE_SHIFT 2 +#define FLASH_CFG_MODE_WIDTH 3 +#define FLASH_CFG_MODE_MASK (((1U << FLASH_CFG_MODE_WIDTH) - 1U) << FLASH_CFG_MODE_SHIFT) +#define FLASH_CFG_MODE_VALUE_READ_AHB 0U +#define FLASH_CFG_MODE_BITS_READ_AHB (FLASH_CFG_MODE_VALUE_READ_AHB << FLASH_CFG_MODE_SHIFT) +#define FLASH_CFG_MODE_VALUE_PROGRAM 1U +#define FLASH_CFG_MODE_BITS_PROGRAM (FLASH_CFG_MODE_VALUE_PROGRAM << FLASH_CFG_MODE_SHIFT) +#define FLASH_CFG_MODE_VALUE_ERASE 2U +#define FLASH_CFG_MODE_BITS_ERASE (FLASH_CFG_MODE_VALUE_ERASE << FLASH_CFG_MODE_SHIFT) +#define FLASH_CFG_MODE_VALUE_READ_APB 5U +#define FLASH_CFG_MODE_BITS_READ_APB (FLASH_CFG_MODE_VALUE_READ_APB << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_DEEP_PD_SHIFT 31 -#define FLASH_CFG_DEEP_PD_WIDTH 1 -#define FLASH_CFG_DEEP_PD_MASK (((1U << FLASH_CFG_DEEP_PD_WIDTH) - 1U) << FLASH_CFG_DEEP_PD_SHIFT) -#define FLASH_CFG_DEEP_PD_NORMAL (0U << FLASH_CFG_DEEP_PD_SHIFT) -#define FLASH_CFG_DEEP_PD_LOW_POWER (1U << FLASH_CFG_DEEP_PD_SHIFT) +#define FLASH_CFG_DEEP_PD_SHIFT 31 +#define FLASH_CFG_DEEP_PD_WIDTH 1 +#define FLASH_CFG_DEEP_PD_MASK (((1U << FLASH_CFG_DEEP_PD_WIDTH) - 1U) << FLASH_CFG_DEEP_PD_SHIFT) +#define FLASH_CFG_DEEP_PD_VALUE_NORMAL 0U +#define FLASH_CFG_DEEP_PD_BITS_NORMAL (FLASH_CFG_DEEP_PD_VALUE_NORMAL << FLASH_CFG_DEEP_PD_SHIFT) +#define FLASH_CFG_DEEP_PD_VALUE_LOW_POWER 1U +#define FLASH_CFG_DEEP_PD_BITS_LOW_POWER (FLASH_CFG_DEEP_PD_VALUE_LOW_POWER << FLASH_CFG_DEEP_PD_SHIFT) -#define FLASH_ADDR_ADDR (FLASH_BASE_ADDR + 0x0004U) -#define FLASH_ADDR (*(volatile uint32_t *)FLASH_ADDR_ADDR) -#define FLASH_WDATA_ADDR (FLASH_BASE_ADDR + 0x0008U) -#define FLASH_WDATA (*(volatile uint32_t *)FLASH_WDATA_ADDR) -#define FLASH_RDATA_ADDR (FLASH_BASE_ADDR + 0x000CU) -#define FLASH_RDATA (*(volatile uint32_t *)FLASH_RDATA_ADDR) +#define FLASH_ADDR_ADDR (FLASH_BASE_ADDR + 0x0004U) +#define FLASH_ADDR (*(volatile uint32_t *)FLASH_ADDR_ADDR) +#define FLASH_WDATA_ADDR (FLASH_BASE_ADDR + 0x0008U) +#define FLASH_WDATA (*(volatile uint32_t *)FLASH_WDATA_ADDR) +#define FLASH_RDATA_ADDR (FLASH_BASE_ADDR + 0x000CU) +#define FLASH_RDATA (*(volatile uint32_t *)FLASH_RDATA_ADDR) -#define FLASH_START_ADDR (FLASH_BASE_ADDR + 0x0010U) -#define FLASH_START (*(volatile uint32_t *)FLASH_START_ADDR) -#define FLASH_START_START_SHIFT 0 -#define FLASH_START_START_WIDTH 1 -#define FLASH_START_START_MASK (((1U << FLASH_START_START_WIDTH) - 1U) << FLASH_START_START_SHIFT) -#define FLASH_START_START_START (1U << FLASH_START_START_SHIFT) +#define FLASH_START_ADDR (FLASH_BASE_ADDR + 0x0010U) +#define FLASH_START (*(volatile uint32_t *)FLASH_START_ADDR) +#define FLASH_START_START_SHIFT 0 +#define FLASH_START_START_WIDTH 1 +#define FLASH_START_START_MASK (((1U << FLASH_START_START_WIDTH) - 1U) << FLASH_START_START_SHIFT) +#define FLASH_START_START_VALUE_START 1U +#define FLASH_START_START_BITS_START (FLASH_START_START_VALUE_START << FLASH_START_START_SHIFT) -#define FLASH_ST_ADDR (FLASH_BASE_ADDR + 0x0014U) -#define FLASH_ST (*(volatile uint32_t *)FLASH_ST_ADDR) -#define FLASH_ST_INIT_BUSY_SHIFT 0 -#define FLASH_ST_INIT_BUSY_WIDTH 1 -#define FLASH_ST_INIT_BUSY_MASK (((1U << FLASH_ST_INIT_BUSY_WIDTH) - 1U) << FLASH_ST_INIT_BUSY_SHIFT) -#define FLASH_ST_INIT_BUSY_COMPLETE (0U << FLASH_ST_INIT_BUSY_SHIFT) -#define FLASH_ST_INIT_BUSY_BUSY (1U << FLASH_ST_INIT_BUSY_SHIFT) +#define FLASH_ST_ADDR (FLASH_BASE_ADDR + 0x0014U) +#define FLASH_ST (*(volatile uint32_t *)FLASH_ST_ADDR) +#define FLASH_ST_INIT_BUSY_SHIFT 0 +#define FLASH_ST_INIT_BUSY_WIDTH 1 +#define FLASH_ST_INIT_BUSY_MASK (((1U << FLASH_ST_INIT_BUSY_WIDTH) - 1U) << FLASH_ST_INIT_BUSY_SHIFT) +#define FLASH_ST_INIT_BUSY_VALUE_COMPLETE 0U +#define FLASH_ST_INIT_BUSY_BITS_COMPLETE (FLASH_ST_INIT_BUSY_VALUE_COMPLETE << FLASH_ST_INIT_BUSY_SHIFT) +#define FLASH_ST_INIT_BUSY_VALUE_BUSY 1U +#define FLASH_ST_INIT_BUSY_BITS_BUSY (FLASH_ST_INIT_BUSY_VALUE_BUSY << FLASH_ST_INIT_BUSY_SHIFT) -#define FLASH_ST_BUSY_SHIFT 1 -#define FLASH_ST_BUSY_WIDTH 1 -#define FLASH_ST_BUSY_MASK (((1U << FLASH_ST_BUSY_WIDTH) - 1U) << FLASH_ST_BUSY_SHIFT) -#define FLASH_ST_BUSY_READY (0U << FLASH_ST_BUSY_SHIFT) -#define FLASH_ST_BUSY_BUSY (1U << FLASH_ST_BUSY_SHIFT) +#define FLASH_ST_BUSY_SHIFT 1 +#define FLASH_ST_BUSY_WIDTH 1 +#define FLASH_ST_BUSY_MASK (((1U << FLASH_ST_BUSY_WIDTH) - 1U) << FLASH_ST_BUSY_SHIFT) +#define FLASH_ST_BUSY_VALUE_READY 0U +#define FLASH_ST_BUSY_BITS_READY (FLASH_ST_BUSY_VALUE_READY << FLASH_ST_BUSY_SHIFT) +#define FLASH_ST_BUSY_VALUE_BUSY 1U +#define FLASH_ST_BUSY_BITS_BUSY (FLASH_ST_BUSY_VALUE_BUSY << FLASH_ST_BUSY_SHIFT) -#define FLASH_ST_PROG_BUF_EMPTY_SHIFT 2 -#define FLASH_ST_PROG_BUF_EMPTY_WIDTH 1 -#define FLASH_ST_PROG_BUF_EMPTY_MASK (((1U << FLASH_ST_PROG_BUF_EMPTY_WIDTH) - 1U) << FLASH_ST_PROG_BUF_EMPTY_SHIFT) -#define FLASH_ST_PROG_BUF_EMPTY_NOT_EMPTY (0U << FLASH_ST_PROG_BUF_EMPTY_SHIFT) -#define FLASH_ST_PROG_BUF_EMPTY_EMPTY (1U << FLASH_ST_PROG_BUF_EMPTY_SHIFT) +#define FLASH_ST_PROG_BUF_EMPTY_SHIFT 2 +#define FLASH_ST_PROG_BUF_EMPTY_WIDTH 1 +#define FLASH_ST_PROG_BUF_EMPTY_MASK (((1U << FLASH_ST_PROG_BUF_EMPTY_WIDTH) - 1U) << FLASH_ST_PROG_BUF_EMPTY_SHIFT) +#define FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY 0U +#define FLASH_ST_PROG_BUF_EMPTY_BITS_NOT_EMPTY (FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT) +#define FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY 1U +#define FLASH_ST_PROG_BUF_EMPTY_BITS_EMPTY (FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT) -#define FLASH_LOCK_ADDR (FLASH_BASE_ADDR + 0x0018U) -#define FLASH_LOCK (*(volatile uint32_t *)FLASH_LOCK_ADDR) -#define FLASH_LOCK_LOCK_SHIFT 0 -#define FLASH_LOCK_LOCK_WIDTH 8 -#define FLASH_LOCK_LOCK_MASK (((1U << FLASH_LOCK_LOCK_WIDTH) - 1U) << FLASH_LOCK_LOCK_SHIFT) -#define FLASH_LOCK_LOCK_LOCK (85U << FLASH_LOCK_LOCK_SHIFT) +#define FLASH_LOCK_ADDR (FLASH_BASE_ADDR + 0x0018U) +#define FLASH_LOCK (*(volatile uint32_t *)FLASH_LOCK_ADDR) +#define FLASH_LOCK_LOCK_SHIFT 0 +#define FLASH_LOCK_LOCK_WIDTH 8 +#define FLASH_LOCK_LOCK_MASK (((1U << FLASH_LOCK_LOCK_WIDTH) - 1U) << FLASH_LOCK_LOCK_SHIFT) +#define FLASH_LOCK_LOCK_VALUE_LOCK 85U +#define FLASH_LOCK_LOCK_BITS_LOCK (FLASH_LOCK_LOCK_VALUE_LOCK << FLASH_LOCK_LOCK_SHIFT) -#define FLASH_UNLOCK_ADDR (FLASH_BASE_ADDR + 0x001CU) -#define FLASH_UNLOCK (*(volatile uint32_t *)FLASH_UNLOCK_ADDR) -#define FLASH_UNLOCK_UNLOCK_SHIFT 0 -#define FLASH_UNLOCK_UNLOCK_WIDTH 8 -#define FLASH_UNLOCK_UNLOCK_MASK (((1U << FLASH_UNLOCK_UNLOCK_WIDTH) - 1U) << FLASH_UNLOCK_UNLOCK_SHIFT) -#define FLASH_UNLOCK_UNLOCK_UNLOCK (170U << FLASH_UNLOCK_UNLOCK_SHIFT) +#define FLASH_UNLOCK_ADDR (FLASH_BASE_ADDR + 0x001CU) +#define FLASH_UNLOCK (*(volatile uint32_t *)FLASH_UNLOCK_ADDR) +#define FLASH_UNLOCK_UNLOCK_SHIFT 0 +#define FLASH_UNLOCK_UNLOCK_WIDTH 8 +#define FLASH_UNLOCK_UNLOCK_MASK (((1U << FLASH_UNLOCK_UNLOCK_WIDTH) - 1U) << FLASH_UNLOCK_UNLOCK_SHIFT) +#define FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK 170U +#define FLASH_UNLOCK_UNLOCK_BITS_UNLOCK (FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK << FLASH_UNLOCK_UNLOCK_SHIFT) -#define FLASH_MASK_ADDR (FLASH_BASE_ADDR + 0x0020U) -#define FLASH_MASK (*(volatile uint32_t *)FLASH_MASK_ADDR) -#define FLASH_MASK_SEL_SHIFT 0 -#define FLASH_MASK_SEL_WIDTH 2 -#define FLASH_MASK_SEL_MASK (((1U << FLASH_MASK_SEL_WIDTH) - 1U) << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_NONE (0U << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_2KB (1U << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_4KB (2U << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_8KB (3U << FLASH_MASK_SEL_SHIFT) +#define FLASH_MASK_ADDR (FLASH_BASE_ADDR + 0x0020U) +#define FLASH_MASK (*(volatile uint32_t *)FLASH_MASK_ADDR) +#define FLASH_MASK_SEL_SHIFT 0 +#define FLASH_MASK_SEL_WIDTH 2 +#define FLASH_MASK_SEL_MASK (((1U << FLASH_MASK_SEL_WIDTH) - 1U) << FLASH_MASK_SEL_SHIFT) +#define FLASH_MASK_SEL_VALUE_NONE 0U +#define FLASH_MASK_SEL_BITS_NONE (FLASH_MASK_SEL_VALUE_NONE << FLASH_MASK_SEL_SHIFT) +#define FLASH_MASK_SEL_VALUE_2KB 1U +#define FLASH_MASK_SEL_BITS_2KB (FLASH_MASK_SEL_VALUE_2KB << FLASH_MASK_SEL_SHIFT) +#define FLASH_MASK_SEL_VALUE_4KB 2U +#define FLASH_MASK_SEL_BITS_4KB (FLASH_MASK_SEL_VALUE_4KB << FLASH_MASK_SEL_SHIFT) +#define FLASH_MASK_SEL_VALUE_8KB 3U +#define FLASH_MASK_SEL_BITS_8KB (FLASH_MASK_SEL_VALUE_8KB << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_LOCK_SHIFT 2 -#define FLASH_MASK_LOCK_WIDTH 1 -#define FLASH_MASK_LOCK_MASK (((1U << FLASH_MASK_LOCK_WIDTH) - 1U) << FLASH_MASK_LOCK_SHIFT) -#define FLASH_MASK_LOCK_NOT_SET (0U << FLASH_MASK_LOCK_SHIFT) -#define FLASH_MASK_LOCK_SET (1U << FLASH_MASK_LOCK_SHIFT) +#define FLASH_MASK_LOCK_SHIFT 2 +#define FLASH_MASK_LOCK_WIDTH 1 +#define FLASH_MASK_LOCK_MASK (((1U << FLASH_MASK_LOCK_WIDTH) - 1U) << FLASH_MASK_LOCK_SHIFT) +#define FLASH_MASK_LOCK_VALUE_NOT_SET 0U +#define FLASH_MASK_LOCK_BITS_NOT_SET (FLASH_MASK_LOCK_VALUE_NOT_SET << FLASH_MASK_LOCK_SHIFT) +#define FLASH_MASK_LOCK_VALUE_SET 1U +#define FLASH_MASK_LOCK_BITS_SET (FLASH_MASK_LOCK_VALUE_SET << FLASH_MASK_LOCK_SHIFT) -#define FLASH_ERASETIME_ADDR (FLASH_BASE_ADDR + 0x0024U) -#define FLASH_ERASETIME (*(volatile uint32_t *)FLASH_ERASETIME_ADDR) -#define FLASH_ERASETIME_TERASE_SHIFT 0 -#define FLASH_ERASETIME_TERASE_WIDTH 19 -#define FLASH_ERASETIME_TERASE_MASK (((1U << FLASH_ERASETIME_TERASE_WIDTH) - 1U) << FLASH_ERASETIME_TERASE_SHIFT) -#define FLASH_ERASETIME_TRCV_SHIFT 19 -#define FLASH_ERASETIME_TRCV_WIDTH 12 -#define FLASH_ERASETIME_TRCV_MASK (((1U << FLASH_ERASETIME_TRCV_WIDTH) - 1U) << FLASH_ERASETIME_TRCV_SHIFT) +#define FLASH_ERASETIME_ADDR (FLASH_BASE_ADDR + 0x0024U) +#define FLASH_ERASETIME (*(volatile uint32_t *)FLASH_ERASETIME_ADDR) +#define FLASH_ERASETIME_TERASE_SHIFT 0 +#define FLASH_ERASETIME_TERASE_WIDTH 19 +#define FLASH_ERASETIME_TERASE_MASK (((1U << FLASH_ERASETIME_TERASE_WIDTH) - 1U) << FLASH_ERASETIME_TERASE_SHIFT) +#define FLASH_ERASETIME_TRCV_SHIFT 19 +#define FLASH_ERASETIME_TRCV_WIDTH 12 +#define FLASH_ERASETIME_TRCV_MASK (((1U << FLASH_ERASETIME_TRCV_WIDTH) - 1U) << FLASH_ERASETIME_TRCV_SHIFT) -#define FLASH_PROGTIME_ADDR (FLASH_BASE_ADDR + 0x0028U) -#define FLASH_PROGTIME (*(volatile uint32_t *)FLASH_PROGTIME_ADDR) -#define FLASH_PROGTIME_TPROG_SHIFT 0 -#define FLASH_PROGTIME_TPROG_WIDTH 11 -#define FLASH_PROGTIME_TPROG_MASK (((1U << FLASH_PROGTIME_TPROG_WIDTH) - 1U) << FLASH_PROGTIME_TPROG_SHIFT) -#define FLASH_PROGTIME_TPGS_SHIFT 11 -#define FLASH_PROGTIME_TPGS_WIDTH 11 -#define FLASH_PROGTIME_TPGS_MASK (((1U << FLASH_PROGTIME_TPGS_WIDTH) - 1U) << FLASH_PROGTIME_TPGS_SHIFT) +#define FLASH_PROGTIME_ADDR (FLASH_BASE_ADDR + 0x0028U) +#define FLASH_PROGTIME (*(volatile uint32_t *)FLASH_PROGTIME_ADDR) +#define FLASH_PROGTIME_TPROG_SHIFT 0 +#define FLASH_PROGTIME_TPROG_WIDTH 11 +#define FLASH_PROGTIME_TPROG_MASK (((1U << FLASH_PROGTIME_TPROG_WIDTH) - 1U) << FLASH_PROGTIME_TPROG_SHIFT) +#define FLASH_PROGTIME_TPGS_SHIFT 11 +#define FLASH_PROGTIME_TPGS_WIDTH 11 +#define FLASH_PROGTIME_TPGS_MASK (((1U << FLASH_PROGTIME_TPGS_WIDTH) - 1U) << FLASH_PROGTIME_TPGS_SHIFT) #endif diff --git a/bsp/dp32g030/gpio.h b/bsp/dp32g030/gpio.h index 4288629..6c9bbcb 100644 --- a/bsp/dp32g030/gpio.h +++ b/bsp/dp32g030/gpio.h @@ -22,19 +22,19 @@ #endif /* -------- GPIOA -------- */ -#define GPIOA_BASE_ADDR 0x40060000U -#define GPIOA_BASE_SIZE 0x00000800U -#define GPIOA ((volatile GPIO_Bank_t *)GPIOA_BASE_ADDR) +#define GPIOA_BASE_ADDR 0x40060000U +#define GPIOA_BASE_SIZE 0x00000800U +#define GPIOA ((volatile GPIO_Bank_t *)GPIOA_BASE_ADDR) /* -------- GPIOB -------- */ -#define GPIOB_BASE_ADDR 0x40060800U -#define GPIOB_BASE_SIZE 0x00000800U -#define GPIOB ((volatile GPIO_Bank_t *)GPIOB_BASE_ADDR) +#define GPIOB_BASE_ADDR 0x40060800U +#define GPIOB_BASE_SIZE 0x00000800U +#define GPIOB ((volatile GPIO_Bank_t *)GPIOB_BASE_ADDR) /* -------- GPIOC -------- */ -#define GPIOC_BASE_ADDR 0x40061000U -#define GPIOC_BASE_SIZE 0x00000800U -#define GPIOC ((volatile GPIO_Bank_t *)GPIOC_BASE_ADDR) +#define GPIOC_BASE_ADDR 0x40061000U +#define GPIOC_BASE_SIZE 0x00000800U +#define GPIOC ((volatile GPIO_Bank_t *)GPIOC_BASE_ADDR) /* -------- GPIO -------- */ @@ -43,101 +43,133 @@ typedef struct { uint32_t DIR; } GPIO_Bank_t; -#define GPIO_DIR_0_SHIFT 0 -#define GPIO_DIR_0_WIDTH 1 -#define GPIO_DIR_0_MASK (((1U << GPIO_DIR_0_WIDTH) - 1U) << GPIO_DIR_0_SHIFT) -#define GPIO_DIR_0_INPUT (0U << GPIO_DIR_0_SHIFT) -#define GPIO_DIR_0_OUTPUT (1U << GPIO_DIR_0_SHIFT) +#define GPIO_DIR_0_SHIFT 0 +#define GPIO_DIR_0_WIDTH 1 +#define GPIO_DIR_0_MASK (((1U << GPIO_DIR_0_WIDTH) - 1U) << GPIO_DIR_0_SHIFT) +#define GPIO_DIR_0_VALUE_INPUT 0U +#define GPIO_DIR_0_BITS_INPUT (GPIO_DIR_0_VALUE_INPUT << GPIO_DIR_0_SHIFT) +#define GPIO_DIR_0_VALUE_OUTPUT 1U +#define GPIO_DIR_0_BITS_OUTPUT (GPIO_DIR_0_VALUE_OUTPUT << GPIO_DIR_0_SHIFT) -#define GPIO_DIR_1_SHIFT 1 -#define GPIO_DIR_1_WIDTH 1 -#define GPIO_DIR_1_MASK (((1U << GPIO_DIR_1_WIDTH) - 1U) << GPIO_DIR_1_SHIFT) -#define GPIO_DIR_1_INPUT (0U << GPIO_DIR_1_SHIFT) -#define GPIO_DIR_1_OUTPUT (1U << GPIO_DIR_1_SHIFT) +#define GPIO_DIR_1_SHIFT 1 +#define GPIO_DIR_1_WIDTH 1 +#define GPIO_DIR_1_MASK (((1U << GPIO_DIR_1_WIDTH) - 1U) << GPIO_DIR_1_SHIFT) +#define GPIO_DIR_1_VALUE_INPUT 0U +#define GPIO_DIR_1_BITS_INPUT (GPIO_DIR_1_VALUE_INPUT << GPIO_DIR_1_SHIFT) +#define GPIO_DIR_1_VALUE_OUTPUT 1U +#define GPIO_DIR_1_BITS_OUTPUT (GPIO_DIR_1_VALUE_OUTPUT << GPIO_DIR_1_SHIFT) -#define GPIO_DIR_2_SHIFT 2 -#define GPIO_DIR_2_WIDTH 1 -#define GPIO_DIR_2_MASK (((1U << GPIO_DIR_2_WIDTH) - 1U) << GPIO_DIR_2_SHIFT) -#define GPIO_DIR_2_INPUT (0U << GPIO_DIR_2_SHIFT) -#define GPIO_DIR_2_OUTPUT (1U << GPIO_DIR_2_SHIFT) +#define GPIO_DIR_2_SHIFT 2 +#define GPIO_DIR_2_WIDTH 1 +#define GPIO_DIR_2_MASK (((1U << GPIO_DIR_2_WIDTH) - 1U) << GPIO_DIR_2_SHIFT) +#define GPIO_DIR_2_VALUE_INPUT 0U +#define GPIO_DIR_2_BITS_INPUT (GPIO_DIR_2_VALUE_INPUT << GPIO_DIR_2_SHIFT) +#define GPIO_DIR_2_VALUE_OUTPUT 1U +#define GPIO_DIR_2_BITS_OUTPUT (GPIO_DIR_2_VALUE_OUTPUT << GPIO_DIR_2_SHIFT) -#define GPIO_DIR_3_SHIFT 3 -#define GPIO_DIR_3_WIDTH 1 -#define GPIO_DIR_3_MASK (((1U << GPIO_DIR_3_WIDTH) - 1U) << GPIO_DIR_3_SHIFT) -#define GPIO_DIR_3_INPUT (0U << GPIO_DIR_3_SHIFT) -#define GPIO_DIR_3_OUTPUT (1U << GPIO_DIR_3_SHIFT) +#define GPIO_DIR_3_SHIFT 3 +#define GPIO_DIR_3_WIDTH 1 +#define GPIO_DIR_3_MASK (((1U << GPIO_DIR_3_WIDTH) - 1U) << GPIO_DIR_3_SHIFT) +#define GPIO_DIR_3_VALUE_INPUT 0U +#define GPIO_DIR_3_BITS_INPUT (GPIO_DIR_3_VALUE_INPUT << GPIO_DIR_3_SHIFT) +#define GPIO_DIR_3_VALUE_OUTPUT 1U +#define GPIO_DIR_3_BITS_OUTPUT (GPIO_DIR_3_VALUE_OUTPUT << GPIO_DIR_3_SHIFT) -#define GPIO_DIR_4_SHIFT 4 -#define GPIO_DIR_4_WIDTH 1 -#define GPIO_DIR_4_MASK (((1U << GPIO_DIR_4_WIDTH) - 1U) << GPIO_DIR_4_SHIFT) -#define GPIO_DIR_4_INPUT (0U << GPIO_DIR_4_SHIFT) -#define GPIO_DIR_4_OUTPUT (1U << GPIO_DIR_4_SHIFT) +#define GPIO_DIR_4_SHIFT 4 +#define GPIO_DIR_4_WIDTH 1 +#define GPIO_DIR_4_MASK (((1U << GPIO_DIR_4_WIDTH) - 1U) << GPIO_DIR_4_SHIFT) +#define GPIO_DIR_4_VALUE_INPUT 0U +#define GPIO_DIR_4_BITS_INPUT (GPIO_DIR_4_VALUE_INPUT << GPIO_DIR_4_SHIFT) +#define GPIO_DIR_4_VALUE_OUTPUT 1U +#define GPIO_DIR_4_BITS_OUTPUT (GPIO_DIR_4_VALUE_OUTPUT << GPIO_DIR_4_SHIFT) -#define GPIO_DIR_5_SHIFT 5 -#define GPIO_DIR_5_WIDTH 1 -#define GPIO_DIR_5_MASK (((1U << GPIO_DIR_5_WIDTH) - 1U) << GPIO_DIR_5_SHIFT) -#define GPIO_DIR_5_INPUT (0U << GPIO_DIR_5_SHIFT) -#define GPIO_DIR_5_OUTPUT (1U << GPIO_DIR_5_SHIFT) +#define GPIO_DIR_5_SHIFT 5 +#define GPIO_DIR_5_WIDTH 1 +#define GPIO_DIR_5_MASK (((1U << GPIO_DIR_5_WIDTH) - 1U) << GPIO_DIR_5_SHIFT) +#define GPIO_DIR_5_VALUE_INPUT 0U +#define GPIO_DIR_5_BITS_INPUT (GPIO_DIR_5_VALUE_INPUT << GPIO_DIR_5_SHIFT) +#define GPIO_DIR_5_VALUE_OUTPUT 1U +#define GPIO_DIR_5_BITS_OUTPUT (GPIO_DIR_5_VALUE_OUTPUT << GPIO_DIR_5_SHIFT) -#define GPIO_DIR_6_SHIFT 6 -#define GPIO_DIR_6_WIDTH 1 -#define GPIO_DIR_6_MASK (((1U << GPIO_DIR_6_WIDTH) - 1U) << GPIO_DIR_6_SHIFT) -#define GPIO_DIR_6_INPUT (0U << GPIO_DIR_6_SHIFT) -#define GPIO_DIR_6_OUTPUT (1U << GPIO_DIR_6_SHIFT) +#define GPIO_DIR_6_SHIFT 6 +#define GPIO_DIR_6_WIDTH 1 +#define GPIO_DIR_6_MASK (((1U << GPIO_DIR_6_WIDTH) - 1U) << GPIO_DIR_6_SHIFT) +#define GPIO_DIR_6_VALUE_INPUT 0U +#define GPIO_DIR_6_BITS_INPUT (GPIO_DIR_6_VALUE_INPUT << GPIO_DIR_6_SHIFT) +#define GPIO_DIR_6_VALUE_OUTPUT 1U +#define GPIO_DIR_6_BITS_OUTPUT (GPIO_DIR_6_VALUE_OUTPUT << GPIO_DIR_6_SHIFT) -#define GPIO_DIR_7_SHIFT 7 -#define GPIO_DIR_7_WIDTH 1 -#define GPIO_DIR_7_MASK (((1U << GPIO_DIR_7_WIDTH) - 1U) << GPIO_DIR_7_SHIFT) -#define GPIO_DIR_7_INPUT (0U << GPIO_DIR_7_SHIFT) -#define GPIO_DIR_7_OUTPUT (1U << GPIO_DIR_7_SHIFT) +#define GPIO_DIR_7_SHIFT 7 +#define GPIO_DIR_7_WIDTH 1 +#define GPIO_DIR_7_MASK (((1U << GPIO_DIR_7_WIDTH) - 1U) << GPIO_DIR_7_SHIFT) +#define GPIO_DIR_7_VALUE_INPUT 0U +#define GPIO_DIR_7_BITS_INPUT (GPIO_DIR_7_VALUE_INPUT << GPIO_DIR_7_SHIFT) +#define GPIO_DIR_7_VALUE_OUTPUT 1U +#define GPIO_DIR_7_BITS_OUTPUT (GPIO_DIR_7_VALUE_OUTPUT << GPIO_DIR_7_SHIFT) -#define GPIO_DIR_8_SHIFT 8 -#define GPIO_DIR_8_WIDTH 1 -#define GPIO_DIR_8_MASK (((1U << GPIO_DIR_8_WIDTH) - 1U) << GPIO_DIR_8_SHIFT) -#define GPIO_DIR_8_INPUT (0U << GPIO_DIR_8_SHIFT) -#define GPIO_DIR_8_OUTPUT (1U << GPIO_DIR_8_SHIFT) +#define GPIO_DIR_8_SHIFT 8 +#define GPIO_DIR_8_WIDTH 1 +#define GPIO_DIR_8_MASK (((1U << GPIO_DIR_8_WIDTH) - 1U) << GPIO_DIR_8_SHIFT) +#define GPIO_DIR_8_VALUE_INPUT 0U +#define GPIO_DIR_8_BITS_INPUT (GPIO_DIR_8_VALUE_INPUT << GPIO_DIR_8_SHIFT) +#define GPIO_DIR_8_VALUE_OUTPUT 1U +#define GPIO_DIR_8_BITS_OUTPUT (GPIO_DIR_8_VALUE_OUTPUT << GPIO_DIR_8_SHIFT) -#define GPIO_DIR_9_SHIFT 9 -#define GPIO_DIR_9_WIDTH 1 -#define GPIO_DIR_9_MASK (((1U << GPIO_DIR_9_WIDTH) - 1U) << GPIO_DIR_9_SHIFT) -#define GPIO_DIR_9_INPUT (0U << GPIO_DIR_9_SHIFT) -#define GPIO_DIR_9_OUTPUT (1U << GPIO_DIR_9_SHIFT) +#define GPIO_DIR_9_SHIFT 9 +#define GPIO_DIR_9_WIDTH 1 +#define GPIO_DIR_9_MASK (((1U << GPIO_DIR_9_WIDTH) - 1U) << GPIO_DIR_9_SHIFT) +#define GPIO_DIR_9_VALUE_INPUT 0U +#define GPIO_DIR_9_BITS_INPUT (GPIO_DIR_9_VALUE_INPUT << GPIO_DIR_9_SHIFT) +#define GPIO_DIR_9_VALUE_OUTPUT 1U +#define GPIO_DIR_9_BITS_OUTPUT (GPIO_DIR_9_VALUE_OUTPUT << GPIO_DIR_9_SHIFT) -#define GPIO_DIR_10_SHIFT 10 -#define GPIO_DIR_10_WIDTH 1 -#define GPIO_DIR_10_MASK (((1U << GPIO_DIR_10_WIDTH) - 1U) << GPIO_DIR_10_SHIFT) -#define GPIO_DIR_10_INPUT (0U << GPIO_DIR_10_SHIFT) -#define GPIO_DIR_10_OUTPUT (1U << GPIO_DIR_10_SHIFT) +#define GPIO_DIR_10_SHIFT 10 +#define GPIO_DIR_10_WIDTH 1 +#define GPIO_DIR_10_MASK (((1U << GPIO_DIR_10_WIDTH) - 1U) << GPIO_DIR_10_SHIFT) +#define GPIO_DIR_10_VALUE_INPUT 0U +#define GPIO_DIR_10_BITS_INPUT (GPIO_DIR_10_VALUE_INPUT << GPIO_DIR_10_SHIFT) +#define GPIO_DIR_10_VALUE_OUTPUT 1U +#define GPIO_DIR_10_BITS_OUTPUT (GPIO_DIR_10_VALUE_OUTPUT << GPIO_DIR_10_SHIFT) -#define GPIO_DIR_11_SHIFT 11 -#define GPIO_DIR_11_WIDTH 1 -#define GPIO_DIR_11_MASK (((1U << GPIO_DIR_11_WIDTH) - 1U) << GPIO_DIR_11_SHIFT) -#define GPIO_DIR_11_INPUT (0U << GPIO_DIR_11_SHIFT) -#define GPIO_DIR_11_OUTPUT (1U << GPIO_DIR_11_SHIFT) +#define GPIO_DIR_11_SHIFT 11 +#define GPIO_DIR_11_WIDTH 1 +#define GPIO_DIR_11_MASK (((1U << GPIO_DIR_11_WIDTH) - 1U) << GPIO_DIR_11_SHIFT) +#define GPIO_DIR_11_VALUE_INPUT 0U +#define GPIO_DIR_11_BITS_INPUT (GPIO_DIR_11_VALUE_INPUT << GPIO_DIR_11_SHIFT) +#define GPIO_DIR_11_VALUE_OUTPUT 1U +#define GPIO_DIR_11_BITS_OUTPUT (GPIO_DIR_11_VALUE_OUTPUT << GPIO_DIR_11_SHIFT) -#define GPIO_DIR_12_SHIFT 12 -#define GPIO_DIR_12_WIDTH 1 -#define GPIO_DIR_12_MASK (((1U << GPIO_DIR_12_WIDTH) - 1U) << GPIO_DIR_12_SHIFT) -#define GPIO_DIR_12_INPUT (0U << GPIO_DIR_12_SHIFT) -#define GPIO_DIR_12_OUTPUT (1U << GPIO_DIR_12_SHIFT) +#define GPIO_DIR_12_SHIFT 12 +#define GPIO_DIR_12_WIDTH 1 +#define GPIO_DIR_12_MASK (((1U << GPIO_DIR_12_WIDTH) - 1U) << GPIO_DIR_12_SHIFT) +#define GPIO_DIR_12_VALUE_INPUT 0U +#define GPIO_DIR_12_BITS_INPUT (GPIO_DIR_12_VALUE_INPUT << GPIO_DIR_12_SHIFT) +#define GPIO_DIR_12_VALUE_OUTPUT 1U +#define GPIO_DIR_12_BITS_OUTPUT (GPIO_DIR_12_VALUE_OUTPUT << GPIO_DIR_12_SHIFT) -#define GPIO_DIR_13_SHIFT 13 -#define GPIO_DIR_13_WIDTH 1 -#define GPIO_DIR_13_MASK (((1U << GPIO_DIR_13_WIDTH) - 1U) << GPIO_DIR_13_SHIFT) -#define GPIO_DIR_13_INPUT (0U << GPIO_DIR_13_SHIFT) -#define GPIO_DIR_13_OUTPUT (1U << GPIO_DIR_13_SHIFT) +#define GPIO_DIR_13_SHIFT 13 +#define GPIO_DIR_13_WIDTH 1 +#define GPIO_DIR_13_MASK (((1U << GPIO_DIR_13_WIDTH) - 1U) << GPIO_DIR_13_SHIFT) +#define GPIO_DIR_13_VALUE_INPUT 0U +#define GPIO_DIR_13_BITS_INPUT (GPIO_DIR_13_VALUE_INPUT << GPIO_DIR_13_SHIFT) +#define GPIO_DIR_13_VALUE_OUTPUT 1U +#define GPIO_DIR_13_BITS_OUTPUT (GPIO_DIR_13_VALUE_OUTPUT << GPIO_DIR_13_SHIFT) -#define GPIO_DIR_14_SHIFT 14 -#define GPIO_DIR_14_WIDTH 1 -#define GPIO_DIR_14_MASK (((1U << GPIO_DIR_14_WIDTH) - 1U) << GPIO_DIR_14_SHIFT) -#define GPIO_DIR_14_INPUT (0U << GPIO_DIR_14_SHIFT) -#define GPIO_DIR_14_OUTPUT (1U << GPIO_DIR_14_SHIFT) +#define GPIO_DIR_14_SHIFT 14 +#define GPIO_DIR_14_WIDTH 1 +#define GPIO_DIR_14_MASK (((1U << GPIO_DIR_14_WIDTH) - 1U) << GPIO_DIR_14_SHIFT) +#define GPIO_DIR_14_VALUE_INPUT 0U +#define GPIO_DIR_14_BITS_INPUT (GPIO_DIR_14_VALUE_INPUT << GPIO_DIR_14_SHIFT) +#define GPIO_DIR_14_VALUE_OUTPUT 1U +#define GPIO_DIR_14_BITS_OUTPUT (GPIO_DIR_14_VALUE_OUTPUT << GPIO_DIR_14_SHIFT) -#define GPIO_DIR_15_SHIFT 15 -#define GPIO_DIR_15_WIDTH 1 -#define GPIO_DIR_15_MASK (((1U << GPIO_DIR_15_WIDTH) - 1U) << GPIO_DIR_15_SHIFT) -#define GPIO_DIR_15_INPUT (0U << GPIO_DIR_15_SHIFT) -#define GPIO_DIR_15_OUTPUT (1U << GPIO_DIR_15_SHIFT) +#define GPIO_DIR_15_SHIFT 15 +#define GPIO_DIR_15_WIDTH 1 +#define GPIO_DIR_15_MASK (((1U << GPIO_DIR_15_WIDTH) - 1U) << GPIO_DIR_15_SHIFT) +#define GPIO_DIR_15_VALUE_INPUT 0U +#define GPIO_DIR_15_BITS_INPUT (GPIO_DIR_15_VALUE_INPUT << GPIO_DIR_15_SHIFT) +#define GPIO_DIR_15_VALUE_OUTPUT 1U +#define GPIO_DIR_15_BITS_OUTPUT (GPIO_DIR_15_VALUE_OUTPUT << GPIO_DIR_15_SHIFT) #endif diff --git a/bsp/dp32g030/pmu.h b/bsp/dp32g030/pmu.h index f51965a..91a1df7 100644 --- a/bsp/dp32g030/pmu.h +++ b/bsp/dp32g030/pmu.h @@ -22,33 +22,35 @@ #endif /* -------- PMU -------- */ -#define PMU_BASE_ADDR 0x40000800U -#define PMU_BASE_SIZE 0x00000800U +#define PMU_BASE_ADDR 0x40000800U +#define PMU_BASE_SIZE 0x00000800U -#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U) -#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR) -#define PMU_SRC_CFG_RTC_CLK_SEL_SHIFT 4 -#define PMU_SRC_CFG_RTC_CLK_SEL_WIDTH 1 -#define PMU_SRC_CFG_RTC_CLK_SEL_MASK (((1U << PMU_SRC_CFG_RTC_CLK_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT) -#define PMU_SRC_CFG_RTC_CLK_SEL_RCLF (0U << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT) -#define PMU_SRC_CFG_RTC_CLK_SEL_XTAL (1U << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT) +#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U) +#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR) +#define PMU_SRC_CFG_RTC_CLK_SEL_SHIFT 4 +#define PMU_SRC_CFG_RTC_CLK_SEL_WIDTH 1 +#define PMU_SRC_CFG_RTC_CLK_SEL_MASK (((1U << PMU_SRC_CFG_RTC_CLK_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT) +#define PMU_SRC_CFG_RTC_CLK_SEL_VALUE_RCLF 0U +#define PMU_SRC_CFG_RTC_CLK_SEL_BITS_RCLF (PMU_SRC_CFG_RTC_CLK_SEL_VALUE_RCLF << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT) +#define PMU_SRC_CFG_RTC_CLK_SEL_VALUE_XTAL 1U +#define PMU_SRC_CFG_RTC_CLK_SEL_BITS_XTAL (PMU_SRC_CFG_RTC_CLK_SEL_VALUE_XTAL << PMU_SRC_CFG_RTC_CLK_SEL_SHIFT) -#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U) -#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR) -#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U) -#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR) -#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U) -#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR) -#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU) -#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR) -#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U) -#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR) -#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U) -#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR) -#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U) -#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR) -#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU) -#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR) +#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U) +#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR) +#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U) +#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR) +#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U) +#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR) +#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU) +#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR) +#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U) +#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR) +#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U) +#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR) +#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U) +#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR) +#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU) +#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR) #endif diff --git a/bsp/dp32g030/portcon.h b/bsp/dp32g030/portcon.h index 36d495c..d77507b 100644 --- a/bsp/dp32g030/portcon.h +++ b/bsp/dp32g030/portcon.h @@ -22,1561 +22,2152 @@ #endif /* -------- PORTCON -------- */ -#define PORTCON_BASE_ADDR 0x400B0000U -#define PORTCON_BASE_SIZE 0x00000800U - -#define PORTCON_PORTA_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0000U) -#define PORTCON_PORTA_SEL0 (*(volatile uint32_t *)PORTCON_PORTA_SEL0_ADDR) -#define PORTCON_PORTA_SEL0_A0_SHIFT 0 -#define PORTCON_PORTA_SEL0_A0_WIDTH 4 -#define PORTCON_PORTA_SEL0_A0_MASK (((1U << PORTCON_PORTA_SEL0_A0_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_GPIOA0 (0U << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_PWMP1_PLUS0 (1U << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_PWMP0_PLUS1 (2U << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_TM (3U << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_WAKEUP0 (4U << PORTCON_PORTA_SEL0_A0_SHIFT) - -#define PORTCON_PORTA_SEL0_A1_SHIFT 4 -#define PORTCON_PORTA_SEL0_A1_WIDTH 4 -#define PORTCON_PORTA_SEL0_A1_MASK (((1U << PORTCON_PORTA_SEL0_A1_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A1_SHIFT) -#define PORTCON_PORTA_SEL0_A1_GPIOA1 (0U << PORTCON_PORTA_SEL0_A1_SHIFT) -#define PORTCON_PORTA_SEL0_A1_XTAL_XI (1U << PORTCON_PORTA_SEL0_A1_SHIFT) - -#define PORTCON_PORTA_SEL0_A2_SHIFT 8 -#define PORTCON_PORTA_SEL0_A2_WIDTH 4 -#define PORTCON_PORTA_SEL0_A2_MASK (((1U << PORTCON_PORTA_SEL0_A2_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A2_SHIFT) -#define PORTCON_PORTA_SEL0_A2_GPIOA2 (0U << PORTCON_PORTA_SEL0_A2_SHIFT) -#define PORTCON_PORTA_SEL0_A2_XTAL_XO (1U << PORTCON_PORTA_SEL0_A2_SHIFT) - -#define PORTCON_PORTA_SEL0_A3_SHIFT 12 -#define PORTCON_PORTA_SEL0_A3_WIDTH 4 -#define PORTCON_PORTA_SEL0_A3_MASK (((1U << PORTCON_PORTA_SEL0_A3_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A3_SHIFT) -#define PORTCON_PORTA_SEL0_A3_GPIOA3 (0U << PORTCON_PORTA_SEL0_A3_SHIFT) -#define PORTCON_PORTA_SEL0_A3_CMP0_VN (1U << PORTCON_PORTA_SEL0_A3_SHIFT) -#define PORTCON_PORTA_SEL0_A3_XTAH_XI (2U << PORTCON_PORTA_SEL0_A3_SHIFT) - -#define PORTCON_PORTA_SEL0_A4_SHIFT 16 -#define PORTCON_PORTA_SEL0_A4_WIDTH 4 -#define PORTCON_PORTA_SEL0_A4_MASK (((1U << PORTCON_PORTA_SEL0_A4_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A4_SHIFT) -#define PORTCON_PORTA_SEL0_A4_GPIOA4 (0U << PORTCON_PORTA_SEL0_A4_SHIFT) -#define PORTCON_PORTA_SEL0_A4_CMP0_VP (1U << PORTCON_PORTA_SEL0_A4_SHIFT) -#define PORTCON_PORTA_SEL0_A4_XTAH_XO (2U << PORTCON_PORTA_SEL0_A4_SHIFT) - -#define PORTCON_PORTA_SEL0_A5_SHIFT 20 -#define PORTCON_PORTA_SEL0_A5_WIDTH 4 -#define PORTCON_PORTA_SEL0_A5_MASK (((1U << PORTCON_PORTA_SEL0_A5_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_GPIOA5 (0U << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_UART1_CTS (1U << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_PWMP1_PLUS1 (2U << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_TIMERP1_IN0 (3U << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_TIMERP1_OUT_L (4U << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_WAKEUP1 (5U << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_SARADC_CH1 (6U << PORTCON_PORTA_SEL0_A5_SHIFT) - -#define PORTCON_PORTA_SEL0_A6_SHIFT 24 -#define PORTCON_PORTA_SEL0_A6_WIDTH 4 -#define PORTCON_PORTA_SEL0_A6_MASK (((1U << PORTCON_PORTA_SEL0_A6_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_GPIOA6 (0U << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_UART1_RTS (1U << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_TIMERP1_IN1 (2U << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_TIMERP1_OUT_H (3U << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_SARADC_CH1 (4U << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_OPA0_OUT (5U << PORTCON_PORTA_SEL0_A6_SHIFT) - -#define PORTCON_PORTA_SEL0_A7_SHIFT 28 -#define PORTCON_PORTA_SEL0_A7_WIDTH 4 -#define PORTCON_PORTA_SEL0_A7_MASK (((1U << PORTCON_PORTA_SEL0_A7_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_GPIOA7 (0U << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_UART1_TX (1U << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_TIMERP0_IN0 (2U << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_TIMERP0_OUT_L (3U << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_SARADC_CH2 (4U << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_OPA0_VP (5U << PORTCON_PORTA_SEL0_A7_SHIFT) - -#define PORTCON_PORTA_SEL1_ADDR (PORTCON_BASE_ADDR + 0x0004U) -#define PORTCON_PORTA_SEL1 (*(volatile uint32_t *)PORTCON_PORTA_SEL1_ADDR) -#define PORTCON_PORTA_SEL1_A8_SHIFT 0 -#define PORTCON_PORTA_SEL1_A8_WIDTH 4 -#define PORTCON_PORTA_SEL1_A8_MASK (((1U << PORTCON_PORTA_SEL1_A8_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_GPIOA8 (0U << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_UART1_RX (1U << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_TIMERP0_IN1 (2U << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_TIMERP0_OUT_H (3U << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_SARADC_CH3 (4U << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_OPA0_VN (5U << PORTCON_PORTA_SEL1_A8_SHIFT) - -#define PORTCON_PORTA_SEL1_A9_SHIFT 4 -#define PORTCON_PORTA_SEL1_A9_WIDTH 4 -#define PORTCON_PORTA_SEL1_A9_MASK (((1U << PORTCON_PORTA_SEL1_A9_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_GPIOA9 (0U << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_SPI0_SSN (1U << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_TIMERP1_IN0 (2U << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_TIMERP1_OUT_L (3U << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_TM (4U << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_SARADC_CH4 (5U << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_CMP1_VN (6U << PORTCON_PORTA_SEL1_A9_SHIFT) - -#define PORTCON_PORTA_SEL1_A10_SHIFT 8 -#define PORTCON_PORTA_SEL1_A10_WIDTH 4 -#define PORTCON_PORTA_SEL1_A10_MASK (((1U << PORTCON_PORTA_SEL1_A10_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_GPIOA10 (0U << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_SPI0_CLK (1U << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_SARADC_CH5 (2U << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_CMP1_VP (3U << PORTCON_PORTA_SEL1_A10_SHIFT) - -#define PORTCON_PORTA_SEL1_A11_SHIFT 12 -#define PORTCON_PORTA_SEL1_A11_WIDTH 4 -#define PORTCON_PORTA_SEL1_A11_MASK (((1U << PORTCON_PORTA_SEL1_A11_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_GPIOA11 (0U << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_SPI0_MISO (1U << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_PWMB0_CH0 (2U << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_PWMP0_BRAKE0 (3U << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_TIMERP1_IN1 (4U << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_TIMERP1_OUT_H (5U << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_SARADC_CH6 (6U << PORTCON_PORTA_SEL1_A11_SHIFT) - -#define PORTCON_PORTA_SEL1_A12_SHIFT 16 -#define PORTCON_PORTA_SEL1_A12_WIDTH 4 -#define PORTCON_PORTA_SEL1_A12_MASK (((1U << PORTCON_PORTA_SEL1_A12_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_GPIOA12 (0U << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_SPI0_MOSI (1U << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_PWMB0_CH1 (2U << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_PWMP0_CH0N (3U << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_TIMERP0_IN0 (4U << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_TIMERP0_OUT_L (5U << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_SARADC_CH7 (6U << PORTCON_PORTA_SEL1_A12_SHIFT) - -#define PORTCON_PORTA_SEL1_A13_SHIFT 20 -#define PORTCON_PORTA_SEL1_A13_WIDTH 4 -#define PORTCON_PORTA_SEL1_A13_MASK (((1U << PORTCON_PORTA_SEL1_A13_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_GPIOA13 (0U << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_PWMB0_CH2 (1U << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_PWMP0_CH1N (2U << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_TIMERP0_IN1 (3U << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_TIMERP0_OUT_H (4U << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_SARADC_CH8 (5U << PORTCON_PORTA_SEL1_A13_SHIFT) - -#define PORTCON_PORTA_SEL1_A14_SHIFT 24 -#define PORTCON_PORTA_SEL1_A14_WIDTH 4 -#define PORTCON_PORTA_SEL1_A14_MASK (((1U << PORTCON_PORTA_SEL1_A14_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_GPIOA14 (0U << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_PWMB1_CH0 (1U << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_PWMP0_CH2N (2U << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_TIMERP1_IN0 (3U << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_TIMERP1_OUT_L (4U << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_SARADC_CH9 (5U << PORTCON_PORTA_SEL1_A14_SHIFT) - -#define PORTCON_PORTA_SEL1_A15_SHIFT 28 -#define PORTCON_PORTA_SEL1_A15_WIDTH 4 -#define PORTCON_PORTA_SEL1_A15_MASK (((1U << PORTCON_PORTA_SEL1_A15_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_GPIOA15 (0U << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_PWMB1_CH1 (1U << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_PWMP0_CH0 (2U << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_TIMERP1_IN1 (3U << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_TIMERP1_OUT_H (4U << PORTCON_PORTA_SEL1_A15_SHIFT) - -#define PORTCON_PORTB_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0008U) -#define PORTCON_PORTB_SEL0 (*(volatile uint32_t *)PORTCON_PORTB_SEL0_ADDR) -#define PORTCON_PORTB_SEL0_B0_SHIFT 0 -#define PORTCON_PORTB_SEL0_B0_WIDTH 4 -#define PORTCON_PORTB_SEL0_B0_MASK (((1U << PORTCON_PORTB_SEL0_B0_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_GPIOB0 (0U << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_UART2_TX (1U << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_IIC0_SCL (2U << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_PWMB1_CH2 (3U << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_PWMP0_CH1 (4U << PORTCON_PORTB_SEL0_B0_SHIFT) - -#define PORTCON_PORTB_SEL0_B1_SHIFT 4 -#define PORTCON_PORTB_SEL0_B1_WIDTH 4 -#define PORTCON_PORTB_SEL0_B1_MASK (((1U << PORTCON_PORTB_SEL0_B1_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_GPIOB1 (0U << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_UART2_RX (1U << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_IIC0_SDA (2U << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_PWMP0_CH2 (3U << PORTCON_PORTB_SEL0_B1_SHIFT) - -#define PORTCON_PORTB_SEL0_B2_SHIFT 8 -#define PORTCON_PORTB_SEL0_B2_WIDTH 4 -#define PORTCON_PORTB_SEL0_B2_MASK (((1U << PORTCON_PORTB_SEL0_B2_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_GPIOB2 (0U << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_SPI1_SSN (1U << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_PWMP0_BRAKE1 (2U << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_TIMERP1_HALL0 (3U << PORTCON_PORTB_SEL0_B2_SHIFT) - -#define PORTCON_PORTB_SEL0_B3_SHIFT 12 -#define PORTCON_PORTB_SEL0_B3_WIDTH 4 -#define PORTCON_PORTB_SEL0_B3_MASK (((1U << PORTCON_PORTB_SEL0_B3_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_GPIOB3 (0U << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_SPI1_CLK (1U << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_IIC1_SDA (2U << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_PWMP0_CH0N (3U << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_TIMERP1_HALL1 (4U << PORTCON_PORTB_SEL0_B3_SHIFT) - -#define PORTCON_PORTB_SEL0_B4_SHIFT 16 -#define PORTCON_PORTB_SEL0_B4_WIDTH 4 -#define PORTCON_PORTB_SEL0_B4_MASK (((1U << PORTCON_PORTB_SEL0_B4_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_GPIOB4 (0U << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_SPI1_MISO (1U << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_IIC1_SCL (2U << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_PWMP1_CH0 (3U << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_PWMP0_CH1N (4U << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_TIMERP1_HALL2 (5U << PORTCON_PORTB_SEL0_B4_SHIFT) - -#define PORTCON_PORTB_SEL0_B5_SHIFT 20 -#define PORTCON_PORTB_SEL0_B5_WIDTH 4 -#define PORTCON_PORTB_SEL0_B5_MASK (((1U << PORTCON_PORTB_SEL0_B5_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_GPIOB5 (0U << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_SPI1_MOSI (1U << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_PWMP1_CH0N (2U << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_PWMP0_CH2N (3U << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_TIMERP0_IN0 (4U << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_TIMERP0_OUT_L (5U << PORTCON_PORTB_SEL0_B5_SHIFT) - -#define PORTCON_PORTB_SEL0_B6_SHIFT 24 -#define PORTCON_PORTB_SEL0_B6_WIDTH 4 -#define PORTCON_PORTB_SEL0_B6_MASK (((1U << PORTCON_PORTB_SEL0_B6_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_GPIOB6 (0U << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_PWMP0_CH0 (1U << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_TIMERP0_IN1 (2U << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_TIMERP0_OUT_H (3U << PORTCON_PORTB_SEL0_B6_SHIFT) - -#define PORTCON_PORTB_SEL0_B7_SHIFT 28 -#define PORTCON_PORTB_SEL0_B7_WIDTH 4 -#define PORTCON_PORTB_SEL0_B7_MASK (((1U << PORTCON_PORTB_SEL0_B7_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_GPIOB7 (0U << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_SPI0_SSN (1U << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_UART0_TX (2U << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_IIC0_SCL (3U << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_PWMP1_BRAKE0 (4U << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_PWMP0_CH1 (5U << PORTCON_PORTB_SEL0_B7_SHIFT) - -#define PORTCON_PORTB_SEL1_ADDR (PORTCON_BASE_ADDR + 0x000CU) -#define PORTCON_PORTB_SEL1 (*(volatile uint32_t *)PORTCON_PORTB_SEL1_ADDR) -#define PORTCON_PORTB_SEL1_B8_SHIFT 0 -#define PORTCON_PORTB_SEL1_B8_WIDTH 4 -#define PORTCON_PORTB_SEL1_B8_MASK (((1U << PORTCON_PORTB_SEL1_B8_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_GPIOB8 (0U << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_SPI0_CLK (1U << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_UART0_RX (2U << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_IIC0_SDA (3U << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_PWMB0_CH0 (4U << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_PWMP1_BRAKE1 (5U << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_PWMP0_CH2 (6U << PORTCON_PORTB_SEL1_B8_SHIFT) - -#define PORTCON_PORTB_SEL1_B9_SHIFT 4 -#define PORTCON_PORTB_SEL1_B9_WIDTH 4 -#define PORTCON_PORTB_SEL1_B9_MASK (((1U << PORTCON_PORTB_SEL1_B9_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_GPIOB9 (0U << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_SPI0_MISO (1U << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_UART0_CTS (2U << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_PWMB0_CH1 (3U << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_PWMP1_CH0 (4U << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_TIMERP1_IN1 (5U << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_TIMERP1_OUT_H (6U << PORTCON_PORTB_SEL1_B9_SHIFT) - -#define PORTCON_PORTB_SEL1_B10_SHIFT 8 -#define PORTCON_PORTB_SEL1_B10_WIDTH 4 -#define PORTCON_PORTB_SEL1_B10_MASK (((1U << PORTCON_PORTB_SEL1_B10_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_GPIOB10 (0U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_SPI0_MOSI (1U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_UART0_RTS (2U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_PWMB0_CH2 (3U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_PWMP1_CH1 (4U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_PWMP0_PLUS0 (5U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_TIMERP1_IN0 (6U << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_TIMERP1_OUT_L (7U << PORTCON_PORTB_SEL1_B10_SHIFT) - -#define PORTCON_PORTB_SEL1_B11_SHIFT 12 -#define PORTCON_PORTB_SEL1_B11_WIDTH 4 -#define PORTCON_PORTB_SEL1_B11_MASK (((1U << PORTCON_PORTB_SEL1_B11_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_GPIOB11 (0U << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_SWDIO (1U << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_PWMP1_CH2 (2U << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_PWMP0_BRAKE2 (3U << PORTCON_PORTB_SEL1_B11_SHIFT) - -#define PORTCON_PORTB_SEL1_B12_SHIFT 16 -#define PORTCON_PORTB_SEL1_B12_WIDTH 4 -#define PORTCON_PORTB_SEL1_B12_MASK (((1U << PORTCON_PORTB_SEL1_B12_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_GPIOB12 (0U << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_UART1_TX (1U << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_IIC1_SCL (2U << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_PWMP1_CH0N (3U << PORTCON_PORTB_SEL1_B12_SHIFT) - -#define PORTCON_PORTB_SEL1_B13_SHIFT 20 -#define PORTCON_PORTB_SEL1_B13_WIDTH 4 -#define PORTCON_PORTB_SEL1_B13_MASK (((1U << PORTCON_PORTB_SEL1_B13_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_GPIOB13 (0U << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_UART1_RX (1U << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_IIC1_SDA (2U << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_PWMP1_CH1N (3U << PORTCON_PORTB_SEL1_B13_SHIFT) - -#define PORTCON_PORTB_SEL1_B14_SHIFT 24 -#define PORTCON_PORTB_SEL1_B14_WIDTH 4 -#define PORTCON_PORTB_SEL1_B14_MASK (((1U << PORTCON_PORTB_SEL1_B14_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_GPIOB14 (0U << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_SWCLK (1U << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_UART2_TX (2U << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_PWMP1_CH2N (3U << PORTCON_PORTB_SEL1_B14_SHIFT) - -#define PORTCON_PORTB_SEL1_B15_SHIFT 28 -#define PORTCON_PORTB_SEL1_B15_WIDTH 4 -#define PORTCON_PORTB_SEL1_B15_MASK (((1U << PORTCON_PORTB_SEL1_B15_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B15_SHIFT) -#define PORTCON_PORTB_SEL1_B15_GPIOB15 (0U << PORTCON_PORTB_SEL1_B15_SHIFT) -#define PORTCON_PORTB_SEL1_B15_SPI1_SSN (1U << PORTCON_PORTB_SEL1_B15_SHIFT) -#define PORTCON_PORTB_SEL1_B15_UART2_RX (2U << PORTCON_PORTB_SEL1_B15_SHIFT) - -#define PORTCON_PORTC_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0010U) -#define PORTCON_PORTC_SEL0 (*(volatile uint32_t *)PORTCON_PORTC_SEL0_ADDR) -#define PORTCON_PORTC_SEL0_C0_SHIFT 0 -#define PORTCON_PORTC_SEL0_C0_WIDTH 4 -#define PORTCON_PORTC_SEL0_C0_MASK (((1U << PORTCON_PORTC_SEL0_C0_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_GPIOC0 (0U << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_SPI1_CLK (1U << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_UART2_CTS (2U << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_PWMB1_CH0 (3U << PORTCON_PORTC_SEL0_C0_SHIFT) - -#define PORTCON_PORTC_SEL0_C1_SHIFT 4 -#define PORTCON_PORTC_SEL0_C1_WIDTH 4 -#define PORTCON_PORTC_SEL0_C1_MASK (((1U << PORTCON_PORTC_SEL0_C1_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_GPIOC1 (0U << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_SPI1_MISO (1U << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_UART2_RTS (2U << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_PWMB1_CH1 (3U << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_TIMERP0_IN0 (4U << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_TIMERP0_OUT_L (5U << PORTCON_PORTC_SEL0_C1_SHIFT) - -#define PORTCON_PORTC_SEL0_C2_SHIFT 8 -#define PORTCON_PORTC_SEL0_C2_WIDTH 4 -#define PORTCON_PORTC_SEL0_C2_MASK (((1U << PORTCON_PORTC_SEL0_C2_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_GPIOC2 (0U << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_SPI1_MOSI (1U << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_PWMB1_CH2 (2U << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_PWMP1_BRAKE2 (3U << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_TIMERP0_IN1 (4U << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_TIMERP0_OUT_H (5U << PORTCON_PORTC_SEL0_C2_SHIFT) - -#define PORTCON_PORTC_SEL0_C3_SHIFT 12 -#define PORTCON_PORTC_SEL0_C3_WIDTH 4 -#define PORTCON_PORTC_SEL0_C3_MASK (((1U << PORTCON_PORTC_SEL0_C3_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_GPIOC3 (0U << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_UART0_TX (1U << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_IIC0_SCL (2U << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_PWMP1_CH1N (3U << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_TIMERP0_HALL0 (4U << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_CMP2_VN (5U << PORTCON_PORTC_SEL0_C3_SHIFT) - -#define PORTCON_PORTC_SEL0_C4_SHIFT 16 -#define PORTCON_PORTC_SEL0_C4_WIDTH 4 -#define PORTCON_PORTC_SEL0_C4_MASK (((1U << PORTCON_PORTC_SEL0_C4_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_GPIOC4 (0U << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_UART0_RX (1U << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_IIC0_SDA (2U << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_PWMP1_CH2N (3U << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_TIMERP0_HALL1 (4U << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_CMP2_VP (5U << PORTCON_PORTC_SEL0_C4_SHIFT) - -#define PORTCON_PORTC_SEL0_C5_SHIFT 20 -#define PORTCON_PORTC_SEL0_C5_WIDTH 4 -#define PORTCON_PORTC_SEL0_C5_MASK (((1U << PORTCON_PORTC_SEL0_C5_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_GPIOC5 (0U << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_TIMERP0_HALL2 (1U << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_TM (2U << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_OPA1_VP (3U << PORTCON_PORTC_SEL0_C5_SHIFT) - -#define PORTCON_PORTC_SEL0_C6_SHIFT 24 -#define PORTCON_PORTC_SEL0_C6_WIDTH 4 -#define PORTCON_PORTC_SEL0_C6_MASK (((1U << PORTCON_PORTC_SEL0_C6_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_GPIOC6 (0U << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_IIC1_SCL (1U << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_PWMP1_CH1 (2U << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_TIMERP1_IN1 (3U << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_TIMERP1_OUT_H (4U << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_OPA1_VN (5U << PORTCON_PORTC_SEL0_C6_SHIFT) - -#define PORTCON_PORTC_SEL0_C7_SHIFT 28 -#define PORTCON_PORTC_SEL0_C7_WIDTH 4 -#define PORTCON_PORTC_SEL0_C7_MASK (((1U << PORTCON_PORTC_SEL0_C7_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_GPIOC7 (0U << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_IIC1_SDA (1U << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_PWMP1_CH2 (2U << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_TIMERP1_IN0 (3U << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_TIMERP1_OUT_L (4U << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_OPA1_OUT (5U << PORTCON_PORTC_SEL0_C7_SHIFT) - -#define PORTCON_PORTA_IE_ADDR (PORTCON_BASE_ADDR + 0x0100U) -#define PORTCON_PORTA_IE (*(volatile uint32_t *)PORTCON_PORTA_IE_ADDR) -#define PORTCON_PORTA_IE_A0_SHIFT 0 -#define PORTCON_PORTA_IE_A0_WIDTH 1 -#define PORTCON_PORTA_IE_A0_MASK (((1U << PORTCON_PORTA_IE_A0_WIDTH) - 1U) << PORTCON_PORTA_IE_A0_SHIFT) -#define PORTCON_PORTA_IE_A0_DISABLE (0U << PORTCON_PORTA_IE_A0_SHIFT) -#define PORTCON_PORTA_IE_A0_ENABLE (1U << PORTCON_PORTA_IE_A0_SHIFT) - -#define PORTCON_PORTA_IE_A1_SHIFT 1 -#define PORTCON_PORTA_IE_A1_WIDTH 1 -#define PORTCON_PORTA_IE_A1_MASK (((1U << PORTCON_PORTA_IE_A1_WIDTH) - 1U) << PORTCON_PORTA_IE_A1_SHIFT) -#define PORTCON_PORTA_IE_A1_DISABLE (0U << PORTCON_PORTA_IE_A1_SHIFT) -#define PORTCON_PORTA_IE_A1_ENABLE (1U << PORTCON_PORTA_IE_A1_SHIFT) - -#define PORTCON_PORTA_IE_A2_SHIFT 2 -#define PORTCON_PORTA_IE_A2_WIDTH 1 -#define PORTCON_PORTA_IE_A2_MASK (((1U << PORTCON_PORTA_IE_A2_WIDTH) - 1U) << PORTCON_PORTA_IE_A2_SHIFT) -#define PORTCON_PORTA_IE_A2_DISABLE (0U << PORTCON_PORTA_IE_A2_SHIFT) -#define PORTCON_PORTA_IE_A2_ENABLE (1U << PORTCON_PORTA_IE_A2_SHIFT) - -#define PORTCON_PORTA_IE_A3_SHIFT 3 -#define PORTCON_PORTA_IE_A3_WIDTH 1 -#define PORTCON_PORTA_IE_A3_MASK (((1U << PORTCON_PORTA_IE_A3_WIDTH) - 1U) << PORTCON_PORTA_IE_A3_SHIFT) -#define PORTCON_PORTA_IE_A3_DISABLE (0U << PORTCON_PORTA_IE_A3_SHIFT) -#define PORTCON_PORTA_IE_A3_ENABLE (1U << PORTCON_PORTA_IE_A3_SHIFT) - -#define PORTCON_PORTA_IE_A4_SHIFT 4 -#define PORTCON_PORTA_IE_A4_WIDTH 1 -#define PORTCON_PORTA_IE_A4_MASK (((1U << PORTCON_PORTA_IE_A4_WIDTH) - 1U) << PORTCON_PORTA_IE_A4_SHIFT) -#define PORTCON_PORTA_IE_A4_DISABLE (0U << PORTCON_PORTA_IE_A4_SHIFT) -#define PORTCON_PORTA_IE_A4_ENABLE (1U << PORTCON_PORTA_IE_A4_SHIFT) - -#define PORTCON_PORTA_IE_A5_SHIFT 5 -#define PORTCON_PORTA_IE_A5_WIDTH 1 -#define PORTCON_PORTA_IE_A5_MASK (((1U << PORTCON_PORTA_IE_A5_WIDTH) - 1U) << PORTCON_PORTA_IE_A5_SHIFT) -#define PORTCON_PORTA_IE_A5_DISABLE (0U << PORTCON_PORTA_IE_A5_SHIFT) -#define PORTCON_PORTA_IE_A5_ENABLE (1U << PORTCON_PORTA_IE_A5_SHIFT) - -#define PORTCON_PORTA_IE_A6_SHIFT 6 -#define PORTCON_PORTA_IE_A6_WIDTH 1 -#define PORTCON_PORTA_IE_A6_MASK (((1U << PORTCON_PORTA_IE_A6_WIDTH) - 1U) << PORTCON_PORTA_IE_A6_SHIFT) -#define PORTCON_PORTA_IE_A6_DISABLE (0U << PORTCON_PORTA_IE_A6_SHIFT) -#define PORTCON_PORTA_IE_A6_ENABLE (1U << PORTCON_PORTA_IE_A6_SHIFT) - -#define PORTCON_PORTA_IE_A7_SHIFT 7 -#define PORTCON_PORTA_IE_A7_WIDTH 1 -#define PORTCON_PORTA_IE_A7_MASK (((1U << PORTCON_PORTA_IE_A7_WIDTH) - 1U) << PORTCON_PORTA_IE_A7_SHIFT) -#define PORTCON_PORTA_IE_A7_DISABLE (0U << PORTCON_PORTA_IE_A7_SHIFT) -#define PORTCON_PORTA_IE_A7_ENABLE (1U << PORTCON_PORTA_IE_A7_SHIFT) - -#define PORTCON_PORTA_IE_A8_SHIFT 8 -#define PORTCON_PORTA_IE_A8_WIDTH 1 -#define PORTCON_PORTA_IE_A8_MASK (((1U << PORTCON_PORTA_IE_A8_WIDTH) - 1U) << PORTCON_PORTA_IE_A8_SHIFT) -#define PORTCON_PORTA_IE_A8_DISABLE (0U << PORTCON_PORTA_IE_A8_SHIFT) -#define PORTCON_PORTA_IE_A8_ENABLE (1U << PORTCON_PORTA_IE_A8_SHIFT) - -#define PORTCON_PORTA_IE_A9_SHIFT 9 -#define PORTCON_PORTA_IE_A9_WIDTH 1 -#define PORTCON_PORTA_IE_A9_MASK (((1U << PORTCON_PORTA_IE_A9_WIDTH) - 1U) << PORTCON_PORTA_IE_A9_SHIFT) -#define PORTCON_PORTA_IE_A9_DISABLE (0U << PORTCON_PORTA_IE_A9_SHIFT) -#define PORTCON_PORTA_IE_A9_ENABLE (1U << PORTCON_PORTA_IE_A9_SHIFT) - -#define PORTCON_PORTA_IE_A10_SHIFT 10 -#define PORTCON_PORTA_IE_A10_WIDTH 1 -#define PORTCON_PORTA_IE_A10_MASK (((1U << PORTCON_PORTA_IE_A10_WIDTH) - 1U) << PORTCON_PORTA_IE_A10_SHIFT) -#define PORTCON_PORTA_IE_A10_DISABLE (0U << PORTCON_PORTA_IE_A10_SHIFT) -#define PORTCON_PORTA_IE_A10_ENABLE (1U << PORTCON_PORTA_IE_A10_SHIFT) - -#define PORTCON_PORTA_IE_A11_SHIFT 11 -#define PORTCON_PORTA_IE_A11_WIDTH 1 -#define PORTCON_PORTA_IE_A11_MASK (((1U << PORTCON_PORTA_IE_A11_WIDTH) - 1U) << PORTCON_PORTA_IE_A11_SHIFT) -#define PORTCON_PORTA_IE_A11_DISABLE (0U << PORTCON_PORTA_IE_A11_SHIFT) -#define PORTCON_PORTA_IE_A11_ENABLE (1U << PORTCON_PORTA_IE_A11_SHIFT) - -#define PORTCON_PORTA_IE_A12_SHIFT 12 -#define PORTCON_PORTA_IE_A12_WIDTH 1 -#define PORTCON_PORTA_IE_A12_MASK (((1U << PORTCON_PORTA_IE_A12_WIDTH) - 1U) << PORTCON_PORTA_IE_A12_SHIFT) -#define PORTCON_PORTA_IE_A12_DISABLE (0U << PORTCON_PORTA_IE_A12_SHIFT) -#define PORTCON_PORTA_IE_A12_ENABLE (1U << PORTCON_PORTA_IE_A12_SHIFT) - -#define PORTCON_PORTA_IE_A13_SHIFT 13 -#define PORTCON_PORTA_IE_A13_WIDTH 1 -#define PORTCON_PORTA_IE_A13_MASK (((1U << PORTCON_PORTA_IE_A13_WIDTH) - 1U) << PORTCON_PORTA_IE_A13_SHIFT) -#define PORTCON_PORTA_IE_A13_DISABLE (0U << PORTCON_PORTA_IE_A13_SHIFT) -#define PORTCON_PORTA_IE_A13_ENABLE (1U << PORTCON_PORTA_IE_A13_SHIFT) - -#define PORTCON_PORTA_IE_A14_SHIFT 14 -#define PORTCON_PORTA_IE_A14_WIDTH 1 -#define PORTCON_PORTA_IE_A14_MASK (((1U << PORTCON_PORTA_IE_A14_WIDTH) - 1U) << PORTCON_PORTA_IE_A14_SHIFT) -#define PORTCON_PORTA_IE_A14_DISABLE (0U << PORTCON_PORTA_IE_A14_SHIFT) -#define PORTCON_PORTA_IE_A14_ENABLE (1U << PORTCON_PORTA_IE_A14_SHIFT) - -#define PORTCON_PORTA_IE_A15_SHIFT 15 -#define PORTCON_PORTA_IE_A15_WIDTH 1 -#define PORTCON_PORTA_IE_A15_MASK (((1U << PORTCON_PORTA_IE_A15_WIDTH) - 1U) << PORTCON_PORTA_IE_A15_SHIFT) -#define PORTCON_PORTA_IE_A15_DISABLE (0U << PORTCON_PORTA_IE_A15_SHIFT) -#define PORTCON_PORTA_IE_A15_ENABLE (1U << PORTCON_PORTA_IE_A15_SHIFT) - -#define PORTCON_PORTB_IE_ADDR (PORTCON_BASE_ADDR + 0x0104U) -#define PORTCON_PORTB_IE (*(volatile uint32_t *)PORTCON_PORTB_IE_ADDR) -#define PORTCON_PORTB_IE_B0_SHIFT 0 -#define PORTCON_PORTB_IE_B0_WIDTH 1 -#define PORTCON_PORTB_IE_B0_MASK (((1U << PORTCON_PORTB_IE_B0_WIDTH) - 1U) << PORTCON_PORTB_IE_B0_SHIFT) -#define PORTCON_PORTB_IE_B0_DISABLE (0U << PORTCON_PORTB_IE_B0_SHIFT) -#define PORTCON_PORTB_IE_B0_ENABLE (1U << PORTCON_PORTB_IE_B0_SHIFT) - -#define PORTCON_PORTB_IE_B1_SHIFT 1 -#define PORTCON_PORTB_IE_B1_WIDTH 1 -#define PORTCON_PORTB_IE_B1_MASK (((1U << PORTCON_PORTB_IE_B1_WIDTH) - 1U) << PORTCON_PORTB_IE_B1_SHIFT) -#define PORTCON_PORTB_IE_B1_DISABLE (0U << PORTCON_PORTB_IE_B1_SHIFT) -#define PORTCON_PORTB_IE_B1_ENABLE (1U << PORTCON_PORTB_IE_B1_SHIFT) - -#define PORTCON_PORTB_IE_B2_SHIFT 2 -#define PORTCON_PORTB_IE_B2_WIDTH 1 -#define PORTCON_PORTB_IE_B2_MASK (((1U << PORTCON_PORTB_IE_B2_WIDTH) - 1U) << PORTCON_PORTB_IE_B2_SHIFT) -#define PORTCON_PORTB_IE_B2_DISABLE (0U << PORTCON_PORTB_IE_B2_SHIFT) -#define PORTCON_PORTB_IE_B2_ENABLE (1U << PORTCON_PORTB_IE_B2_SHIFT) - -#define PORTCON_PORTB_IE_B3_SHIFT 3 -#define PORTCON_PORTB_IE_B3_WIDTH 1 -#define PORTCON_PORTB_IE_B3_MASK (((1U << PORTCON_PORTB_IE_B3_WIDTH) - 1U) << PORTCON_PORTB_IE_B3_SHIFT) -#define PORTCON_PORTB_IE_B3_DISABLE (0U << PORTCON_PORTB_IE_B3_SHIFT) -#define PORTCON_PORTB_IE_B3_ENABLE (1U << PORTCON_PORTB_IE_B3_SHIFT) - -#define PORTCON_PORTB_IE_B4_SHIFT 4 -#define PORTCON_PORTB_IE_B4_WIDTH 1 -#define PORTCON_PORTB_IE_B4_MASK (((1U << PORTCON_PORTB_IE_B4_WIDTH) - 1U) << PORTCON_PORTB_IE_B4_SHIFT) -#define PORTCON_PORTB_IE_B4_DISABLE (0U << PORTCON_PORTB_IE_B4_SHIFT) -#define PORTCON_PORTB_IE_B4_ENABLE (1U << PORTCON_PORTB_IE_B4_SHIFT) - -#define PORTCON_PORTB_IE_B5_SHIFT 5 -#define PORTCON_PORTB_IE_B5_WIDTH 1 -#define PORTCON_PORTB_IE_B5_MASK (((1U << PORTCON_PORTB_IE_B5_WIDTH) - 1U) << PORTCON_PORTB_IE_B5_SHIFT) -#define PORTCON_PORTB_IE_B5_DISABLE (0U << PORTCON_PORTB_IE_B5_SHIFT) -#define PORTCON_PORTB_IE_B5_ENABLE (1U << PORTCON_PORTB_IE_B5_SHIFT) - -#define PORTCON_PORTB_IE_B6_SHIFT 6 -#define PORTCON_PORTB_IE_B6_WIDTH 1 -#define PORTCON_PORTB_IE_B6_MASK (((1U << PORTCON_PORTB_IE_B6_WIDTH) - 1U) << PORTCON_PORTB_IE_B6_SHIFT) -#define PORTCON_PORTB_IE_B6_DISABLE (0U << PORTCON_PORTB_IE_B6_SHIFT) -#define PORTCON_PORTB_IE_B6_ENABLE (1U << PORTCON_PORTB_IE_B6_SHIFT) - -#define PORTCON_PORTB_IE_B7_SHIFT 7 -#define PORTCON_PORTB_IE_B7_WIDTH 1 -#define PORTCON_PORTB_IE_B7_MASK (((1U << PORTCON_PORTB_IE_B7_WIDTH) - 1U) << PORTCON_PORTB_IE_B7_SHIFT) -#define PORTCON_PORTB_IE_B7_DISABLE (0U << PORTCON_PORTB_IE_B7_SHIFT) -#define PORTCON_PORTB_IE_B7_ENABLE (1U << PORTCON_PORTB_IE_B7_SHIFT) - -#define PORTCON_PORTB_IE_B8_SHIFT 8 -#define PORTCON_PORTB_IE_B8_WIDTH 1 -#define PORTCON_PORTB_IE_B8_MASK (((1U << PORTCON_PORTB_IE_B8_WIDTH) - 1U) << PORTCON_PORTB_IE_B8_SHIFT) -#define PORTCON_PORTB_IE_B8_DISABLE (0U << PORTCON_PORTB_IE_B8_SHIFT) -#define PORTCON_PORTB_IE_B8_ENABLE (1U << PORTCON_PORTB_IE_B8_SHIFT) - -#define PORTCON_PORTB_IE_B9_SHIFT 9 -#define PORTCON_PORTB_IE_B9_WIDTH 1 -#define PORTCON_PORTB_IE_B9_MASK (((1U << PORTCON_PORTB_IE_B9_WIDTH) - 1U) << PORTCON_PORTB_IE_B9_SHIFT) -#define PORTCON_PORTB_IE_B9_DISABLE (0U << PORTCON_PORTB_IE_B9_SHIFT) -#define PORTCON_PORTB_IE_B9_ENABLE (1U << PORTCON_PORTB_IE_B9_SHIFT) - -#define PORTCON_PORTB_IE_B10_SHIFT 10 -#define PORTCON_PORTB_IE_B10_WIDTH 1 -#define PORTCON_PORTB_IE_B10_MASK (((1U << PORTCON_PORTB_IE_B10_WIDTH) - 1U) << PORTCON_PORTB_IE_B10_SHIFT) -#define PORTCON_PORTB_IE_B10_DISABLE (0U << PORTCON_PORTB_IE_B10_SHIFT) -#define PORTCON_PORTB_IE_B10_ENABLE (1U << PORTCON_PORTB_IE_B10_SHIFT) - -#define PORTCON_PORTB_IE_B11_SHIFT 11 -#define PORTCON_PORTB_IE_B11_WIDTH 1 -#define PORTCON_PORTB_IE_B11_MASK (((1U << PORTCON_PORTB_IE_B11_WIDTH) - 1U) << PORTCON_PORTB_IE_B11_SHIFT) -#define PORTCON_PORTB_IE_B11_DISABLE (0U << PORTCON_PORTB_IE_B11_SHIFT) -#define PORTCON_PORTB_IE_B11_ENABLE (1U << PORTCON_PORTB_IE_B11_SHIFT) - -#define PORTCON_PORTB_IE_B12_SHIFT 12 -#define PORTCON_PORTB_IE_B12_WIDTH 1 -#define PORTCON_PORTB_IE_B12_MASK (((1U << PORTCON_PORTB_IE_B12_WIDTH) - 1U) << PORTCON_PORTB_IE_B12_SHIFT) -#define PORTCON_PORTB_IE_B12_DISABLE (0U << PORTCON_PORTB_IE_B12_SHIFT) -#define PORTCON_PORTB_IE_B12_ENABLE (1U << PORTCON_PORTB_IE_B12_SHIFT) - -#define PORTCON_PORTB_IE_B13_SHIFT 13 -#define PORTCON_PORTB_IE_B13_WIDTH 1 -#define PORTCON_PORTB_IE_B13_MASK (((1U << PORTCON_PORTB_IE_B13_WIDTH) - 1U) << PORTCON_PORTB_IE_B13_SHIFT) -#define PORTCON_PORTB_IE_B13_DISABLE (0U << PORTCON_PORTB_IE_B13_SHIFT) -#define PORTCON_PORTB_IE_B13_ENABLE (1U << PORTCON_PORTB_IE_B13_SHIFT) - -#define PORTCON_PORTB_IE_B14_SHIFT 14 -#define PORTCON_PORTB_IE_B14_WIDTH 1 -#define PORTCON_PORTB_IE_B14_MASK (((1U << PORTCON_PORTB_IE_B14_WIDTH) - 1U) << PORTCON_PORTB_IE_B14_SHIFT) -#define PORTCON_PORTB_IE_B14_DISABLE (0U << PORTCON_PORTB_IE_B14_SHIFT) -#define PORTCON_PORTB_IE_B14_ENABLE (1U << PORTCON_PORTB_IE_B14_SHIFT) - -#define PORTCON_PORTB_IE_B15_SHIFT 15 -#define PORTCON_PORTB_IE_B15_WIDTH 1 -#define PORTCON_PORTB_IE_B15_MASK (((1U << PORTCON_PORTB_IE_B15_WIDTH) - 1U) << PORTCON_PORTB_IE_B15_SHIFT) -#define PORTCON_PORTB_IE_B15_DISABLE (0U << PORTCON_PORTB_IE_B15_SHIFT) -#define PORTCON_PORTB_IE_B15_ENABLE (1U << PORTCON_PORTB_IE_B15_SHIFT) - -#define PORTCON_PORTC_IE_ADDR (PORTCON_BASE_ADDR + 0x0108U) -#define PORTCON_PORTC_IE (*(volatile uint32_t *)PORTCON_PORTC_IE_ADDR) -#define PORTCON_PORTC_IE_C0_SHIFT 0 -#define PORTCON_PORTC_IE_C0_WIDTH 1 -#define PORTCON_PORTC_IE_C0_MASK (((1U << PORTCON_PORTC_IE_C0_WIDTH) - 1U) << PORTCON_PORTC_IE_C0_SHIFT) -#define PORTCON_PORTC_IE_C0_DISABLE (0U << PORTCON_PORTC_IE_C0_SHIFT) -#define PORTCON_PORTC_IE_C0_ENABLE (1U << PORTCON_PORTC_IE_C0_SHIFT) - -#define PORTCON_PORTC_IE_C1_SHIFT 1 -#define PORTCON_PORTC_IE_C1_WIDTH 1 -#define PORTCON_PORTC_IE_C1_MASK (((1U << PORTCON_PORTC_IE_C1_WIDTH) - 1U) << PORTCON_PORTC_IE_C1_SHIFT) -#define PORTCON_PORTC_IE_C1_DISABLE (0U << PORTCON_PORTC_IE_C1_SHIFT) -#define PORTCON_PORTC_IE_C1_ENABLE (1U << PORTCON_PORTC_IE_C1_SHIFT) - -#define PORTCON_PORTC_IE_C2_SHIFT 2 -#define PORTCON_PORTC_IE_C2_WIDTH 1 -#define PORTCON_PORTC_IE_C2_MASK (((1U << PORTCON_PORTC_IE_C2_WIDTH) - 1U) << PORTCON_PORTC_IE_C2_SHIFT) -#define PORTCON_PORTC_IE_C2_DISABLE (0U << PORTCON_PORTC_IE_C2_SHIFT) -#define PORTCON_PORTC_IE_C2_ENABLE (1U << PORTCON_PORTC_IE_C2_SHIFT) - -#define PORTCON_PORTC_IE_C3_SHIFT 3 -#define PORTCON_PORTC_IE_C3_WIDTH 1 -#define PORTCON_PORTC_IE_C3_MASK (((1U << PORTCON_PORTC_IE_C3_WIDTH) - 1U) << PORTCON_PORTC_IE_C3_SHIFT) -#define PORTCON_PORTC_IE_C3_DISABLE (0U << PORTCON_PORTC_IE_C3_SHIFT) -#define PORTCON_PORTC_IE_C3_ENABLE (1U << PORTCON_PORTC_IE_C3_SHIFT) - -#define PORTCON_PORTC_IE_C4_SHIFT 4 -#define PORTCON_PORTC_IE_C4_WIDTH 1 -#define PORTCON_PORTC_IE_C4_MASK (((1U << PORTCON_PORTC_IE_C4_WIDTH) - 1U) << PORTCON_PORTC_IE_C4_SHIFT) -#define PORTCON_PORTC_IE_C4_DISABLE (0U << PORTCON_PORTC_IE_C4_SHIFT) -#define PORTCON_PORTC_IE_C4_ENABLE (1U << PORTCON_PORTC_IE_C4_SHIFT) - -#define PORTCON_PORTC_IE_C5_SHIFT 5 -#define PORTCON_PORTC_IE_C5_WIDTH 1 -#define PORTCON_PORTC_IE_C5_MASK (((1U << PORTCON_PORTC_IE_C5_WIDTH) - 1U) << PORTCON_PORTC_IE_C5_SHIFT) -#define PORTCON_PORTC_IE_C5_DISABLE (0U << PORTCON_PORTC_IE_C5_SHIFT) -#define PORTCON_PORTC_IE_C5_ENABLE (1U << PORTCON_PORTC_IE_C5_SHIFT) - -#define PORTCON_PORTC_IE_C6_SHIFT 6 -#define PORTCON_PORTC_IE_C6_WIDTH 1 -#define PORTCON_PORTC_IE_C6_MASK (((1U << PORTCON_PORTC_IE_C6_WIDTH) - 1U) << PORTCON_PORTC_IE_C6_SHIFT) -#define PORTCON_PORTC_IE_C6_DISABLE (0U << PORTCON_PORTC_IE_C6_SHIFT) -#define PORTCON_PORTC_IE_C6_ENABLE (1U << PORTCON_PORTC_IE_C6_SHIFT) - -#define PORTCON_PORTC_IE_C7_SHIFT 7 -#define PORTCON_PORTC_IE_C7_WIDTH 1 -#define PORTCON_PORTC_IE_C7_MASK (((1U << PORTCON_PORTC_IE_C7_WIDTH) - 1U) << PORTCON_PORTC_IE_C7_SHIFT) -#define PORTCON_PORTC_IE_C7_DISABLE (0U << PORTCON_PORTC_IE_C7_SHIFT) -#define PORTCON_PORTC_IE_C7_ENABLE (1U << PORTCON_PORTC_IE_C7_SHIFT) - -#define PORTCON_PORTC_IE_C8_SHIFT 8 -#define PORTCON_PORTC_IE_C8_WIDTH 1 -#define PORTCON_PORTC_IE_C8_MASK (((1U << PORTCON_PORTC_IE_C8_WIDTH) - 1U) << PORTCON_PORTC_IE_C8_SHIFT) -#define PORTCON_PORTC_IE_C8_DISABLE (0U << PORTCON_PORTC_IE_C8_SHIFT) -#define PORTCON_PORTC_IE_C8_ENABLE (1U << PORTCON_PORTC_IE_C8_SHIFT) - -#define PORTCON_PORTC_IE_C9_SHIFT 9 -#define PORTCON_PORTC_IE_C9_WIDTH 1 -#define PORTCON_PORTC_IE_C9_MASK (((1U << PORTCON_PORTC_IE_C9_WIDTH) - 1U) << PORTCON_PORTC_IE_C9_SHIFT) -#define PORTCON_PORTC_IE_C9_DISABLE (0U << PORTCON_PORTC_IE_C9_SHIFT) -#define PORTCON_PORTC_IE_C9_ENABLE (1U << PORTCON_PORTC_IE_C9_SHIFT) - -#define PORTCON_PORTC_IE_C10_SHIFT 10 -#define PORTCON_PORTC_IE_C10_WIDTH 1 -#define PORTCON_PORTC_IE_C10_MASK (((1U << PORTCON_PORTC_IE_C10_WIDTH) - 1U) << PORTCON_PORTC_IE_C10_SHIFT) -#define PORTCON_PORTC_IE_C10_DISABLE (0U << PORTCON_PORTC_IE_C10_SHIFT) -#define PORTCON_PORTC_IE_C10_ENABLE (1U << PORTCON_PORTC_IE_C10_SHIFT) - -#define PORTCON_PORTC_IE_C11_SHIFT 11 -#define PORTCON_PORTC_IE_C11_WIDTH 1 -#define PORTCON_PORTC_IE_C11_MASK (((1U << PORTCON_PORTC_IE_C11_WIDTH) - 1U) << PORTCON_PORTC_IE_C11_SHIFT) -#define PORTCON_PORTC_IE_C11_DISABLE (0U << PORTCON_PORTC_IE_C11_SHIFT) -#define PORTCON_PORTC_IE_C11_ENABLE (1U << PORTCON_PORTC_IE_C11_SHIFT) - -#define PORTCON_PORTC_IE_C12_SHIFT 12 -#define PORTCON_PORTC_IE_C12_WIDTH 1 -#define PORTCON_PORTC_IE_C12_MASK (((1U << PORTCON_PORTC_IE_C12_WIDTH) - 1U) << PORTCON_PORTC_IE_C12_SHIFT) -#define PORTCON_PORTC_IE_C12_DISABLE (0U << PORTCON_PORTC_IE_C12_SHIFT) -#define PORTCON_PORTC_IE_C12_ENABLE (1U << PORTCON_PORTC_IE_C12_SHIFT) - -#define PORTCON_PORTC_IE_C13_SHIFT 13 -#define PORTCON_PORTC_IE_C13_WIDTH 1 -#define PORTCON_PORTC_IE_C13_MASK (((1U << PORTCON_PORTC_IE_C13_WIDTH) - 1U) << PORTCON_PORTC_IE_C13_SHIFT) -#define PORTCON_PORTC_IE_C13_DISABLE (0U << PORTCON_PORTC_IE_C13_SHIFT) -#define PORTCON_PORTC_IE_C13_ENABLE (1U << PORTCON_PORTC_IE_C13_SHIFT) - -#define PORTCON_PORTC_IE_C14_SHIFT 14 -#define PORTCON_PORTC_IE_C14_WIDTH 1 -#define PORTCON_PORTC_IE_C14_MASK (((1U << PORTCON_PORTC_IE_C14_WIDTH) - 1U) << PORTCON_PORTC_IE_C14_SHIFT) -#define PORTCON_PORTC_IE_C14_DISABLE (0U << PORTCON_PORTC_IE_C14_SHIFT) -#define PORTCON_PORTC_IE_C14_ENABLE (1U << PORTCON_PORTC_IE_C14_SHIFT) - -#define PORTCON_PORTC_IE_C15_SHIFT 15 -#define PORTCON_PORTC_IE_C15_WIDTH 1 -#define PORTCON_PORTC_IE_C15_MASK (((1U << PORTCON_PORTC_IE_C15_WIDTH) - 1U) << PORTCON_PORTC_IE_C15_SHIFT) -#define PORTCON_PORTC_IE_C15_DISABLE (0U << PORTCON_PORTC_IE_C15_SHIFT) -#define PORTCON_PORTC_IE_C15_ENABLE (1U << PORTCON_PORTC_IE_C15_SHIFT) - -#define PORTCON_PORTA_PU_ADDR (PORTCON_BASE_ADDR + 0x0200U) -#define PORTCON_PORTA_PU (*(volatile uint32_t *)PORTCON_PORTA_PU_ADDR) -#define PORTCON_PORTA_PU_A0_SHIFT 0 -#define PORTCON_PORTA_PU_A0_WIDTH 1 -#define PORTCON_PORTA_PU_A0_MASK (((1U << PORTCON_PORTA_PU_A0_WIDTH) - 1U) << PORTCON_PORTA_PU_A0_SHIFT) -#define PORTCON_PORTA_PU_A0_DISABLE (0U << PORTCON_PORTA_PU_A0_SHIFT) -#define PORTCON_PORTA_PU_A0_ENABLE (1U << PORTCON_PORTA_PU_A0_SHIFT) - -#define PORTCON_PORTA_PU_A1_SHIFT 1 -#define PORTCON_PORTA_PU_A1_WIDTH 1 -#define PORTCON_PORTA_PU_A1_MASK (((1U << PORTCON_PORTA_PU_A1_WIDTH) - 1U) << PORTCON_PORTA_PU_A1_SHIFT) -#define PORTCON_PORTA_PU_A1_DISABLE (0U << PORTCON_PORTA_PU_A1_SHIFT) -#define PORTCON_PORTA_PU_A1_ENABLE (1U << PORTCON_PORTA_PU_A1_SHIFT) - -#define PORTCON_PORTA_PU_A2_SHIFT 2 -#define PORTCON_PORTA_PU_A2_WIDTH 1 -#define PORTCON_PORTA_PU_A2_MASK (((1U << PORTCON_PORTA_PU_A2_WIDTH) - 1U) << PORTCON_PORTA_PU_A2_SHIFT) -#define PORTCON_PORTA_PU_A2_DISABLE (0U << PORTCON_PORTA_PU_A2_SHIFT) -#define PORTCON_PORTA_PU_A2_ENABLE (1U << PORTCON_PORTA_PU_A2_SHIFT) - -#define PORTCON_PORTA_PU_A3_SHIFT 3 -#define PORTCON_PORTA_PU_A3_WIDTH 1 -#define PORTCON_PORTA_PU_A3_MASK (((1U << PORTCON_PORTA_PU_A3_WIDTH) - 1U) << PORTCON_PORTA_PU_A3_SHIFT) -#define PORTCON_PORTA_PU_A3_DISABLE (0U << PORTCON_PORTA_PU_A3_SHIFT) -#define PORTCON_PORTA_PU_A3_ENABLE (1U << PORTCON_PORTA_PU_A3_SHIFT) - -#define PORTCON_PORTA_PU_A4_SHIFT 4 -#define PORTCON_PORTA_PU_A4_WIDTH 1 -#define PORTCON_PORTA_PU_A4_MASK (((1U << PORTCON_PORTA_PU_A4_WIDTH) - 1U) << PORTCON_PORTA_PU_A4_SHIFT) -#define PORTCON_PORTA_PU_A4_DISABLE (0U << PORTCON_PORTA_PU_A4_SHIFT) -#define PORTCON_PORTA_PU_A4_ENABLE (1U << PORTCON_PORTA_PU_A4_SHIFT) - -#define PORTCON_PORTA_PU_A5_SHIFT 5 -#define PORTCON_PORTA_PU_A5_WIDTH 1 -#define PORTCON_PORTA_PU_A5_MASK (((1U << PORTCON_PORTA_PU_A5_WIDTH) - 1U) << PORTCON_PORTA_PU_A5_SHIFT) -#define PORTCON_PORTA_PU_A5_DISABLE (0U << PORTCON_PORTA_PU_A5_SHIFT) -#define PORTCON_PORTA_PU_A5_ENABLE (1U << PORTCON_PORTA_PU_A5_SHIFT) - -#define PORTCON_PORTA_PU_A6_SHIFT 6 -#define PORTCON_PORTA_PU_A6_WIDTH 1 -#define PORTCON_PORTA_PU_A6_MASK (((1U << PORTCON_PORTA_PU_A6_WIDTH) - 1U) << PORTCON_PORTA_PU_A6_SHIFT) -#define PORTCON_PORTA_PU_A6_DISABLE (0U << PORTCON_PORTA_PU_A6_SHIFT) -#define PORTCON_PORTA_PU_A6_ENABLE (1U << PORTCON_PORTA_PU_A6_SHIFT) - -#define PORTCON_PORTA_PU_A7_SHIFT 7 -#define PORTCON_PORTA_PU_A7_WIDTH 1 -#define PORTCON_PORTA_PU_A7_MASK (((1U << PORTCON_PORTA_PU_A7_WIDTH) - 1U) << PORTCON_PORTA_PU_A7_SHIFT) -#define PORTCON_PORTA_PU_A7_DISABLE (0U << PORTCON_PORTA_PU_A7_SHIFT) -#define PORTCON_PORTA_PU_A7_ENABLE (1U << PORTCON_PORTA_PU_A7_SHIFT) - -#define PORTCON_PORTA_PU_A8_SHIFT 8 -#define PORTCON_PORTA_PU_A8_WIDTH 1 -#define PORTCON_PORTA_PU_A8_MASK (((1U << PORTCON_PORTA_PU_A8_WIDTH) - 1U) << PORTCON_PORTA_PU_A8_SHIFT) -#define PORTCON_PORTA_PU_A8_DISABLE (0U << PORTCON_PORTA_PU_A8_SHIFT) -#define PORTCON_PORTA_PU_A8_ENABLE (1U << PORTCON_PORTA_PU_A8_SHIFT) - -#define PORTCON_PORTA_PU_A9_SHIFT 9 -#define PORTCON_PORTA_PU_A9_WIDTH 1 -#define PORTCON_PORTA_PU_A9_MASK (((1U << PORTCON_PORTA_PU_A9_WIDTH) - 1U) << PORTCON_PORTA_PU_A9_SHIFT) -#define PORTCON_PORTA_PU_A9_DISABLE (0U << PORTCON_PORTA_PU_A9_SHIFT) -#define PORTCON_PORTA_PU_A9_ENABLE (1U << PORTCON_PORTA_PU_A9_SHIFT) - -#define PORTCON_PORTA_PU_A10_SHIFT 10 -#define PORTCON_PORTA_PU_A10_WIDTH 1 -#define PORTCON_PORTA_PU_A10_MASK (((1U << PORTCON_PORTA_PU_A10_WIDTH) - 1U) << PORTCON_PORTA_PU_A10_SHIFT) -#define PORTCON_PORTA_PU_A10_DISABLE (0U << PORTCON_PORTA_PU_A10_SHIFT) -#define PORTCON_PORTA_PU_A10_ENABLE (1U << PORTCON_PORTA_PU_A10_SHIFT) - -#define PORTCON_PORTA_PU_A11_SHIFT 11 -#define PORTCON_PORTA_PU_A11_WIDTH 1 -#define PORTCON_PORTA_PU_A11_MASK (((1U << PORTCON_PORTA_PU_A11_WIDTH) - 1U) << PORTCON_PORTA_PU_A11_SHIFT) -#define PORTCON_PORTA_PU_A11_DISABLE (0U << PORTCON_PORTA_PU_A11_SHIFT) -#define PORTCON_PORTA_PU_A11_ENABLE (1U << PORTCON_PORTA_PU_A11_SHIFT) - -#define PORTCON_PORTA_PU_A12_SHIFT 12 -#define PORTCON_PORTA_PU_A12_WIDTH 1 -#define PORTCON_PORTA_PU_A12_MASK (((1U << PORTCON_PORTA_PU_A12_WIDTH) - 1U) << PORTCON_PORTA_PU_A12_SHIFT) -#define PORTCON_PORTA_PU_A12_DISABLE (0U << PORTCON_PORTA_PU_A12_SHIFT) -#define PORTCON_PORTA_PU_A12_ENABLE (1U << PORTCON_PORTA_PU_A12_SHIFT) - -#define PORTCON_PORTA_PU_A13_SHIFT 13 -#define PORTCON_PORTA_PU_A13_WIDTH 1 -#define PORTCON_PORTA_PU_A13_MASK (((1U << PORTCON_PORTA_PU_A13_WIDTH) - 1U) << PORTCON_PORTA_PU_A13_SHIFT) -#define PORTCON_PORTA_PU_A13_DISABLE (0U << PORTCON_PORTA_PU_A13_SHIFT) -#define PORTCON_PORTA_PU_A13_ENABLE (1U << PORTCON_PORTA_PU_A13_SHIFT) - -#define PORTCON_PORTA_PU_A14_SHIFT 14 -#define PORTCON_PORTA_PU_A14_WIDTH 1 -#define PORTCON_PORTA_PU_A14_MASK (((1U << PORTCON_PORTA_PU_A14_WIDTH) - 1U) << PORTCON_PORTA_PU_A14_SHIFT) -#define PORTCON_PORTA_PU_A14_DISABLE (0U << PORTCON_PORTA_PU_A14_SHIFT) -#define PORTCON_PORTA_PU_A14_ENABLE (1U << PORTCON_PORTA_PU_A14_SHIFT) - -#define PORTCON_PORTA_PU_A15_SHIFT 15 -#define PORTCON_PORTA_PU_A15_WIDTH 1 -#define PORTCON_PORTA_PU_A15_MASK (((1U << PORTCON_PORTA_PU_A15_WIDTH) - 1U) << PORTCON_PORTA_PU_A15_SHIFT) -#define PORTCON_PORTA_PU_A15_DISABLE (0U << PORTCON_PORTA_PU_A15_SHIFT) -#define PORTCON_PORTA_PU_A15_ENABLE (1U << PORTCON_PORTA_PU_A15_SHIFT) - -#define PORTCON_PORTB_PU_ADDR (PORTCON_BASE_ADDR + 0x0204U) -#define PORTCON_PORTB_PU (*(volatile uint32_t *)PORTCON_PORTB_PU_ADDR) -#define PORTCON_PORTB_PU_B0_SHIFT 0 -#define PORTCON_PORTB_PU_B0_WIDTH 1 -#define PORTCON_PORTB_PU_B0_MASK (((1U << PORTCON_PORTB_PU_B0_WIDTH) - 1U) << PORTCON_PORTB_PU_B0_SHIFT) -#define PORTCON_PORTB_PU_B0_DISABLE (0U << PORTCON_PORTB_PU_B0_SHIFT) -#define PORTCON_PORTB_PU_B0_ENABLE (1U << PORTCON_PORTB_PU_B0_SHIFT) - -#define PORTCON_PORTB_PU_B1_SHIFT 1 -#define PORTCON_PORTB_PU_B1_WIDTH 1 -#define PORTCON_PORTB_PU_B1_MASK (((1U << PORTCON_PORTB_PU_B1_WIDTH) - 1U) << PORTCON_PORTB_PU_B1_SHIFT) -#define PORTCON_PORTB_PU_B1_DISABLE (0U << PORTCON_PORTB_PU_B1_SHIFT) -#define PORTCON_PORTB_PU_B1_ENABLE (1U << PORTCON_PORTB_PU_B1_SHIFT) - -#define PORTCON_PORTB_PU_B2_SHIFT 2 -#define PORTCON_PORTB_PU_B2_WIDTH 1 -#define PORTCON_PORTB_PU_B2_MASK (((1U << PORTCON_PORTB_PU_B2_WIDTH) - 1U) << PORTCON_PORTB_PU_B2_SHIFT) -#define PORTCON_PORTB_PU_B2_DISABLE (0U << PORTCON_PORTB_PU_B2_SHIFT) -#define PORTCON_PORTB_PU_B2_ENABLE (1U << PORTCON_PORTB_PU_B2_SHIFT) - -#define PORTCON_PORTB_PU_B3_SHIFT 3 -#define PORTCON_PORTB_PU_B3_WIDTH 1 -#define PORTCON_PORTB_PU_B3_MASK (((1U << PORTCON_PORTB_PU_B3_WIDTH) - 1U) << PORTCON_PORTB_PU_B3_SHIFT) -#define PORTCON_PORTB_PU_B3_DISABLE (0U << PORTCON_PORTB_PU_B3_SHIFT) -#define PORTCON_PORTB_PU_B3_ENABLE (1U << PORTCON_PORTB_PU_B3_SHIFT) - -#define PORTCON_PORTB_PU_B4_SHIFT 4 -#define PORTCON_PORTB_PU_B4_WIDTH 1 -#define PORTCON_PORTB_PU_B4_MASK (((1U << PORTCON_PORTB_PU_B4_WIDTH) - 1U) << PORTCON_PORTB_PU_B4_SHIFT) -#define PORTCON_PORTB_PU_B4_DISABLE (0U << PORTCON_PORTB_PU_B4_SHIFT) -#define PORTCON_PORTB_PU_B4_ENABLE (1U << PORTCON_PORTB_PU_B4_SHIFT) - -#define PORTCON_PORTB_PU_B5_SHIFT 5 -#define PORTCON_PORTB_PU_B5_WIDTH 1 -#define PORTCON_PORTB_PU_B5_MASK (((1U << PORTCON_PORTB_PU_B5_WIDTH) - 1U) << PORTCON_PORTB_PU_B5_SHIFT) -#define PORTCON_PORTB_PU_B5_DISABLE (0U << PORTCON_PORTB_PU_B5_SHIFT) -#define PORTCON_PORTB_PU_B5_ENABLE (1U << PORTCON_PORTB_PU_B5_SHIFT) - -#define PORTCON_PORTB_PU_B6_SHIFT 6 -#define PORTCON_PORTB_PU_B6_WIDTH 1 -#define PORTCON_PORTB_PU_B6_MASK (((1U << PORTCON_PORTB_PU_B6_WIDTH) - 1U) << PORTCON_PORTB_PU_B6_SHIFT) -#define PORTCON_PORTB_PU_B6_DISABLE (0U << PORTCON_PORTB_PU_B6_SHIFT) -#define PORTCON_PORTB_PU_B6_ENABLE (1U << PORTCON_PORTB_PU_B6_SHIFT) - -#define PORTCON_PORTB_PU_B7_SHIFT 7 -#define PORTCON_PORTB_PU_B7_WIDTH 1 -#define PORTCON_PORTB_PU_B7_MASK (((1U << PORTCON_PORTB_PU_B7_WIDTH) - 1U) << PORTCON_PORTB_PU_B7_SHIFT) -#define PORTCON_PORTB_PU_B7_DISABLE (0U << PORTCON_PORTB_PU_B7_SHIFT) -#define PORTCON_PORTB_PU_B7_ENABLE (1U << PORTCON_PORTB_PU_B7_SHIFT) - -#define PORTCON_PORTB_PU_B8_SHIFT 8 -#define PORTCON_PORTB_PU_B8_WIDTH 1 -#define PORTCON_PORTB_PU_B8_MASK (((1U << PORTCON_PORTB_PU_B8_WIDTH) - 1U) << PORTCON_PORTB_PU_B8_SHIFT) -#define PORTCON_PORTB_PU_B8_DISABLE (0U << PORTCON_PORTB_PU_B8_SHIFT) -#define PORTCON_PORTB_PU_B8_ENABLE (1U << PORTCON_PORTB_PU_B8_SHIFT) - -#define PORTCON_PORTB_PU_B9_SHIFT 9 -#define PORTCON_PORTB_PU_B9_WIDTH 1 -#define PORTCON_PORTB_PU_B9_MASK (((1U << PORTCON_PORTB_PU_B9_WIDTH) - 1U) << PORTCON_PORTB_PU_B9_SHIFT) -#define PORTCON_PORTB_PU_B9_DISABLE (0U << PORTCON_PORTB_PU_B9_SHIFT) -#define PORTCON_PORTB_PU_B9_ENABLE (1U << PORTCON_PORTB_PU_B9_SHIFT) - -#define PORTCON_PORTB_PU_B10_SHIFT 10 -#define PORTCON_PORTB_PU_B10_WIDTH 1 -#define PORTCON_PORTB_PU_B10_MASK (((1U << PORTCON_PORTB_PU_B10_WIDTH) - 1U) << PORTCON_PORTB_PU_B10_SHIFT) -#define PORTCON_PORTB_PU_B10_DISABLE (0U << PORTCON_PORTB_PU_B10_SHIFT) -#define PORTCON_PORTB_PU_B10_ENABLE (1U << PORTCON_PORTB_PU_B10_SHIFT) - -#define PORTCON_PORTB_PU_B11_SHIFT 11 -#define PORTCON_PORTB_PU_B11_WIDTH 1 -#define PORTCON_PORTB_PU_B11_MASK (((1U << PORTCON_PORTB_PU_B11_WIDTH) - 1U) << PORTCON_PORTB_PU_B11_SHIFT) -#define PORTCON_PORTB_PU_B11_DISABLE (0U << PORTCON_PORTB_PU_B11_SHIFT) -#define PORTCON_PORTB_PU_B11_ENABLE (1U << PORTCON_PORTB_PU_B11_SHIFT) - -#define PORTCON_PORTB_PU_B12_SHIFT 12 -#define PORTCON_PORTB_PU_B12_WIDTH 1 -#define PORTCON_PORTB_PU_B12_MASK (((1U << PORTCON_PORTB_PU_B12_WIDTH) - 1U) << PORTCON_PORTB_PU_B12_SHIFT) -#define PORTCON_PORTB_PU_B12_DISABLE (0U << PORTCON_PORTB_PU_B12_SHIFT) -#define PORTCON_PORTB_PU_B12_ENABLE (1U << PORTCON_PORTB_PU_B12_SHIFT) - -#define PORTCON_PORTB_PU_B13_SHIFT 13 -#define PORTCON_PORTB_PU_B13_WIDTH 1 -#define PORTCON_PORTB_PU_B13_MASK (((1U << PORTCON_PORTB_PU_B13_WIDTH) - 1U) << PORTCON_PORTB_PU_B13_SHIFT) -#define PORTCON_PORTB_PU_B13_DISABLE (0U << PORTCON_PORTB_PU_B13_SHIFT) -#define PORTCON_PORTB_PU_B13_ENABLE (1U << PORTCON_PORTB_PU_B13_SHIFT) - -#define PORTCON_PORTB_PU_B14_SHIFT 14 -#define PORTCON_PORTB_PU_B14_WIDTH 1 -#define PORTCON_PORTB_PU_B14_MASK (((1U << PORTCON_PORTB_PU_B14_WIDTH) - 1U) << PORTCON_PORTB_PU_B14_SHIFT) -#define PORTCON_PORTB_PU_B14_DISABLE (0U << PORTCON_PORTB_PU_B14_SHIFT) -#define PORTCON_PORTB_PU_B14_ENABLE (1U << PORTCON_PORTB_PU_B14_SHIFT) - -#define PORTCON_PORTB_PU_B15_SHIFT 15 -#define PORTCON_PORTB_PU_B15_WIDTH 1 -#define PORTCON_PORTB_PU_B15_MASK (((1U << PORTCON_PORTB_PU_B15_WIDTH) - 1U) << PORTCON_PORTB_PU_B15_SHIFT) -#define PORTCON_PORTB_PU_B15_DISABLE (0U << PORTCON_PORTB_PU_B15_SHIFT) -#define PORTCON_PORTB_PU_B15_ENABLE (1U << PORTCON_PORTB_PU_B15_SHIFT) - -#define PORTCON_PORTC_PU_ADDR (PORTCON_BASE_ADDR + 0x0208U) -#define PORTCON_PORTC_PU (*(volatile uint32_t *)PORTCON_PORTC_PU_ADDR) -#define PORTCON_PORTC_PU_C0_SHIFT 0 -#define PORTCON_PORTC_PU_C0_WIDTH 1 -#define PORTCON_PORTC_PU_C0_MASK (((1U << PORTCON_PORTC_PU_C0_WIDTH) - 1U) << PORTCON_PORTC_PU_C0_SHIFT) -#define PORTCON_PORTC_PU_C0_DISABLE (0U << PORTCON_PORTC_PU_C0_SHIFT) -#define PORTCON_PORTC_PU_C0_ENABLE (1U << PORTCON_PORTC_PU_C0_SHIFT) - -#define PORTCON_PORTC_PU_C1_SHIFT 1 -#define PORTCON_PORTC_PU_C1_WIDTH 1 -#define PORTCON_PORTC_PU_C1_MASK (((1U << PORTCON_PORTC_PU_C1_WIDTH) - 1U) << PORTCON_PORTC_PU_C1_SHIFT) -#define PORTCON_PORTC_PU_C1_DISABLE (0U << PORTCON_PORTC_PU_C1_SHIFT) -#define PORTCON_PORTC_PU_C1_ENABLE (1U << PORTCON_PORTC_PU_C1_SHIFT) - -#define PORTCON_PORTC_PU_C2_SHIFT 2 -#define PORTCON_PORTC_PU_C2_WIDTH 1 -#define PORTCON_PORTC_PU_C2_MASK (((1U << PORTCON_PORTC_PU_C2_WIDTH) - 1U) << PORTCON_PORTC_PU_C2_SHIFT) -#define PORTCON_PORTC_PU_C2_DISABLE (0U << PORTCON_PORTC_PU_C2_SHIFT) -#define PORTCON_PORTC_PU_C2_ENABLE (1U << PORTCON_PORTC_PU_C2_SHIFT) - -#define PORTCON_PORTC_PU_C3_SHIFT 3 -#define PORTCON_PORTC_PU_C3_WIDTH 1 -#define PORTCON_PORTC_PU_C3_MASK (((1U << PORTCON_PORTC_PU_C3_WIDTH) - 1U) << PORTCON_PORTC_PU_C3_SHIFT) -#define PORTCON_PORTC_PU_C3_DISABLE (0U << PORTCON_PORTC_PU_C3_SHIFT) -#define PORTCON_PORTC_PU_C3_ENABLE (1U << PORTCON_PORTC_PU_C3_SHIFT) - -#define PORTCON_PORTC_PU_C4_SHIFT 4 -#define PORTCON_PORTC_PU_C4_WIDTH 1 -#define PORTCON_PORTC_PU_C4_MASK (((1U << PORTCON_PORTC_PU_C4_WIDTH) - 1U) << PORTCON_PORTC_PU_C4_SHIFT) -#define PORTCON_PORTC_PU_C4_DISABLE (0U << PORTCON_PORTC_PU_C4_SHIFT) -#define PORTCON_PORTC_PU_C4_ENABLE (1U << PORTCON_PORTC_PU_C4_SHIFT) - -#define PORTCON_PORTC_PU_C5_SHIFT 5 -#define PORTCON_PORTC_PU_C5_WIDTH 1 -#define PORTCON_PORTC_PU_C5_MASK (((1U << PORTCON_PORTC_PU_C5_WIDTH) - 1U) << PORTCON_PORTC_PU_C5_SHIFT) -#define PORTCON_PORTC_PU_C5_DISABLE (0U << PORTCON_PORTC_PU_C5_SHIFT) -#define PORTCON_PORTC_PU_C5_ENABLE (1U << PORTCON_PORTC_PU_C5_SHIFT) - -#define PORTCON_PORTC_PU_C6_SHIFT 6 -#define PORTCON_PORTC_PU_C6_WIDTH 1 -#define PORTCON_PORTC_PU_C6_MASK (((1U << PORTCON_PORTC_PU_C6_WIDTH) - 1U) << PORTCON_PORTC_PU_C6_SHIFT) -#define PORTCON_PORTC_PU_C6_DISABLE (0U << PORTCON_PORTC_PU_C6_SHIFT) -#define PORTCON_PORTC_PU_C6_ENABLE (1U << PORTCON_PORTC_PU_C6_SHIFT) - -#define PORTCON_PORTC_PU_C7_SHIFT 7 -#define PORTCON_PORTC_PU_C7_WIDTH 1 -#define PORTCON_PORTC_PU_C7_MASK (((1U << PORTCON_PORTC_PU_C7_WIDTH) - 1U) << PORTCON_PORTC_PU_C7_SHIFT) -#define PORTCON_PORTC_PU_C7_DISABLE (0U << PORTCON_PORTC_PU_C7_SHIFT) -#define PORTCON_PORTC_PU_C7_ENABLE (1U << PORTCON_PORTC_PU_C7_SHIFT) - -#define PORTCON_PORTC_PU_C8_SHIFT 8 -#define PORTCON_PORTC_PU_C8_WIDTH 1 -#define PORTCON_PORTC_PU_C8_MASK (((1U << PORTCON_PORTC_PU_C8_WIDTH) - 1U) << PORTCON_PORTC_PU_C8_SHIFT) -#define PORTCON_PORTC_PU_C8_DISABLE (0U << PORTCON_PORTC_PU_C8_SHIFT) -#define PORTCON_PORTC_PU_C8_ENABLE (1U << PORTCON_PORTC_PU_C8_SHIFT) - -#define PORTCON_PORTC_PU_C9_SHIFT 9 -#define PORTCON_PORTC_PU_C9_WIDTH 1 -#define PORTCON_PORTC_PU_C9_MASK (((1U << PORTCON_PORTC_PU_C9_WIDTH) - 1U) << PORTCON_PORTC_PU_C9_SHIFT) -#define PORTCON_PORTC_PU_C9_DISABLE (0U << PORTCON_PORTC_PU_C9_SHIFT) -#define PORTCON_PORTC_PU_C9_ENABLE (1U << PORTCON_PORTC_PU_C9_SHIFT) - -#define PORTCON_PORTC_PU_C10_SHIFT 10 -#define PORTCON_PORTC_PU_C10_WIDTH 1 -#define PORTCON_PORTC_PU_C10_MASK (((1U << PORTCON_PORTC_PU_C10_WIDTH) - 1U) << PORTCON_PORTC_PU_C10_SHIFT) -#define PORTCON_PORTC_PU_C10_DISABLE (0U << PORTCON_PORTC_PU_C10_SHIFT) -#define PORTCON_PORTC_PU_C10_ENABLE (1U << PORTCON_PORTC_PU_C10_SHIFT) - -#define PORTCON_PORTC_PU_C11_SHIFT 11 -#define PORTCON_PORTC_PU_C11_WIDTH 1 -#define PORTCON_PORTC_PU_C11_MASK (((1U << PORTCON_PORTC_PU_C11_WIDTH) - 1U) << PORTCON_PORTC_PU_C11_SHIFT) -#define PORTCON_PORTC_PU_C11_DISABLE (0U << PORTCON_PORTC_PU_C11_SHIFT) -#define PORTCON_PORTC_PU_C11_ENABLE (1U << PORTCON_PORTC_PU_C11_SHIFT) - -#define PORTCON_PORTC_PU_C12_SHIFT 12 -#define PORTCON_PORTC_PU_C12_WIDTH 1 -#define PORTCON_PORTC_PU_C12_MASK (((1U << PORTCON_PORTC_PU_C12_WIDTH) - 1U) << PORTCON_PORTC_PU_C12_SHIFT) -#define PORTCON_PORTC_PU_C12_DISABLE (0U << PORTCON_PORTC_PU_C12_SHIFT) -#define PORTCON_PORTC_PU_C12_ENABLE (1U << PORTCON_PORTC_PU_C12_SHIFT) - -#define PORTCON_PORTC_PU_C13_SHIFT 13 -#define PORTCON_PORTC_PU_C13_WIDTH 1 -#define PORTCON_PORTC_PU_C13_MASK (((1U << PORTCON_PORTC_PU_C13_WIDTH) - 1U) << PORTCON_PORTC_PU_C13_SHIFT) -#define PORTCON_PORTC_PU_C13_DISABLE (0U << PORTCON_PORTC_PU_C13_SHIFT) -#define PORTCON_PORTC_PU_C13_ENABLE (1U << PORTCON_PORTC_PU_C13_SHIFT) - -#define PORTCON_PORTC_PU_C14_SHIFT 14 -#define PORTCON_PORTC_PU_C14_WIDTH 1 -#define PORTCON_PORTC_PU_C14_MASK (((1U << PORTCON_PORTC_PU_C14_WIDTH) - 1U) << PORTCON_PORTC_PU_C14_SHIFT) -#define PORTCON_PORTC_PU_C14_DISABLE (0U << PORTCON_PORTC_PU_C14_SHIFT) -#define PORTCON_PORTC_PU_C14_ENABLE (1U << PORTCON_PORTC_PU_C14_SHIFT) - -#define PORTCON_PORTC_PU_C15_SHIFT 15 -#define PORTCON_PORTC_PU_C15_WIDTH 1 -#define PORTCON_PORTC_PU_C15_MASK (((1U << PORTCON_PORTC_PU_C15_WIDTH) - 1U) << PORTCON_PORTC_PU_C15_SHIFT) -#define PORTCON_PORTC_PU_C15_DISABLE (0U << PORTCON_PORTC_PU_C15_SHIFT) -#define PORTCON_PORTC_PU_C15_ENABLE (1U << PORTCON_PORTC_PU_C15_SHIFT) - -#define PORTCON_PORTA_PD_ADDR (PORTCON_BASE_ADDR + 0x0300U) -#define PORTCON_PORTA_PD (*(volatile uint32_t *)PORTCON_PORTA_PD_ADDR) -#define PORTCON_PORTA_PD_A0_SHIFT 0 -#define PORTCON_PORTA_PD_A0_WIDTH 1 -#define PORTCON_PORTA_PD_A0_MASK (((1U << PORTCON_PORTA_PD_A0_WIDTH) - 1U) << PORTCON_PORTA_PD_A0_SHIFT) -#define PORTCON_PORTA_PD_A0_DISABLE (0U << PORTCON_PORTA_PD_A0_SHIFT) -#define PORTCON_PORTA_PD_A0_ENABLE (1U << PORTCON_PORTA_PD_A0_SHIFT) - -#define PORTCON_PORTA_PD_A1_SHIFT 1 -#define PORTCON_PORTA_PD_A1_WIDTH 1 -#define PORTCON_PORTA_PD_A1_MASK (((1U << PORTCON_PORTA_PD_A1_WIDTH) - 1U) << PORTCON_PORTA_PD_A1_SHIFT) -#define PORTCON_PORTA_PD_A1_DISABLE (0U << PORTCON_PORTA_PD_A1_SHIFT) -#define PORTCON_PORTA_PD_A1_ENABLE (1U << PORTCON_PORTA_PD_A1_SHIFT) - -#define PORTCON_PORTA_PD_A2_SHIFT 2 -#define PORTCON_PORTA_PD_A2_WIDTH 1 -#define PORTCON_PORTA_PD_A2_MASK (((1U << PORTCON_PORTA_PD_A2_WIDTH) - 1U) << PORTCON_PORTA_PD_A2_SHIFT) -#define PORTCON_PORTA_PD_A2_DISABLE (0U << PORTCON_PORTA_PD_A2_SHIFT) -#define PORTCON_PORTA_PD_A2_ENABLE (1U << PORTCON_PORTA_PD_A2_SHIFT) - -#define PORTCON_PORTA_PD_A3_SHIFT 3 -#define PORTCON_PORTA_PD_A3_WIDTH 1 -#define PORTCON_PORTA_PD_A3_MASK (((1U << PORTCON_PORTA_PD_A3_WIDTH) - 1U) << PORTCON_PORTA_PD_A3_SHIFT) -#define PORTCON_PORTA_PD_A3_DISABLE (0U << PORTCON_PORTA_PD_A3_SHIFT) -#define PORTCON_PORTA_PD_A3_ENABLE (1U << PORTCON_PORTA_PD_A3_SHIFT) - -#define PORTCON_PORTA_PD_A4_SHIFT 4 -#define PORTCON_PORTA_PD_A4_WIDTH 1 -#define PORTCON_PORTA_PD_A4_MASK (((1U << PORTCON_PORTA_PD_A4_WIDTH) - 1U) << PORTCON_PORTA_PD_A4_SHIFT) -#define PORTCON_PORTA_PD_A4_DISABLE (0U << PORTCON_PORTA_PD_A4_SHIFT) -#define PORTCON_PORTA_PD_A4_ENABLE (1U << PORTCON_PORTA_PD_A4_SHIFT) - -#define PORTCON_PORTA_PD_A5_SHIFT 5 -#define PORTCON_PORTA_PD_A5_WIDTH 1 -#define PORTCON_PORTA_PD_A5_MASK (((1U << PORTCON_PORTA_PD_A5_WIDTH) - 1U) << PORTCON_PORTA_PD_A5_SHIFT) -#define PORTCON_PORTA_PD_A5_DISABLE (0U << PORTCON_PORTA_PD_A5_SHIFT) -#define PORTCON_PORTA_PD_A5_ENABLE (1U << PORTCON_PORTA_PD_A5_SHIFT) - -#define PORTCON_PORTA_PD_A6_SHIFT 6 -#define PORTCON_PORTA_PD_A6_WIDTH 1 -#define PORTCON_PORTA_PD_A6_MASK (((1U << PORTCON_PORTA_PD_A6_WIDTH) - 1U) << PORTCON_PORTA_PD_A6_SHIFT) -#define PORTCON_PORTA_PD_A6_DISABLE (0U << PORTCON_PORTA_PD_A6_SHIFT) -#define PORTCON_PORTA_PD_A6_ENABLE (1U << PORTCON_PORTA_PD_A6_SHIFT) - -#define PORTCON_PORTA_PD_A7_SHIFT 7 -#define PORTCON_PORTA_PD_A7_WIDTH 1 -#define PORTCON_PORTA_PD_A7_MASK (((1U << PORTCON_PORTA_PD_A7_WIDTH) - 1U) << PORTCON_PORTA_PD_A7_SHIFT) -#define PORTCON_PORTA_PD_A7_DISABLE (0U << PORTCON_PORTA_PD_A7_SHIFT) -#define PORTCON_PORTA_PD_A7_ENABLE (1U << PORTCON_PORTA_PD_A7_SHIFT) - -#define PORTCON_PORTA_PD_A8_SHIFT 8 -#define PORTCON_PORTA_PD_A8_WIDTH 1 -#define PORTCON_PORTA_PD_A8_MASK (((1U << PORTCON_PORTA_PD_A8_WIDTH) - 1U) << PORTCON_PORTA_PD_A8_SHIFT) -#define PORTCON_PORTA_PD_A8_DISABLE (0U << PORTCON_PORTA_PD_A8_SHIFT) -#define PORTCON_PORTA_PD_A8_ENABLE (1U << PORTCON_PORTA_PD_A8_SHIFT) - -#define PORTCON_PORTA_PD_A9_SHIFT 9 -#define PORTCON_PORTA_PD_A9_WIDTH 1 -#define PORTCON_PORTA_PD_A9_MASK (((1U << PORTCON_PORTA_PD_A9_WIDTH) - 1U) << PORTCON_PORTA_PD_A9_SHIFT) -#define PORTCON_PORTA_PD_A9_DISABLE (0U << PORTCON_PORTA_PD_A9_SHIFT) -#define PORTCON_PORTA_PD_A9_ENABLE (1U << PORTCON_PORTA_PD_A9_SHIFT) - -#define PORTCON_PORTA_PD_A10_SHIFT 10 -#define PORTCON_PORTA_PD_A10_WIDTH 1 -#define PORTCON_PORTA_PD_A10_MASK (((1U << PORTCON_PORTA_PD_A10_WIDTH) - 1U) << PORTCON_PORTA_PD_A10_SHIFT) -#define PORTCON_PORTA_PD_A10_DISABLE (0U << PORTCON_PORTA_PD_A10_SHIFT) -#define PORTCON_PORTA_PD_A10_ENABLE (1U << PORTCON_PORTA_PD_A10_SHIFT) - -#define PORTCON_PORTA_PD_A11_SHIFT 11 -#define PORTCON_PORTA_PD_A11_WIDTH 1 -#define PORTCON_PORTA_PD_A11_MASK (((1U << PORTCON_PORTA_PD_A11_WIDTH) - 1U) << PORTCON_PORTA_PD_A11_SHIFT) -#define PORTCON_PORTA_PD_A11_DISABLE (0U << PORTCON_PORTA_PD_A11_SHIFT) -#define PORTCON_PORTA_PD_A11_ENABLE (1U << PORTCON_PORTA_PD_A11_SHIFT) - -#define PORTCON_PORTA_PD_A12_SHIFT 12 -#define PORTCON_PORTA_PD_A12_WIDTH 1 -#define PORTCON_PORTA_PD_A12_MASK (((1U << PORTCON_PORTA_PD_A12_WIDTH) - 1U) << PORTCON_PORTA_PD_A12_SHIFT) -#define PORTCON_PORTA_PD_A12_DISABLE (0U << PORTCON_PORTA_PD_A12_SHIFT) -#define PORTCON_PORTA_PD_A12_ENABLE (1U << PORTCON_PORTA_PD_A12_SHIFT) - -#define PORTCON_PORTA_PD_A13_SHIFT 13 -#define PORTCON_PORTA_PD_A13_WIDTH 1 -#define PORTCON_PORTA_PD_A13_MASK (((1U << PORTCON_PORTA_PD_A13_WIDTH) - 1U) << PORTCON_PORTA_PD_A13_SHIFT) -#define PORTCON_PORTA_PD_A13_DISABLE (0U << PORTCON_PORTA_PD_A13_SHIFT) -#define PORTCON_PORTA_PD_A13_ENABLE (1U << PORTCON_PORTA_PD_A13_SHIFT) - -#define PORTCON_PORTA_PD_A14_SHIFT 14 -#define PORTCON_PORTA_PD_A14_WIDTH 1 -#define PORTCON_PORTA_PD_A14_MASK (((1U << PORTCON_PORTA_PD_A14_WIDTH) - 1U) << PORTCON_PORTA_PD_A14_SHIFT) -#define PORTCON_PORTA_PD_A14_DISABLE (0U << PORTCON_PORTA_PD_A14_SHIFT) -#define PORTCON_PORTA_PD_A14_ENABLE (1U << PORTCON_PORTA_PD_A14_SHIFT) - -#define PORTCON_PORTA_PD_A15_SHIFT 15 -#define PORTCON_PORTA_PD_A15_WIDTH 1 -#define PORTCON_PORTA_PD_A15_MASK (((1U << PORTCON_PORTA_PD_A15_WIDTH) - 1U) << PORTCON_PORTA_PD_A15_SHIFT) -#define PORTCON_PORTA_PD_A15_DISABLE (0U << PORTCON_PORTA_PD_A15_SHIFT) -#define PORTCON_PORTA_PD_A15_ENABLE (1U << PORTCON_PORTA_PD_A15_SHIFT) - -#define PORTCON_PORTB_PD_ADDR (PORTCON_BASE_ADDR + 0x0304U) -#define PORTCON_PORTB_PD (*(volatile uint32_t *)PORTCON_PORTB_PD_ADDR) -#define PORTCON_PORTB_PD_B0_SHIFT 0 -#define PORTCON_PORTB_PD_B0_WIDTH 1 -#define PORTCON_PORTB_PD_B0_MASK (((1U << PORTCON_PORTB_PD_B0_WIDTH) - 1U) << PORTCON_PORTB_PD_B0_SHIFT) -#define PORTCON_PORTB_PD_B0_DISABLE (0U << PORTCON_PORTB_PD_B0_SHIFT) -#define PORTCON_PORTB_PD_B0_ENABLE (1U << PORTCON_PORTB_PD_B0_SHIFT) - -#define PORTCON_PORTB_PD_B1_SHIFT 1 -#define PORTCON_PORTB_PD_B1_WIDTH 1 -#define PORTCON_PORTB_PD_B1_MASK (((1U << PORTCON_PORTB_PD_B1_WIDTH) - 1U) << PORTCON_PORTB_PD_B1_SHIFT) -#define PORTCON_PORTB_PD_B1_DISABLE (0U << PORTCON_PORTB_PD_B1_SHIFT) -#define PORTCON_PORTB_PD_B1_ENABLE (1U << PORTCON_PORTB_PD_B1_SHIFT) - -#define PORTCON_PORTB_PD_B2_SHIFT 2 -#define PORTCON_PORTB_PD_B2_WIDTH 1 -#define PORTCON_PORTB_PD_B2_MASK (((1U << PORTCON_PORTB_PD_B2_WIDTH) - 1U) << PORTCON_PORTB_PD_B2_SHIFT) -#define PORTCON_PORTB_PD_B2_DISABLE (0U << PORTCON_PORTB_PD_B2_SHIFT) -#define PORTCON_PORTB_PD_B2_ENABLE (1U << PORTCON_PORTB_PD_B2_SHIFT) - -#define PORTCON_PORTB_PD_B3_SHIFT 3 -#define PORTCON_PORTB_PD_B3_WIDTH 1 -#define PORTCON_PORTB_PD_B3_MASK (((1U << PORTCON_PORTB_PD_B3_WIDTH) - 1U) << PORTCON_PORTB_PD_B3_SHIFT) -#define PORTCON_PORTB_PD_B3_DISABLE (0U << PORTCON_PORTB_PD_B3_SHIFT) -#define PORTCON_PORTB_PD_B3_ENABLE (1U << PORTCON_PORTB_PD_B3_SHIFT) - -#define PORTCON_PORTB_PD_B4_SHIFT 4 -#define PORTCON_PORTB_PD_B4_WIDTH 1 -#define PORTCON_PORTB_PD_B4_MASK (((1U << PORTCON_PORTB_PD_B4_WIDTH) - 1U) << PORTCON_PORTB_PD_B4_SHIFT) -#define PORTCON_PORTB_PD_B4_DISABLE (0U << PORTCON_PORTB_PD_B4_SHIFT) -#define PORTCON_PORTB_PD_B4_ENABLE (1U << PORTCON_PORTB_PD_B4_SHIFT) - -#define PORTCON_PORTB_PD_B5_SHIFT 5 -#define PORTCON_PORTB_PD_B5_WIDTH 1 -#define PORTCON_PORTB_PD_B5_MASK (((1U << PORTCON_PORTB_PD_B5_WIDTH) - 1U) << PORTCON_PORTB_PD_B5_SHIFT) -#define PORTCON_PORTB_PD_B5_DISABLE (0U << PORTCON_PORTB_PD_B5_SHIFT) -#define PORTCON_PORTB_PD_B5_ENABLE (1U << PORTCON_PORTB_PD_B5_SHIFT) - -#define PORTCON_PORTB_PD_B6_SHIFT 6 -#define PORTCON_PORTB_PD_B6_WIDTH 1 -#define PORTCON_PORTB_PD_B6_MASK (((1U << PORTCON_PORTB_PD_B6_WIDTH) - 1U) << PORTCON_PORTB_PD_B6_SHIFT) -#define PORTCON_PORTB_PD_B6_DISABLE (0U << PORTCON_PORTB_PD_B6_SHIFT) -#define PORTCON_PORTB_PD_B6_ENABLE (1U << PORTCON_PORTB_PD_B6_SHIFT) - -#define PORTCON_PORTB_PD_B7_SHIFT 7 -#define PORTCON_PORTB_PD_B7_WIDTH 1 -#define PORTCON_PORTB_PD_B7_MASK (((1U << PORTCON_PORTB_PD_B7_WIDTH) - 1U) << PORTCON_PORTB_PD_B7_SHIFT) -#define PORTCON_PORTB_PD_B7_DISABLE (0U << PORTCON_PORTB_PD_B7_SHIFT) -#define PORTCON_PORTB_PD_B7_ENABLE (1U << PORTCON_PORTB_PD_B7_SHIFT) - -#define PORTCON_PORTB_PD_B8_SHIFT 8 -#define PORTCON_PORTB_PD_B8_WIDTH 1 -#define PORTCON_PORTB_PD_B8_MASK (((1U << PORTCON_PORTB_PD_B8_WIDTH) - 1U) << PORTCON_PORTB_PD_B8_SHIFT) -#define PORTCON_PORTB_PD_B8_DISABLE (0U << PORTCON_PORTB_PD_B8_SHIFT) -#define PORTCON_PORTB_PD_B8_ENABLE (1U << PORTCON_PORTB_PD_B8_SHIFT) - -#define PORTCON_PORTB_PD_B9_SHIFT 9 -#define PORTCON_PORTB_PD_B9_WIDTH 1 -#define PORTCON_PORTB_PD_B9_MASK (((1U << PORTCON_PORTB_PD_B9_WIDTH) - 1U) << PORTCON_PORTB_PD_B9_SHIFT) -#define PORTCON_PORTB_PD_B9_DISABLE (0U << PORTCON_PORTB_PD_B9_SHIFT) -#define PORTCON_PORTB_PD_B9_ENABLE (1U << PORTCON_PORTB_PD_B9_SHIFT) - -#define PORTCON_PORTB_PD_B10_SHIFT 10 -#define PORTCON_PORTB_PD_B10_WIDTH 1 -#define PORTCON_PORTB_PD_B10_MASK (((1U << PORTCON_PORTB_PD_B10_WIDTH) - 1U) << PORTCON_PORTB_PD_B10_SHIFT) -#define PORTCON_PORTB_PD_B10_DISABLE (0U << PORTCON_PORTB_PD_B10_SHIFT) -#define PORTCON_PORTB_PD_B10_ENABLE (1U << PORTCON_PORTB_PD_B10_SHIFT) - -#define PORTCON_PORTB_PD_B11_SHIFT 11 -#define PORTCON_PORTB_PD_B11_WIDTH 1 -#define PORTCON_PORTB_PD_B11_MASK (((1U << PORTCON_PORTB_PD_B11_WIDTH) - 1U) << PORTCON_PORTB_PD_B11_SHIFT) -#define PORTCON_PORTB_PD_B11_DISABLE (0U << PORTCON_PORTB_PD_B11_SHIFT) -#define PORTCON_PORTB_PD_B11_ENABLE (1U << PORTCON_PORTB_PD_B11_SHIFT) - -#define PORTCON_PORTB_PD_B12_SHIFT 12 -#define PORTCON_PORTB_PD_B12_WIDTH 1 -#define PORTCON_PORTB_PD_B12_MASK (((1U << PORTCON_PORTB_PD_B12_WIDTH) - 1U) << PORTCON_PORTB_PD_B12_SHIFT) -#define PORTCON_PORTB_PD_B12_DISABLE (0U << PORTCON_PORTB_PD_B12_SHIFT) -#define PORTCON_PORTB_PD_B12_ENABLE (1U << PORTCON_PORTB_PD_B12_SHIFT) - -#define PORTCON_PORTB_PD_B13_SHIFT 13 -#define PORTCON_PORTB_PD_B13_WIDTH 1 -#define PORTCON_PORTB_PD_B13_MASK (((1U << PORTCON_PORTB_PD_B13_WIDTH) - 1U) << PORTCON_PORTB_PD_B13_SHIFT) -#define PORTCON_PORTB_PD_B13_DISABLE (0U << PORTCON_PORTB_PD_B13_SHIFT) -#define PORTCON_PORTB_PD_B13_ENABLE (1U << PORTCON_PORTB_PD_B13_SHIFT) - -#define PORTCON_PORTB_PD_B14_SHIFT 14 -#define PORTCON_PORTB_PD_B14_WIDTH 1 -#define PORTCON_PORTB_PD_B14_MASK (((1U << PORTCON_PORTB_PD_B14_WIDTH) - 1U) << PORTCON_PORTB_PD_B14_SHIFT) -#define PORTCON_PORTB_PD_B14_DISABLE (0U << PORTCON_PORTB_PD_B14_SHIFT) -#define PORTCON_PORTB_PD_B14_ENABLE (1U << PORTCON_PORTB_PD_B14_SHIFT) - -#define PORTCON_PORTB_PD_B15_SHIFT 15 -#define PORTCON_PORTB_PD_B15_WIDTH 1 -#define PORTCON_PORTB_PD_B15_MASK (((1U << PORTCON_PORTB_PD_B15_WIDTH) - 1U) << PORTCON_PORTB_PD_B15_SHIFT) -#define PORTCON_PORTB_PD_B15_DISABLE (0U << PORTCON_PORTB_PD_B15_SHIFT) -#define PORTCON_PORTB_PD_B15_ENABLE (1U << PORTCON_PORTB_PD_B15_SHIFT) - -#define PORTCON_PORTC_PD_ADDR (PORTCON_BASE_ADDR + 0x0308U) -#define PORTCON_PORTC_PD (*(volatile uint32_t *)PORTCON_PORTC_PD_ADDR) -#define PORTCON_PORTC_PD_C0_SHIFT 0 -#define PORTCON_PORTC_PD_C0_WIDTH 1 -#define PORTCON_PORTC_PD_C0_MASK (((1U << PORTCON_PORTC_PD_C0_WIDTH) - 1U) << PORTCON_PORTC_PD_C0_SHIFT) -#define PORTCON_PORTC_PD_C0_DISABLE (0U << PORTCON_PORTC_PD_C0_SHIFT) -#define PORTCON_PORTC_PD_C0_ENABLE (1U << PORTCON_PORTC_PD_C0_SHIFT) - -#define PORTCON_PORTC_PD_C1_SHIFT 1 -#define PORTCON_PORTC_PD_C1_WIDTH 1 -#define PORTCON_PORTC_PD_C1_MASK (((1U << PORTCON_PORTC_PD_C1_WIDTH) - 1U) << PORTCON_PORTC_PD_C1_SHIFT) -#define PORTCON_PORTC_PD_C1_DISABLE (0U << PORTCON_PORTC_PD_C1_SHIFT) -#define PORTCON_PORTC_PD_C1_ENABLE (1U << PORTCON_PORTC_PD_C1_SHIFT) - -#define PORTCON_PORTC_PD_C2_SHIFT 2 -#define PORTCON_PORTC_PD_C2_WIDTH 1 -#define PORTCON_PORTC_PD_C2_MASK (((1U << PORTCON_PORTC_PD_C2_WIDTH) - 1U) << PORTCON_PORTC_PD_C2_SHIFT) -#define PORTCON_PORTC_PD_C2_DISABLE (0U << PORTCON_PORTC_PD_C2_SHIFT) -#define PORTCON_PORTC_PD_C2_ENABLE (1U << PORTCON_PORTC_PD_C2_SHIFT) - -#define PORTCON_PORTC_PD_C3_SHIFT 3 -#define PORTCON_PORTC_PD_C3_WIDTH 1 -#define PORTCON_PORTC_PD_C3_MASK (((1U << PORTCON_PORTC_PD_C3_WIDTH) - 1U) << PORTCON_PORTC_PD_C3_SHIFT) -#define PORTCON_PORTC_PD_C3_DISABLE (0U << PORTCON_PORTC_PD_C3_SHIFT) -#define PORTCON_PORTC_PD_C3_ENABLE (1U << PORTCON_PORTC_PD_C3_SHIFT) - -#define PORTCON_PORTC_PD_C4_SHIFT 4 -#define PORTCON_PORTC_PD_C4_WIDTH 1 -#define PORTCON_PORTC_PD_C4_MASK (((1U << PORTCON_PORTC_PD_C4_WIDTH) - 1U) << PORTCON_PORTC_PD_C4_SHIFT) -#define PORTCON_PORTC_PD_C4_DISABLE (0U << PORTCON_PORTC_PD_C4_SHIFT) -#define PORTCON_PORTC_PD_C4_ENABLE (1U << PORTCON_PORTC_PD_C4_SHIFT) - -#define PORTCON_PORTC_PD_C5_SHIFT 5 -#define PORTCON_PORTC_PD_C5_WIDTH 1 -#define PORTCON_PORTC_PD_C5_MASK (((1U << PORTCON_PORTC_PD_C5_WIDTH) - 1U) << PORTCON_PORTC_PD_C5_SHIFT) -#define PORTCON_PORTC_PD_C5_DISABLE (0U << PORTCON_PORTC_PD_C5_SHIFT) -#define PORTCON_PORTC_PD_C5_ENABLE (1U << PORTCON_PORTC_PD_C5_SHIFT) - -#define PORTCON_PORTC_PD_C6_SHIFT 6 -#define PORTCON_PORTC_PD_C6_WIDTH 1 -#define PORTCON_PORTC_PD_C6_MASK (((1U << PORTCON_PORTC_PD_C6_WIDTH) - 1U) << PORTCON_PORTC_PD_C6_SHIFT) -#define PORTCON_PORTC_PD_C6_DISABLE (0U << PORTCON_PORTC_PD_C6_SHIFT) -#define PORTCON_PORTC_PD_C6_ENABLE (1U << PORTCON_PORTC_PD_C6_SHIFT) - -#define PORTCON_PORTC_PD_C7_SHIFT 7 -#define PORTCON_PORTC_PD_C7_WIDTH 1 -#define PORTCON_PORTC_PD_C7_MASK (((1U << PORTCON_PORTC_PD_C7_WIDTH) - 1U) << PORTCON_PORTC_PD_C7_SHIFT) -#define PORTCON_PORTC_PD_C7_DISABLE (0U << PORTCON_PORTC_PD_C7_SHIFT) -#define PORTCON_PORTC_PD_C7_ENABLE (1U << PORTCON_PORTC_PD_C7_SHIFT) - -#define PORTCON_PORTC_PD_C8_SHIFT 8 -#define PORTCON_PORTC_PD_C8_WIDTH 1 -#define PORTCON_PORTC_PD_C8_MASK (((1U << PORTCON_PORTC_PD_C8_WIDTH) - 1U) << PORTCON_PORTC_PD_C8_SHIFT) -#define PORTCON_PORTC_PD_C8_DISABLE (0U << PORTCON_PORTC_PD_C8_SHIFT) -#define PORTCON_PORTC_PD_C8_ENABLE (1U << PORTCON_PORTC_PD_C8_SHIFT) - -#define PORTCON_PORTC_PD_C9_SHIFT 9 -#define PORTCON_PORTC_PD_C9_WIDTH 1 -#define PORTCON_PORTC_PD_C9_MASK (((1U << PORTCON_PORTC_PD_C9_WIDTH) - 1U) << PORTCON_PORTC_PD_C9_SHIFT) -#define PORTCON_PORTC_PD_C9_DISABLE (0U << PORTCON_PORTC_PD_C9_SHIFT) -#define PORTCON_PORTC_PD_C9_ENABLE (1U << PORTCON_PORTC_PD_C9_SHIFT) - -#define PORTCON_PORTC_PD_C10_SHIFT 10 -#define PORTCON_PORTC_PD_C10_WIDTH 1 -#define PORTCON_PORTC_PD_C10_MASK (((1U << PORTCON_PORTC_PD_C10_WIDTH) - 1U) << PORTCON_PORTC_PD_C10_SHIFT) -#define PORTCON_PORTC_PD_C10_DISABLE (0U << PORTCON_PORTC_PD_C10_SHIFT) -#define PORTCON_PORTC_PD_C10_ENABLE (1U << PORTCON_PORTC_PD_C10_SHIFT) - -#define PORTCON_PORTC_PD_C11_SHIFT 11 -#define PORTCON_PORTC_PD_C11_WIDTH 1 -#define PORTCON_PORTC_PD_C11_MASK (((1U << PORTCON_PORTC_PD_C11_WIDTH) - 1U) << PORTCON_PORTC_PD_C11_SHIFT) -#define PORTCON_PORTC_PD_C11_DISABLE (0U << PORTCON_PORTC_PD_C11_SHIFT) -#define PORTCON_PORTC_PD_C11_ENABLE (1U << PORTCON_PORTC_PD_C11_SHIFT) - -#define PORTCON_PORTC_PD_C12_SHIFT 12 -#define PORTCON_PORTC_PD_C12_WIDTH 1 -#define PORTCON_PORTC_PD_C12_MASK (((1U << PORTCON_PORTC_PD_C12_WIDTH) - 1U) << PORTCON_PORTC_PD_C12_SHIFT) -#define PORTCON_PORTC_PD_C12_DISABLE (0U << PORTCON_PORTC_PD_C12_SHIFT) -#define PORTCON_PORTC_PD_C12_ENABLE (1U << PORTCON_PORTC_PD_C12_SHIFT) - -#define PORTCON_PORTC_PD_C13_SHIFT 13 -#define PORTCON_PORTC_PD_C13_WIDTH 1 -#define PORTCON_PORTC_PD_C13_MASK (((1U << PORTCON_PORTC_PD_C13_WIDTH) - 1U) << PORTCON_PORTC_PD_C13_SHIFT) -#define PORTCON_PORTC_PD_C13_DISABLE (0U << PORTCON_PORTC_PD_C13_SHIFT) -#define PORTCON_PORTC_PD_C13_ENABLE (1U << PORTCON_PORTC_PD_C13_SHIFT) - -#define PORTCON_PORTC_PD_C14_SHIFT 14 -#define PORTCON_PORTC_PD_C14_WIDTH 1 -#define PORTCON_PORTC_PD_C14_MASK (((1U << PORTCON_PORTC_PD_C14_WIDTH) - 1U) << PORTCON_PORTC_PD_C14_SHIFT) -#define PORTCON_PORTC_PD_C14_DISABLE (0U << PORTCON_PORTC_PD_C14_SHIFT) -#define PORTCON_PORTC_PD_C14_ENABLE (1U << PORTCON_PORTC_PD_C14_SHIFT) - -#define PORTCON_PORTC_PD_C15_SHIFT 15 -#define PORTCON_PORTC_PD_C15_WIDTH 1 -#define PORTCON_PORTC_PD_C15_MASK (((1U << PORTCON_PORTC_PD_C15_WIDTH) - 1U) << PORTCON_PORTC_PD_C15_SHIFT) -#define PORTCON_PORTC_PD_C15_DISABLE (0U << PORTCON_PORTC_PD_C15_SHIFT) -#define PORTCON_PORTC_PD_C15_ENABLE (1U << PORTCON_PORTC_PD_C15_SHIFT) - -#define PORTCON_PORTA_OD_ADDR (PORTCON_BASE_ADDR + 0x0400U) -#define PORTCON_PORTA_OD (*(volatile uint32_t *)PORTCON_PORTA_OD_ADDR) -#define PORTCON_PORTA_OD_A0_SHIFT 0 -#define PORTCON_PORTA_OD_A0_WIDTH 1 -#define PORTCON_PORTA_OD_A0_MASK (((1U << PORTCON_PORTA_OD_A0_WIDTH) - 1U) << PORTCON_PORTA_OD_A0_SHIFT) -#define PORTCON_PORTA_OD_A0_DISABLE (0U << PORTCON_PORTA_OD_A0_SHIFT) -#define PORTCON_PORTA_OD_A0_ENABLE (1U << PORTCON_PORTA_OD_A0_SHIFT) - -#define PORTCON_PORTA_OD_A1_SHIFT 1 -#define PORTCON_PORTA_OD_A1_WIDTH 1 -#define PORTCON_PORTA_OD_A1_MASK (((1U << PORTCON_PORTA_OD_A1_WIDTH) - 1U) << PORTCON_PORTA_OD_A1_SHIFT) -#define PORTCON_PORTA_OD_A1_DISABLE (0U << PORTCON_PORTA_OD_A1_SHIFT) -#define PORTCON_PORTA_OD_A1_ENABLE (1U << PORTCON_PORTA_OD_A1_SHIFT) - -#define PORTCON_PORTA_OD_A2_SHIFT 2 -#define PORTCON_PORTA_OD_A2_WIDTH 1 -#define PORTCON_PORTA_OD_A2_MASK (((1U << PORTCON_PORTA_OD_A2_WIDTH) - 1U) << PORTCON_PORTA_OD_A2_SHIFT) -#define PORTCON_PORTA_OD_A2_DISABLE (0U << PORTCON_PORTA_OD_A2_SHIFT) -#define PORTCON_PORTA_OD_A2_ENABLE (1U << PORTCON_PORTA_OD_A2_SHIFT) - -#define PORTCON_PORTA_OD_A3_SHIFT 3 -#define PORTCON_PORTA_OD_A3_WIDTH 1 -#define PORTCON_PORTA_OD_A3_MASK (((1U << PORTCON_PORTA_OD_A3_WIDTH) - 1U) << PORTCON_PORTA_OD_A3_SHIFT) -#define PORTCON_PORTA_OD_A3_DISABLE (0U << PORTCON_PORTA_OD_A3_SHIFT) -#define PORTCON_PORTA_OD_A3_ENABLE (1U << PORTCON_PORTA_OD_A3_SHIFT) - -#define PORTCON_PORTA_OD_A4_SHIFT 4 -#define PORTCON_PORTA_OD_A4_WIDTH 1 -#define PORTCON_PORTA_OD_A4_MASK (((1U << PORTCON_PORTA_OD_A4_WIDTH) - 1U) << PORTCON_PORTA_OD_A4_SHIFT) -#define PORTCON_PORTA_OD_A4_DISABLE (0U << PORTCON_PORTA_OD_A4_SHIFT) -#define PORTCON_PORTA_OD_A4_ENABLE (1U << PORTCON_PORTA_OD_A4_SHIFT) - -#define PORTCON_PORTA_OD_A5_SHIFT 5 -#define PORTCON_PORTA_OD_A5_WIDTH 1 -#define PORTCON_PORTA_OD_A5_MASK (((1U << PORTCON_PORTA_OD_A5_WIDTH) - 1U) << PORTCON_PORTA_OD_A5_SHIFT) -#define PORTCON_PORTA_OD_A5_DISABLE (0U << PORTCON_PORTA_OD_A5_SHIFT) -#define PORTCON_PORTA_OD_A5_ENABLE (1U << PORTCON_PORTA_OD_A5_SHIFT) - -#define PORTCON_PORTA_OD_A6_SHIFT 6 -#define PORTCON_PORTA_OD_A6_WIDTH 1 -#define PORTCON_PORTA_OD_A6_MASK (((1U << PORTCON_PORTA_OD_A6_WIDTH) - 1U) << PORTCON_PORTA_OD_A6_SHIFT) -#define PORTCON_PORTA_OD_A6_DISABLE (0U << PORTCON_PORTA_OD_A6_SHIFT) -#define PORTCON_PORTA_OD_A6_ENABLE (1U << PORTCON_PORTA_OD_A6_SHIFT) - -#define PORTCON_PORTA_OD_A7_SHIFT 7 -#define PORTCON_PORTA_OD_A7_WIDTH 1 -#define PORTCON_PORTA_OD_A7_MASK (((1U << PORTCON_PORTA_OD_A7_WIDTH) - 1U) << PORTCON_PORTA_OD_A7_SHIFT) -#define PORTCON_PORTA_OD_A7_DISABLE (0U << PORTCON_PORTA_OD_A7_SHIFT) -#define PORTCON_PORTA_OD_A7_ENABLE (1U << PORTCON_PORTA_OD_A7_SHIFT) - -#define PORTCON_PORTA_OD_A8_SHIFT 8 -#define PORTCON_PORTA_OD_A8_WIDTH 1 -#define PORTCON_PORTA_OD_A8_MASK (((1U << PORTCON_PORTA_OD_A8_WIDTH) - 1U) << PORTCON_PORTA_OD_A8_SHIFT) -#define PORTCON_PORTA_OD_A8_DISABLE (0U << PORTCON_PORTA_OD_A8_SHIFT) -#define PORTCON_PORTA_OD_A8_ENABLE (1U << PORTCON_PORTA_OD_A8_SHIFT) - -#define PORTCON_PORTA_OD_A9_SHIFT 9 -#define PORTCON_PORTA_OD_A9_WIDTH 1 -#define PORTCON_PORTA_OD_A9_MASK (((1U << PORTCON_PORTA_OD_A9_WIDTH) - 1U) << PORTCON_PORTA_OD_A9_SHIFT) -#define PORTCON_PORTA_OD_A9_DISABLE (0U << PORTCON_PORTA_OD_A9_SHIFT) -#define PORTCON_PORTA_OD_A9_ENABLE (1U << PORTCON_PORTA_OD_A9_SHIFT) - -#define PORTCON_PORTA_OD_A10_SHIFT 10 -#define PORTCON_PORTA_OD_A10_WIDTH 1 -#define PORTCON_PORTA_OD_A10_MASK (((1U << PORTCON_PORTA_OD_A10_WIDTH) - 1U) << PORTCON_PORTA_OD_A10_SHIFT) -#define PORTCON_PORTA_OD_A10_DISABLE (0U << PORTCON_PORTA_OD_A10_SHIFT) -#define PORTCON_PORTA_OD_A10_ENABLE (1U << PORTCON_PORTA_OD_A10_SHIFT) - -#define PORTCON_PORTA_OD_A11_SHIFT 11 -#define PORTCON_PORTA_OD_A11_WIDTH 1 -#define PORTCON_PORTA_OD_A11_MASK (((1U << PORTCON_PORTA_OD_A11_WIDTH) - 1U) << PORTCON_PORTA_OD_A11_SHIFT) -#define PORTCON_PORTA_OD_A11_DISABLE (0U << PORTCON_PORTA_OD_A11_SHIFT) -#define PORTCON_PORTA_OD_A11_ENABLE (1U << PORTCON_PORTA_OD_A11_SHIFT) - -#define PORTCON_PORTA_OD_A12_SHIFT 12 -#define PORTCON_PORTA_OD_A12_WIDTH 1 -#define PORTCON_PORTA_OD_A12_MASK (((1U << PORTCON_PORTA_OD_A12_WIDTH) - 1U) << PORTCON_PORTA_OD_A12_SHIFT) -#define PORTCON_PORTA_OD_A12_DISABLE (0U << PORTCON_PORTA_OD_A12_SHIFT) -#define PORTCON_PORTA_OD_A12_ENABLE (1U << PORTCON_PORTA_OD_A12_SHIFT) - -#define PORTCON_PORTA_OD_A13_SHIFT 13 -#define PORTCON_PORTA_OD_A13_WIDTH 1 -#define PORTCON_PORTA_OD_A13_MASK (((1U << PORTCON_PORTA_OD_A13_WIDTH) - 1U) << PORTCON_PORTA_OD_A13_SHIFT) -#define PORTCON_PORTA_OD_A13_DISABLE (0U << PORTCON_PORTA_OD_A13_SHIFT) -#define PORTCON_PORTA_OD_A13_ENABLE (1U << PORTCON_PORTA_OD_A13_SHIFT) - -#define PORTCON_PORTA_OD_A14_SHIFT 14 -#define PORTCON_PORTA_OD_A14_WIDTH 1 -#define PORTCON_PORTA_OD_A14_MASK (((1U << PORTCON_PORTA_OD_A14_WIDTH) - 1U) << PORTCON_PORTA_OD_A14_SHIFT) -#define PORTCON_PORTA_OD_A14_DISABLE (0U << PORTCON_PORTA_OD_A14_SHIFT) -#define PORTCON_PORTA_OD_A14_ENABLE (1U << PORTCON_PORTA_OD_A14_SHIFT) - -#define PORTCON_PORTA_OD_A15_SHIFT 15 -#define PORTCON_PORTA_OD_A15_WIDTH 1 -#define PORTCON_PORTA_OD_A15_MASK (((1U << PORTCON_PORTA_OD_A15_WIDTH) - 1U) << PORTCON_PORTA_OD_A15_SHIFT) -#define PORTCON_PORTA_OD_A15_DISABLE (0U << PORTCON_PORTA_OD_A15_SHIFT) -#define PORTCON_PORTA_OD_A15_ENABLE (1U << PORTCON_PORTA_OD_A15_SHIFT) - -#define PORTCON_PORTB_OD_ADDR (PORTCON_BASE_ADDR + 0x0404U) -#define PORTCON_PORTB_OD (*(volatile uint32_t *)PORTCON_PORTB_OD_ADDR) -#define PORTCON_PORTB_OD_B0_SHIFT 0 -#define PORTCON_PORTB_OD_B0_WIDTH 1 -#define PORTCON_PORTB_OD_B0_MASK (((1U << PORTCON_PORTB_OD_B0_WIDTH) - 1U) << PORTCON_PORTB_OD_B0_SHIFT) -#define PORTCON_PORTB_OD_B0_DISABLE (0U << PORTCON_PORTB_OD_B0_SHIFT) -#define PORTCON_PORTB_OD_B0_ENABLE (1U << PORTCON_PORTB_OD_B0_SHIFT) - -#define PORTCON_PORTB_OD_B1_SHIFT 1 -#define PORTCON_PORTB_OD_B1_WIDTH 1 -#define PORTCON_PORTB_OD_B1_MASK (((1U << PORTCON_PORTB_OD_B1_WIDTH) - 1U) << PORTCON_PORTB_OD_B1_SHIFT) -#define PORTCON_PORTB_OD_B1_DISABLE (0U << PORTCON_PORTB_OD_B1_SHIFT) -#define PORTCON_PORTB_OD_B1_ENABLE (1U << PORTCON_PORTB_OD_B1_SHIFT) - -#define PORTCON_PORTB_OD_B2_SHIFT 2 -#define PORTCON_PORTB_OD_B2_WIDTH 1 -#define PORTCON_PORTB_OD_B2_MASK (((1U << PORTCON_PORTB_OD_B2_WIDTH) - 1U) << PORTCON_PORTB_OD_B2_SHIFT) -#define PORTCON_PORTB_OD_B2_DISABLE (0U << PORTCON_PORTB_OD_B2_SHIFT) -#define PORTCON_PORTB_OD_B2_ENABLE (1U << PORTCON_PORTB_OD_B2_SHIFT) - -#define PORTCON_PORTB_OD_B3_SHIFT 3 -#define PORTCON_PORTB_OD_B3_WIDTH 1 -#define PORTCON_PORTB_OD_B3_MASK (((1U << PORTCON_PORTB_OD_B3_WIDTH) - 1U) << PORTCON_PORTB_OD_B3_SHIFT) -#define PORTCON_PORTB_OD_B3_DISABLE (0U << PORTCON_PORTB_OD_B3_SHIFT) -#define PORTCON_PORTB_OD_B3_ENABLE (1U << PORTCON_PORTB_OD_B3_SHIFT) - -#define PORTCON_PORTB_OD_B4_SHIFT 4 -#define PORTCON_PORTB_OD_B4_WIDTH 1 -#define PORTCON_PORTB_OD_B4_MASK (((1U << PORTCON_PORTB_OD_B4_WIDTH) - 1U) << PORTCON_PORTB_OD_B4_SHIFT) -#define PORTCON_PORTB_OD_B4_DISABLE (0U << PORTCON_PORTB_OD_B4_SHIFT) -#define PORTCON_PORTB_OD_B4_ENABLE (1U << PORTCON_PORTB_OD_B4_SHIFT) - -#define PORTCON_PORTB_OD_B5_SHIFT 5 -#define PORTCON_PORTB_OD_B5_WIDTH 1 -#define PORTCON_PORTB_OD_B5_MASK (((1U << PORTCON_PORTB_OD_B5_WIDTH) - 1U) << PORTCON_PORTB_OD_B5_SHIFT) -#define PORTCON_PORTB_OD_B5_DISABLE (0U << PORTCON_PORTB_OD_B5_SHIFT) -#define PORTCON_PORTB_OD_B5_ENABLE (1U << PORTCON_PORTB_OD_B5_SHIFT) - -#define PORTCON_PORTB_OD_B6_SHIFT 6 -#define PORTCON_PORTB_OD_B6_WIDTH 1 -#define PORTCON_PORTB_OD_B6_MASK (((1U << PORTCON_PORTB_OD_B6_WIDTH) - 1U) << PORTCON_PORTB_OD_B6_SHIFT) -#define PORTCON_PORTB_OD_B6_DISABLE (0U << PORTCON_PORTB_OD_B6_SHIFT) -#define PORTCON_PORTB_OD_B6_ENABLE (1U << PORTCON_PORTB_OD_B6_SHIFT) - -#define PORTCON_PORTB_OD_B7_SHIFT 7 -#define PORTCON_PORTB_OD_B7_WIDTH 1 -#define PORTCON_PORTB_OD_B7_MASK (((1U << PORTCON_PORTB_OD_B7_WIDTH) - 1U) << PORTCON_PORTB_OD_B7_SHIFT) -#define PORTCON_PORTB_OD_B7_DISABLE (0U << PORTCON_PORTB_OD_B7_SHIFT) -#define PORTCON_PORTB_OD_B7_ENABLE (1U << PORTCON_PORTB_OD_B7_SHIFT) - -#define PORTCON_PORTB_OD_B8_SHIFT 8 -#define PORTCON_PORTB_OD_B8_WIDTH 1 -#define PORTCON_PORTB_OD_B8_MASK (((1U << PORTCON_PORTB_OD_B8_WIDTH) - 1U) << PORTCON_PORTB_OD_B8_SHIFT) -#define PORTCON_PORTB_OD_B8_DISABLE (0U << PORTCON_PORTB_OD_B8_SHIFT) -#define PORTCON_PORTB_OD_B8_ENABLE (1U << PORTCON_PORTB_OD_B8_SHIFT) - -#define PORTCON_PORTB_OD_B9_SHIFT 9 -#define PORTCON_PORTB_OD_B9_WIDTH 1 -#define PORTCON_PORTB_OD_B9_MASK (((1U << PORTCON_PORTB_OD_B9_WIDTH) - 1U) << PORTCON_PORTB_OD_B9_SHIFT) -#define PORTCON_PORTB_OD_B9_DISABLE (0U << PORTCON_PORTB_OD_B9_SHIFT) -#define PORTCON_PORTB_OD_B9_ENABLE (1U << PORTCON_PORTB_OD_B9_SHIFT) - -#define PORTCON_PORTB_OD_B10_SHIFT 10 -#define PORTCON_PORTB_OD_B10_WIDTH 1 -#define PORTCON_PORTB_OD_B10_MASK (((1U << PORTCON_PORTB_OD_B10_WIDTH) - 1U) << PORTCON_PORTB_OD_B10_SHIFT) -#define PORTCON_PORTB_OD_B10_DISABLE (0U << PORTCON_PORTB_OD_B10_SHIFT) -#define PORTCON_PORTB_OD_B10_ENABLE (1U << PORTCON_PORTB_OD_B10_SHIFT) - -#define PORTCON_PORTB_OD_B11_SHIFT 11 -#define PORTCON_PORTB_OD_B11_WIDTH 1 -#define PORTCON_PORTB_OD_B11_MASK (((1U << PORTCON_PORTB_OD_B11_WIDTH) - 1U) << PORTCON_PORTB_OD_B11_SHIFT) -#define PORTCON_PORTB_OD_B11_DISABLE (0U << PORTCON_PORTB_OD_B11_SHIFT) -#define PORTCON_PORTB_OD_B11_ENABLE (1U << PORTCON_PORTB_OD_B11_SHIFT) - -#define PORTCON_PORTB_OD_B12_SHIFT 12 -#define PORTCON_PORTB_OD_B12_WIDTH 1 -#define PORTCON_PORTB_OD_B12_MASK (((1U << PORTCON_PORTB_OD_B12_WIDTH) - 1U) << PORTCON_PORTB_OD_B12_SHIFT) -#define PORTCON_PORTB_OD_B12_DISABLE (0U << PORTCON_PORTB_OD_B12_SHIFT) -#define PORTCON_PORTB_OD_B12_ENABLE (1U << PORTCON_PORTB_OD_B12_SHIFT) - -#define PORTCON_PORTB_OD_B13_SHIFT 13 -#define PORTCON_PORTB_OD_B13_WIDTH 1 -#define PORTCON_PORTB_OD_B13_MASK (((1U << PORTCON_PORTB_OD_B13_WIDTH) - 1U) << PORTCON_PORTB_OD_B13_SHIFT) -#define PORTCON_PORTB_OD_B13_DISABLE (0U << PORTCON_PORTB_OD_B13_SHIFT) -#define PORTCON_PORTB_OD_B13_ENABLE (1U << PORTCON_PORTB_OD_B13_SHIFT) - -#define PORTCON_PORTB_OD_B14_SHIFT 14 -#define PORTCON_PORTB_OD_B14_WIDTH 1 -#define PORTCON_PORTB_OD_B14_MASK (((1U << PORTCON_PORTB_OD_B14_WIDTH) - 1U) << PORTCON_PORTB_OD_B14_SHIFT) -#define PORTCON_PORTB_OD_B14_DISABLE (0U << PORTCON_PORTB_OD_B14_SHIFT) -#define PORTCON_PORTB_OD_B14_ENABLE (1U << PORTCON_PORTB_OD_B14_SHIFT) - -#define PORTCON_PORTB_OD_B15_SHIFT 15 -#define PORTCON_PORTB_OD_B15_WIDTH 1 -#define PORTCON_PORTB_OD_B15_MASK (((1U << PORTCON_PORTB_OD_B15_WIDTH) - 1U) << PORTCON_PORTB_OD_B15_SHIFT) -#define PORTCON_PORTB_OD_B15_DISABLE (0U << PORTCON_PORTB_OD_B15_SHIFT) -#define PORTCON_PORTB_OD_B15_ENABLE (1U << PORTCON_PORTB_OD_B15_SHIFT) - -#define PORTCON_PORTC_OD_ADDR (PORTCON_BASE_ADDR + 0x0408U) -#define PORTCON_PORTC_OD (*(volatile uint32_t *)PORTCON_PORTC_OD_ADDR) -#define PORTCON_PORTC_OD_C0_SHIFT 0 -#define PORTCON_PORTC_OD_C0_WIDTH 1 -#define PORTCON_PORTC_OD_C0_MASK (((1U << PORTCON_PORTC_OD_C0_WIDTH) - 1U) << PORTCON_PORTC_OD_C0_SHIFT) -#define PORTCON_PORTC_OD_C0_DISABLE (0U << PORTCON_PORTC_OD_C0_SHIFT) -#define PORTCON_PORTC_OD_C0_ENABLE (1U << PORTCON_PORTC_OD_C0_SHIFT) - -#define PORTCON_PORTC_OD_C1_SHIFT 1 -#define PORTCON_PORTC_OD_C1_WIDTH 1 -#define PORTCON_PORTC_OD_C1_MASK (((1U << PORTCON_PORTC_OD_C1_WIDTH) - 1U) << PORTCON_PORTC_OD_C1_SHIFT) -#define PORTCON_PORTC_OD_C1_DISABLE (0U << PORTCON_PORTC_OD_C1_SHIFT) -#define PORTCON_PORTC_OD_C1_ENABLE (1U << PORTCON_PORTC_OD_C1_SHIFT) - -#define PORTCON_PORTC_OD_C2_SHIFT 2 -#define PORTCON_PORTC_OD_C2_WIDTH 1 -#define PORTCON_PORTC_OD_C2_MASK (((1U << PORTCON_PORTC_OD_C2_WIDTH) - 1U) << PORTCON_PORTC_OD_C2_SHIFT) -#define PORTCON_PORTC_OD_C2_DISABLE (0U << PORTCON_PORTC_OD_C2_SHIFT) -#define PORTCON_PORTC_OD_C2_ENABLE (1U << PORTCON_PORTC_OD_C2_SHIFT) - -#define PORTCON_PORTC_OD_C3_SHIFT 3 -#define PORTCON_PORTC_OD_C3_WIDTH 1 -#define PORTCON_PORTC_OD_C3_MASK (((1U << PORTCON_PORTC_OD_C3_WIDTH) - 1U) << PORTCON_PORTC_OD_C3_SHIFT) -#define PORTCON_PORTC_OD_C3_DISABLE (0U << PORTCON_PORTC_OD_C3_SHIFT) -#define PORTCON_PORTC_OD_C3_ENABLE (1U << PORTCON_PORTC_OD_C3_SHIFT) - -#define PORTCON_PORTC_OD_C4_SHIFT 4 -#define PORTCON_PORTC_OD_C4_WIDTH 1 -#define PORTCON_PORTC_OD_C4_MASK (((1U << PORTCON_PORTC_OD_C4_WIDTH) - 1U) << PORTCON_PORTC_OD_C4_SHIFT) -#define PORTCON_PORTC_OD_C4_DISABLE (0U << PORTCON_PORTC_OD_C4_SHIFT) -#define PORTCON_PORTC_OD_C4_ENABLE (1U << PORTCON_PORTC_OD_C4_SHIFT) - -#define PORTCON_PORTC_OD_C5_SHIFT 5 -#define PORTCON_PORTC_OD_C5_WIDTH 1 -#define PORTCON_PORTC_OD_C5_MASK (((1U << PORTCON_PORTC_OD_C5_WIDTH) - 1U) << PORTCON_PORTC_OD_C5_SHIFT) -#define PORTCON_PORTC_OD_C5_DISABLE (0U << PORTCON_PORTC_OD_C5_SHIFT) -#define PORTCON_PORTC_OD_C5_ENABLE (1U << PORTCON_PORTC_OD_C5_SHIFT) - -#define PORTCON_PORTC_OD_C6_SHIFT 6 -#define PORTCON_PORTC_OD_C6_WIDTH 1 -#define PORTCON_PORTC_OD_C6_MASK (((1U << PORTCON_PORTC_OD_C6_WIDTH) - 1U) << PORTCON_PORTC_OD_C6_SHIFT) -#define PORTCON_PORTC_OD_C6_DISABLE (0U << PORTCON_PORTC_OD_C6_SHIFT) -#define PORTCON_PORTC_OD_C6_ENABLE (1U << PORTCON_PORTC_OD_C6_SHIFT) - -#define PORTCON_PORTC_OD_C7_SHIFT 7 -#define PORTCON_PORTC_OD_C7_WIDTH 1 -#define PORTCON_PORTC_OD_C7_MASK (((1U << PORTCON_PORTC_OD_C7_WIDTH) - 1U) << PORTCON_PORTC_OD_C7_SHIFT) -#define PORTCON_PORTC_OD_C7_DISABLE (0U << PORTCON_PORTC_OD_C7_SHIFT) -#define PORTCON_PORTC_OD_C7_ENABLE (1U << PORTCON_PORTC_OD_C7_SHIFT) - -#define PORTCON_PORTC_OD_C8_SHIFT 8 -#define PORTCON_PORTC_OD_C8_WIDTH 1 -#define PORTCON_PORTC_OD_C8_MASK (((1U << PORTCON_PORTC_OD_C8_WIDTH) - 1U) << PORTCON_PORTC_OD_C8_SHIFT) -#define PORTCON_PORTC_OD_C8_DISABLE (0U << PORTCON_PORTC_OD_C8_SHIFT) -#define PORTCON_PORTC_OD_C8_ENABLE (1U << PORTCON_PORTC_OD_C8_SHIFT) - -#define PORTCON_PORTC_OD_C9_SHIFT 9 -#define PORTCON_PORTC_OD_C9_WIDTH 1 -#define PORTCON_PORTC_OD_C9_MASK (((1U << PORTCON_PORTC_OD_C9_WIDTH) - 1U) << PORTCON_PORTC_OD_C9_SHIFT) -#define PORTCON_PORTC_OD_C9_DISABLE (0U << PORTCON_PORTC_OD_C9_SHIFT) -#define PORTCON_PORTC_OD_C9_ENABLE (1U << PORTCON_PORTC_OD_C9_SHIFT) - -#define PORTCON_PORTC_OD_C10_SHIFT 10 -#define PORTCON_PORTC_OD_C10_WIDTH 1 -#define PORTCON_PORTC_OD_C10_MASK (((1U << PORTCON_PORTC_OD_C10_WIDTH) - 1U) << PORTCON_PORTC_OD_C10_SHIFT) -#define PORTCON_PORTC_OD_C10_DISABLE (0U << PORTCON_PORTC_OD_C10_SHIFT) -#define PORTCON_PORTC_OD_C10_ENABLE (1U << PORTCON_PORTC_OD_C10_SHIFT) - -#define PORTCON_PORTC_OD_C11_SHIFT 11 -#define PORTCON_PORTC_OD_C11_WIDTH 1 -#define PORTCON_PORTC_OD_C11_MASK (((1U << PORTCON_PORTC_OD_C11_WIDTH) - 1U) << PORTCON_PORTC_OD_C11_SHIFT) -#define PORTCON_PORTC_OD_C11_DISABLE (0U << PORTCON_PORTC_OD_C11_SHIFT) -#define PORTCON_PORTC_OD_C11_ENABLE (1U << PORTCON_PORTC_OD_C11_SHIFT) - -#define PORTCON_PORTC_OD_C12_SHIFT 12 -#define PORTCON_PORTC_OD_C12_WIDTH 1 -#define PORTCON_PORTC_OD_C12_MASK (((1U << PORTCON_PORTC_OD_C12_WIDTH) - 1U) << PORTCON_PORTC_OD_C12_SHIFT) -#define PORTCON_PORTC_OD_C12_DISABLE (0U << PORTCON_PORTC_OD_C12_SHIFT) -#define PORTCON_PORTC_OD_C12_ENABLE (1U << PORTCON_PORTC_OD_C12_SHIFT) - -#define PORTCON_PORTC_OD_C13_SHIFT 13 -#define PORTCON_PORTC_OD_C13_WIDTH 1 -#define PORTCON_PORTC_OD_C13_MASK (((1U << PORTCON_PORTC_OD_C13_WIDTH) - 1U) << PORTCON_PORTC_OD_C13_SHIFT) -#define PORTCON_PORTC_OD_C13_DISABLE (0U << PORTCON_PORTC_OD_C13_SHIFT) -#define PORTCON_PORTC_OD_C13_ENABLE (1U << PORTCON_PORTC_OD_C13_SHIFT) - -#define PORTCON_PORTC_OD_C14_SHIFT 14 -#define PORTCON_PORTC_OD_C14_WIDTH 1 -#define PORTCON_PORTC_OD_C14_MASK (((1U << PORTCON_PORTC_OD_C14_WIDTH) - 1U) << PORTCON_PORTC_OD_C14_SHIFT) -#define PORTCON_PORTC_OD_C14_DISABLE (0U << PORTCON_PORTC_OD_C14_SHIFT) -#define PORTCON_PORTC_OD_C14_ENABLE (1U << PORTCON_PORTC_OD_C14_SHIFT) - -#define PORTCON_PORTC_OD_C15_SHIFT 15 -#define PORTCON_PORTC_OD_C15_WIDTH 1 -#define PORTCON_PORTC_OD_C15_MASK (((1U << PORTCON_PORTC_OD_C15_WIDTH) - 1U) << PORTCON_PORTC_OD_C15_SHIFT) -#define PORTCON_PORTC_OD_C15_DISABLE (0U << PORTCON_PORTC_OD_C15_SHIFT) -#define PORTCON_PORTC_OD_C15_ENABLE (1U << PORTCON_PORTC_OD_C15_SHIFT) +#define PORTCON_BASE_ADDR 0x400B0000U +#define PORTCON_BASE_SIZE 0x00000800U + +#define PORTCON_PORTA_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0000U) +#define PORTCON_PORTA_SEL0 (*(volatile uint32_t *)PORTCON_PORTA_SEL0_ADDR) +#define PORTCON_PORTA_SEL0_A0_SHIFT 0 +#define PORTCON_PORTA_SEL0_A0_WIDTH 4 +#define PORTCON_PORTA_SEL0_A0_MASK (((1U << PORTCON_PORTA_SEL0_A0_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A0_SHIFT) +#define PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 0U +#define PORTCON_PORTA_SEL0_A0_BITS_GPIOA0 (PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 << PORTCON_PORTA_SEL0_A0_SHIFT) +#define PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 1U +#define PORTCON_PORTA_SEL0_A0_BITS_PWMP1_PLUS0 (PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 << PORTCON_PORTA_SEL0_A0_SHIFT) +#define PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 2U +#define PORTCON_PORTA_SEL0_A0_BITS_PWMP0_PLUS1 (PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 << PORTCON_PORTA_SEL0_A0_SHIFT) +#define PORTCON_PORTA_SEL0_A0_VALUE_TM 3U +#define PORTCON_PORTA_SEL0_A0_BITS_TM (PORTCON_PORTA_SEL0_A0_VALUE_TM << PORTCON_PORTA_SEL0_A0_SHIFT) +#define PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 4U +#define PORTCON_PORTA_SEL0_A0_BITS_WAKEUP0 (PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 << PORTCON_PORTA_SEL0_A0_SHIFT) + +#define PORTCON_PORTA_SEL0_A1_SHIFT 4 +#define PORTCON_PORTA_SEL0_A1_WIDTH 4 +#define PORTCON_PORTA_SEL0_A1_MASK (((1U << PORTCON_PORTA_SEL0_A1_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A1_SHIFT) +#define PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 0U +#define PORTCON_PORTA_SEL0_A1_BITS_GPIOA1 (PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 << PORTCON_PORTA_SEL0_A1_SHIFT) +#define PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI 1U +#define PORTCON_PORTA_SEL0_A1_BITS_XTAL_XI (PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI << PORTCON_PORTA_SEL0_A1_SHIFT) + +#define PORTCON_PORTA_SEL0_A2_SHIFT 8 +#define PORTCON_PORTA_SEL0_A2_WIDTH 4 +#define PORTCON_PORTA_SEL0_A2_MASK (((1U << PORTCON_PORTA_SEL0_A2_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A2_SHIFT) +#define PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 0U +#define PORTCON_PORTA_SEL0_A2_BITS_GPIOA2 (PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 << PORTCON_PORTA_SEL0_A2_SHIFT) +#define PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO 1U +#define PORTCON_PORTA_SEL0_A2_BITS_XTAL_XO (PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO << PORTCON_PORTA_SEL0_A2_SHIFT) + +#define PORTCON_PORTA_SEL0_A3_SHIFT 12 +#define PORTCON_PORTA_SEL0_A3_WIDTH 4 +#define PORTCON_PORTA_SEL0_A3_MASK (((1U << PORTCON_PORTA_SEL0_A3_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A3_SHIFT) +#define PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 0U +#define PORTCON_PORTA_SEL0_A3_BITS_GPIOA3 (PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 << PORTCON_PORTA_SEL0_A3_SHIFT) +#define PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN 1U +#define PORTCON_PORTA_SEL0_A3_BITS_CMP0_VN (PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN << PORTCON_PORTA_SEL0_A3_SHIFT) +#define PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI 2U +#define PORTCON_PORTA_SEL0_A3_BITS_XTAH_XI (PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI << PORTCON_PORTA_SEL0_A3_SHIFT) + +#define PORTCON_PORTA_SEL0_A4_SHIFT 16 +#define PORTCON_PORTA_SEL0_A4_WIDTH 4 +#define PORTCON_PORTA_SEL0_A4_MASK (((1U << PORTCON_PORTA_SEL0_A4_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A4_SHIFT) +#define PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 0U +#define PORTCON_PORTA_SEL0_A4_BITS_GPIOA4 (PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 << PORTCON_PORTA_SEL0_A4_SHIFT) +#define PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP 1U +#define PORTCON_PORTA_SEL0_A4_BITS_CMP0_VP (PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP << PORTCON_PORTA_SEL0_A4_SHIFT) +#define PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO 2U +#define PORTCON_PORTA_SEL0_A4_BITS_XTAH_XO (PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO << PORTCON_PORTA_SEL0_A4_SHIFT) + +#define PORTCON_PORTA_SEL0_A5_SHIFT 20 +#define PORTCON_PORTA_SEL0_A5_WIDTH 4 +#define PORTCON_PORTA_SEL0_A5_MASK (((1U << PORTCON_PORTA_SEL0_A5_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 0U +#define PORTCON_PORTA_SEL0_A5_BITS_GPIOA5 (PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS 1U +#define PORTCON_PORTA_SEL0_A5_BITS_UART1_CTS (PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 2U +#define PORTCON_PORTA_SEL0_A5_BITS_PWMP1_PLUS1 (PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 3U +#define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L 4U +#define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 5U +#define PORTCON_PORTA_SEL0_A5_BITS_WAKEUP1 (PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 << PORTCON_PORTA_SEL0_A5_SHIFT) +#define PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 6U +#define PORTCON_PORTA_SEL0_A5_BITS_SARADC_CH1 (PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A5_SHIFT) + +#define PORTCON_PORTA_SEL0_A6_SHIFT 24 +#define PORTCON_PORTA_SEL0_A6_WIDTH 4 +#define PORTCON_PORTA_SEL0_A6_MASK (((1U << PORTCON_PORTA_SEL0_A6_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A6_SHIFT) +#define PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 0U +#define PORTCON_PORTA_SEL0_A6_BITS_GPIOA6 (PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 << PORTCON_PORTA_SEL0_A6_SHIFT) +#define PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS 1U +#define PORTCON_PORTA_SEL0_A6_BITS_UART1_RTS (PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS << PORTCON_PORTA_SEL0_A6_SHIFT) +#define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 2U +#define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL0_A6_SHIFT) +#define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H 3U +#define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL0_A6_SHIFT) +#define PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 4U +#define PORTCON_PORTA_SEL0_A6_BITS_SARADC_CH1 (PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A6_SHIFT) +#define PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT 5U +#define PORTCON_PORTA_SEL0_A6_BITS_OPA0_OUT (PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT << PORTCON_PORTA_SEL0_A6_SHIFT) + +#define PORTCON_PORTA_SEL0_A7_SHIFT 28 +#define PORTCON_PORTA_SEL0_A7_WIDTH 4 +#define PORTCON_PORTA_SEL0_A7_MASK (((1U << PORTCON_PORTA_SEL0_A7_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A7_SHIFT) +#define PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 0U +#define PORTCON_PORTA_SEL0_A7_BITS_GPIOA7 (PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 << PORTCON_PORTA_SEL0_A7_SHIFT) +#define PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX 1U +#define PORTCON_PORTA_SEL0_A7_BITS_UART1_TX (PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX << PORTCON_PORTA_SEL0_A7_SHIFT) +#define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 2U +#define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_IN0 (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL0_A7_SHIFT) +#define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L 3U +#define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_OUT_L (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL0_A7_SHIFT) +#define PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 4U +#define PORTCON_PORTA_SEL0_A7_BITS_SARADC_CH2 (PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 << PORTCON_PORTA_SEL0_A7_SHIFT) +#define PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP 5U +#define PORTCON_PORTA_SEL0_A7_BITS_OPA0_VP (PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP << PORTCON_PORTA_SEL0_A7_SHIFT) + +#define PORTCON_PORTA_SEL1_ADDR (PORTCON_BASE_ADDR + 0x0004U) +#define PORTCON_PORTA_SEL1 (*(volatile uint32_t *)PORTCON_PORTA_SEL1_ADDR) +#define PORTCON_PORTA_SEL1_A8_SHIFT 0 +#define PORTCON_PORTA_SEL1_A8_WIDTH 4 +#define PORTCON_PORTA_SEL1_A8_MASK (((1U << PORTCON_PORTA_SEL1_A8_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A8_SHIFT) +#define PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 0U +#define PORTCON_PORTA_SEL1_A8_BITS_GPIOA8 (PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 << PORTCON_PORTA_SEL1_A8_SHIFT) +#define PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX 1U +#define PORTCON_PORTA_SEL1_A8_BITS_UART1_RX (PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX << PORTCON_PORTA_SEL1_A8_SHIFT) +#define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 2U +#define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_IN1 (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A8_SHIFT) +#define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H 3U +#define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_OUT_H (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A8_SHIFT) +#define PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 4U +#define PORTCON_PORTA_SEL1_A8_BITS_SARADC_CH3 (PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 << PORTCON_PORTA_SEL1_A8_SHIFT) +#define PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN 5U +#define PORTCON_PORTA_SEL1_A8_BITS_OPA0_VN (PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN << PORTCON_PORTA_SEL1_A8_SHIFT) + +#define PORTCON_PORTA_SEL1_A9_SHIFT 4 +#define PORTCON_PORTA_SEL1_A9_WIDTH 4 +#define PORTCON_PORTA_SEL1_A9_MASK (((1U << PORTCON_PORTA_SEL1_A9_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 0U +#define PORTCON_PORTA_SEL1_A9_BITS_GPIOA9 (PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN 1U +#define PORTCON_PORTA_SEL1_A9_BITS_SPI0_SSN (PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 2U +#define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L 3U +#define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_TM 4U +#define PORTCON_PORTA_SEL1_A9_BITS_TM (PORTCON_PORTA_SEL1_A9_VALUE_TM << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 5U +#define PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4 (PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 << PORTCON_PORTA_SEL1_A9_SHIFT) +#define PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN 6U +#define PORTCON_PORTA_SEL1_A9_BITS_CMP1_VN (PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN << PORTCON_PORTA_SEL1_A9_SHIFT) + +#define PORTCON_PORTA_SEL1_A10_SHIFT 8 +#define PORTCON_PORTA_SEL1_A10_WIDTH 4 +#define PORTCON_PORTA_SEL1_A10_MASK (((1U << PORTCON_PORTA_SEL1_A10_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A10_SHIFT) +#define PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 0U +#define PORTCON_PORTA_SEL1_A10_BITS_GPIOA10 (PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 << PORTCON_PORTA_SEL1_A10_SHIFT) +#define PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK 1U +#define PORTCON_PORTA_SEL1_A10_BITS_SPI0_CLK (PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK << PORTCON_PORTA_SEL1_A10_SHIFT) +#define PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 2U +#define PORTCON_PORTA_SEL1_A10_BITS_SARADC_CH5 (PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 << PORTCON_PORTA_SEL1_A10_SHIFT) +#define PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP 3U +#define PORTCON_PORTA_SEL1_A10_BITS_CMP1_VP (PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP << PORTCON_PORTA_SEL1_A10_SHIFT) + +#define PORTCON_PORTA_SEL1_A11_SHIFT 12 +#define PORTCON_PORTA_SEL1_A11_WIDTH 4 +#define PORTCON_PORTA_SEL1_A11_MASK (((1U << PORTCON_PORTA_SEL1_A11_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 0U +#define PORTCON_PORTA_SEL1_A11_BITS_GPIOA11 (PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO 1U +#define PORTCON_PORTA_SEL1_A11_BITS_SPI0_MISO (PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 2U +#define PORTCON_PORTA_SEL1_A11_BITS_PWMB0_CH0 (PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 3U +#define PORTCON_PORTA_SEL1_A11_BITS_PWMP0_BRAKE0 (PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 4U +#define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H 5U +#define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A11_SHIFT) +#define PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 6U +#define PORTCON_PORTA_SEL1_A11_BITS_SARADC_CH6 (PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 << PORTCON_PORTA_SEL1_A11_SHIFT) + +#define PORTCON_PORTA_SEL1_A12_SHIFT 16 +#define PORTCON_PORTA_SEL1_A12_WIDTH 4 +#define PORTCON_PORTA_SEL1_A12_MASK (((1U << PORTCON_PORTA_SEL1_A12_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 0U +#define PORTCON_PORTA_SEL1_A12_BITS_GPIOA12 (PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI 1U +#define PORTCON_PORTA_SEL1_A12_BITS_SPI0_MOSI (PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 2U +#define PORTCON_PORTA_SEL1_A12_BITS_PWMB0_CH1 (PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N 3U +#define PORTCON_PORTA_SEL1_A12_BITS_PWMP0_CH0N (PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 4U +#define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_IN0 (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L 5U +#define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_OUT_L (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL1_A12_SHIFT) +#define PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 6U +#define PORTCON_PORTA_SEL1_A12_BITS_SARADC_CH7 (PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 << PORTCON_PORTA_SEL1_A12_SHIFT) + +#define PORTCON_PORTA_SEL1_A13_SHIFT 20 +#define PORTCON_PORTA_SEL1_A13_WIDTH 4 +#define PORTCON_PORTA_SEL1_A13_MASK (((1U << PORTCON_PORTA_SEL1_A13_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A13_SHIFT) +#define PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 0U +#define PORTCON_PORTA_SEL1_A13_BITS_GPIOA13 (PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 << PORTCON_PORTA_SEL1_A13_SHIFT) +#define PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 1U +#define PORTCON_PORTA_SEL1_A13_BITS_PWMB0_CH2 (PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 << PORTCON_PORTA_SEL1_A13_SHIFT) +#define PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N 2U +#define PORTCON_PORTA_SEL1_A13_BITS_PWMP0_CH1N (PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N << PORTCON_PORTA_SEL1_A13_SHIFT) +#define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 3U +#define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_IN1 (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A13_SHIFT) +#define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H 4U +#define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_OUT_H (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A13_SHIFT) +#define PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 5U +#define PORTCON_PORTA_SEL1_A13_BITS_SARADC_CH8 (PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 << PORTCON_PORTA_SEL1_A13_SHIFT) + +#define PORTCON_PORTA_SEL1_A14_SHIFT 24 +#define PORTCON_PORTA_SEL1_A14_WIDTH 4 +#define PORTCON_PORTA_SEL1_A14_MASK (((1U << PORTCON_PORTA_SEL1_A14_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A14_SHIFT) +#define PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 0U +#define PORTCON_PORTA_SEL1_A14_BITS_GPIOA14 (PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 << PORTCON_PORTA_SEL1_A14_SHIFT) +#define PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 1U +#define PORTCON_PORTA_SEL1_A14_BITS_PWMB1_CH0 (PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 << PORTCON_PORTA_SEL1_A14_SHIFT) +#define PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N 2U +#define PORTCON_PORTA_SEL1_A14_BITS_PWMP0_CH2N (PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N << PORTCON_PORTA_SEL1_A14_SHIFT) +#define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 3U +#define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A14_SHIFT) +#define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L 4U +#define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A14_SHIFT) +#define PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 5U +#define PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9 (PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 << PORTCON_PORTA_SEL1_A14_SHIFT) + +#define PORTCON_PORTA_SEL1_A15_SHIFT 28 +#define PORTCON_PORTA_SEL1_A15_WIDTH 4 +#define PORTCON_PORTA_SEL1_A15_MASK (((1U << PORTCON_PORTA_SEL1_A15_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A15_SHIFT) +#define PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 0U +#define PORTCON_PORTA_SEL1_A15_BITS_GPIOA15 (PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 << PORTCON_PORTA_SEL1_A15_SHIFT) +#define PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 1U +#define PORTCON_PORTA_SEL1_A15_BITS_PWMB1_CH1 (PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 << PORTCON_PORTA_SEL1_A15_SHIFT) +#define PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 2U +#define PORTCON_PORTA_SEL1_A15_BITS_PWMP0_CH0 (PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 << PORTCON_PORTA_SEL1_A15_SHIFT) +#define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 3U +#define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A15_SHIFT) +#define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H 4U +#define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A15_SHIFT) + +#define PORTCON_PORTB_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0008U) +#define PORTCON_PORTB_SEL0 (*(volatile uint32_t *)PORTCON_PORTB_SEL0_ADDR) +#define PORTCON_PORTB_SEL0_B0_SHIFT 0 +#define PORTCON_PORTB_SEL0_B0_WIDTH 4 +#define PORTCON_PORTB_SEL0_B0_MASK (((1U << PORTCON_PORTB_SEL0_B0_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B0_SHIFT) +#define PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 0U +#define PORTCON_PORTB_SEL0_B0_BITS_GPIOB0 (PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 << PORTCON_PORTB_SEL0_B0_SHIFT) +#define PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX 1U +#define PORTCON_PORTB_SEL0_B0_BITS_UART2_TX (PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX << PORTCON_PORTB_SEL0_B0_SHIFT) +#define PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL 2U +#define PORTCON_PORTB_SEL0_B0_BITS_IIC0_SCL (PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B0_SHIFT) +#define PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 3U +#define PORTCON_PORTB_SEL0_B0_BITS_PWMB1_CH2 (PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 << PORTCON_PORTB_SEL0_B0_SHIFT) +#define PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 4U +#define PORTCON_PORTB_SEL0_B0_BITS_PWMP0_CH1 (PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B0_SHIFT) + +#define PORTCON_PORTB_SEL0_B1_SHIFT 4 +#define PORTCON_PORTB_SEL0_B1_WIDTH 4 +#define PORTCON_PORTB_SEL0_B1_MASK (((1U << PORTCON_PORTB_SEL0_B1_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B1_SHIFT) +#define PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 0U +#define PORTCON_PORTB_SEL0_B1_BITS_GPIOB1 (PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 << PORTCON_PORTB_SEL0_B1_SHIFT) +#define PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX 1U +#define PORTCON_PORTB_SEL0_B1_BITS_UART2_RX (PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX << PORTCON_PORTB_SEL0_B1_SHIFT) +#define PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA 2U +#define PORTCON_PORTB_SEL0_B1_BITS_IIC0_SDA (PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA << PORTCON_PORTB_SEL0_B1_SHIFT) +#define PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 3U +#define PORTCON_PORTB_SEL0_B1_BITS_PWMP0_CH2 (PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL0_B1_SHIFT) + +#define PORTCON_PORTB_SEL0_B2_SHIFT 8 +#define PORTCON_PORTB_SEL0_B2_WIDTH 4 +#define PORTCON_PORTB_SEL0_B2_MASK (((1U << PORTCON_PORTB_SEL0_B2_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B2_SHIFT) +#define PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 0U +#define PORTCON_PORTB_SEL0_B2_BITS_GPIOB2 (PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 << PORTCON_PORTB_SEL0_B2_SHIFT) +#define PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN 1U +#define PORTCON_PORTB_SEL0_B2_BITS_SPI1_SSN (PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN << PORTCON_PORTB_SEL0_B2_SHIFT) +#define PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 2U +#define PORTCON_PORTB_SEL0_B2_BITS_PWMP0_BRAKE1 (PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 << PORTCON_PORTB_SEL0_B2_SHIFT) +#define PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 3U +#define PORTCON_PORTB_SEL0_B2_BITS_TIMERP1_HALL0 (PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 << PORTCON_PORTB_SEL0_B2_SHIFT) + +#define PORTCON_PORTB_SEL0_B3_SHIFT 12 +#define PORTCON_PORTB_SEL0_B3_WIDTH 4 +#define PORTCON_PORTB_SEL0_B3_MASK (((1U << PORTCON_PORTB_SEL0_B3_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B3_SHIFT) +#define PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 0U +#define PORTCON_PORTB_SEL0_B3_BITS_GPIOB3 (PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 << PORTCON_PORTB_SEL0_B3_SHIFT) +#define PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK 1U +#define PORTCON_PORTB_SEL0_B3_BITS_SPI1_CLK (PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK << PORTCON_PORTB_SEL0_B3_SHIFT) +#define PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA 2U +#define PORTCON_PORTB_SEL0_B3_BITS_IIC1_SDA (PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA << PORTCON_PORTB_SEL0_B3_SHIFT) +#define PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N 3U +#define PORTCON_PORTB_SEL0_B3_BITS_PWMP0_CH0N (PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N << PORTCON_PORTB_SEL0_B3_SHIFT) +#define PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 4U +#define PORTCON_PORTB_SEL0_B3_BITS_TIMERP1_HALL1 (PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 << PORTCON_PORTB_SEL0_B3_SHIFT) + +#define PORTCON_PORTB_SEL0_B4_SHIFT 16 +#define PORTCON_PORTB_SEL0_B4_WIDTH 4 +#define PORTCON_PORTB_SEL0_B4_MASK (((1U << PORTCON_PORTB_SEL0_B4_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B4_SHIFT) +#define PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 0U +#define PORTCON_PORTB_SEL0_B4_BITS_GPIOB4 (PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 << PORTCON_PORTB_SEL0_B4_SHIFT) +#define PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO 1U +#define PORTCON_PORTB_SEL0_B4_BITS_SPI1_MISO (PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO << PORTCON_PORTB_SEL0_B4_SHIFT) +#define PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL 2U +#define PORTCON_PORTB_SEL0_B4_BITS_IIC1_SCL (PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL << PORTCON_PORTB_SEL0_B4_SHIFT) +#define PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 3U +#define PORTCON_PORTB_SEL0_B4_BITS_PWMP1_CH0 (PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL0_B4_SHIFT) +#define PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N 4U +#define PORTCON_PORTB_SEL0_B4_BITS_PWMP0_CH1N (PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N << PORTCON_PORTB_SEL0_B4_SHIFT) +#define PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 5U +#define PORTCON_PORTB_SEL0_B4_BITS_TIMERP1_HALL2 (PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 << PORTCON_PORTB_SEL0_B4_SHIFT) + +#define PORTCON_PORTB_SEL0_B5_SHIFT 20 +#define PORTCON_PORTB_SEL0_B5_WIDTH 4 +#define PORTCON_PORTB_SEL0_B5_MASK (((1U << PORTCON_PORTB_SEL0_B5_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B5_SHIFT) +#define PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 0U +#define PORTCON_PORTB_SEL0_B5_BITS_GPIOB5 (PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 << PORTCON_PORTB_SEL0_B5_SHIFT) +#define PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI 1U +#define PORTCON_PORTB_SEL0_B5_BITS_SPI1_MOSI (PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI << PORTCON_PORTB_SEL0_B5_SHIFT) +#define PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N 2U +#define PORTCON_PORTB_SEL0_B5_BITS_PWMP1_CH0N (PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL0_B5_SHIFT) +#define PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N 3U +#define PORTCON_PORTB_SEL0_B5_BITS_PWMP0_CH2N (PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N << PORTCON_PORTB_SEL0_B5_SHIFT) +#define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 4U +#define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_IN0 (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 << PORTCON_PORTB_SEL0_B5_SHIFT) +#define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L 5U +#define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_OUT_L (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L << PORTCON_PORTB_SEL0_B5_SHIFT) + +#define PORTCON_PORTB_SEL0_B6_SHIFT 24 +#define PORTCON_PORTB_SEL0_B6_WIDTH 4 +#define PORTCON_PORTB_SEL0_B6_MASK (((1U << PORTCON_PORTB_SEL0_B6_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B6_SHIFT) +#define PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 0U +#define PORTCON_PORTB_SEL0_B6_BITS_GPIOB6 (PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 << PORTCON_PORTB_SEL0_B6_SHIFT) +#define PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 1U +#define PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0 (PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 << PORTCON_PORTB_SEL0_B6_SHIFT) +#define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 2U +#define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_IN1 (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 << PORTCON_PORTB_SEL0_B6_SHIFT) +#define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H 3U +#define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_OUT_H (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H << PORTCON_PORTB_SEL0_B6_SHIFT) + +#define PORTCON_PORTB_SEL0_B7_SHIFT 28 +#define PORTCON_PORTB_SEL0_B7_WIDTH 4 +#define PORTCON_PORTB_SEL0_B7_MASK (((1U << PORTCON_PORTB_SEL0_B7_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B7_SHIFT) +#define PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 0U +#define PORTCON_PORTB_SEL0_B7_BITS_GPIOB7 (PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 << PORTCON_PORTB_SEL0_B7_SHIFT) +#define PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN 1U +#define PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN (PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN << PORTCON_PORTB_SEL0_B7_SHIFT) +#define PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX 2U +#define PORTCON_PORTB_SEL0_B7_BITS_UART0_TX (PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX << PORTCON_PORTB_SEL0_B7_SHIFT) +#define PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL 3U +#define PORTCON_PORTB_SEL0_B7_BITS_IIC0_SCL (PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B7_SHIFT) +#define PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 4U +#define PORTCON_PORTB_SEL0_B7_BITS_PWMP1_BRAKE0 (PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 << PORTCON_PORTB_SEL0_B7_SHIFT) +#define PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 5U +#define PORTCON_PORTB_SEL0_B7_BITS_PWMP0_CH1 (PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B7_SHIFT) + +#define PORTCON_PORTB_SEL1_ADDR (PORTCON_BASE_ADDR + 0x000CU) +#define PORTCON_PORTB_SEL1 (*(volatile uint32_t *)PORTCON_PORTB_SEL1_ADDR) +#define PORTCON_PORTB_SEL1_B8_SHIFT 0 +#define PORTCON_PORTB_SEL1_B8_WIDTH 4 +#define PORTCON_PORTB_SEL1_B8_MASK (((1U << PORTCON_PORTB_SEL1_B8_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 0U +#define PORTCON_PORTB_SEL1_B8_BITS_GPIOB8 (PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK 1U +#define PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK (PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX 2U +#define PORTCON_PORTB_SEL1_B8_BITS_UART0_RX (PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA 3U +#define PORTCON_PORTB_SEL1_B8_BITS_IIC0_SDA (PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 4U +#define PORTCON_PORTB_SEL1_B8_BITS_PWMB0_CH0 (PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 5U +#define PORTCON_PORTB_SEL1_B8_BITS_PWMP1_BRAKE1 (PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 << PORTCON_PORTB_SEL1_B8_SHIFT) +#define PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 6U +#define PORTCON_PORTB_SEL1_B8_BITS_PWMP0_CH2 (PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL1_B8_SHIFT) + +#define PORTCON_PORTB_SEL1_B9_SHIFT 4 +#define PORTCON_PORTB_SEL1_B9_WIDTH 4 +#define PORTCON_PORTB_SEL1_B9_MASK (((1U << PORTCON_PORTB_SEL1_B9_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 0U +#define PORTCON_PORTB_SEL1_B9_BITS_GPIOB9 (PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO 1U +#define PORTCON_PORTB_SEL1_B9_BITS_SPI0_MISO (PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS 2U +#define PORTCON_PORTB_SEL1_B9_BITS_UART0_CTS (PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 3U +#define PORTCON_PORTB_SEL1_B9_BITS_PWMB0_CH1 (PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 4U +#define PORTCON_PORTB_SEL1_B9_BITS_PWMP1_CH0 (PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 5U +#define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_IN1 (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 << PORTCON_PORTB_SEL1_B9_SHIFT) +#define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H 6U +#define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_OUT_H (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H << PORTCON_PORTB_SEL1_B9_SHIFT) + +#define PORTCON_PORTB_SEL1_B10_SHIFT 8 +#define PORTCON_PORTB_SEL1_B10_WIDTH 4 +#define PORTCON_PORTB_SEL1_B10_MASK (((1U << PORTCON_PORTB_SEL1_B10_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 0U +#define PORTCON_PORTB_SEL1_B10_BITS_GPIOB10 (PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI 1U +#define PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI (PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS 2U +#define PORTCON_PORTB_SEL1_B10_BITS_UART0_RTS (PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 3U +#define PORTCON_PORTB_SEL1_B10_BITS_PWMB0_CH2 (PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 4U +#define PORTCON_PORTB_SEL1_B10_BITS_PWMP1_CH1 (PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 5U +#define PORTCON_PORTB_SEL1_B10_BITS_PWMP0_PLUS0 (PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 6U +#define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_IN0 (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 << PORTCON_PORTB_SEL1_B10_SHIFT) +#define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L 7U +#define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_OUT_L (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L << PORTCON_PORTB_SEL1_B10_SHIFT) + +#define PORTCON_PORTB_SEL1_B11_SHIFT 12 +#define PORTCON_PORTB_SEL1_B11_WIDTH 4 +#define PORTCON_PORTB_SEL1_B11_MASK (((1U << PORTCON_PORTB_SEL1_B11_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B11_SHIFT) +#define PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 0U +#define PORTCON_PORTB_SEL1_B11_BITS_GPIOB11 (PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 << PORTCON_PORTB_SEL1_B11_SHIFT) +#define PORTCON_PORTB_SEL1_B11_VALUE_SWDIO 1U +#define PORTCON_PORTB_SEL1_B11_BITS_SWDIO (PORTCON_PORTB_SEL1_B11_VALUE_SWDIO << PORTCON_PORTB_SEL1_B11_SHIFT) +#define PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 2U +#define PORTCON_PORTB_SEL1_B11_BITS_PWMP1_CH2 (PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 << PORTCON_PORTB_SEL1_B11_SHIFT) +#define PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 3U +#define PORTCON_PORTB_SEL1_B11_BITS_PWMP0_BRAKE2 (PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 << PORTCON_PORTB_SEL1_B11_SHIFT) + +#define PORTCON_PORTB_SEL1_B12_SHIFT 16 +#define PORTCON_PORTB_SEL1_B12_WIDTH 4 +#define PORTCON_PORTB_SEL1_B12_MASK (((1U << PORTCON_PORTB_SEL1_B12_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B12_SHIFT) +#define PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 0U +#define PORTCON_PORTB_SEL1_B12_BITS_GPIOB12 (PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 << PORTCON_PORTB_SEL1_B12_SHIFT) +#define PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX 1U +#define PORTCON_PORTB_SEL1_B12_BITS_UART1_TX (PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX << PORTCON_PORTB_SEL1_B12_SHIFT) +#define PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL 2U +#define PORTCON_PORTB_SEL1_B12_BITS_IIC1_SCL (PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL << PORTCON_PORTB_SEL1_B12_SHIFT) +#define PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N 3U +#define PORTCON_PORTB_SEL1_B12_BITS_PWMP1_CH0N (PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL1_B12_SHIFT) + +#define PORTCON_PORTB_SEL1_B13_SHIFT 20 +#define PORTCON_PORTB_SEL1_B13_WIDTH 4 +#define PORTCON_PORTB_SEL1_B13_MASK (((1U << PORTCON_PORTB_SEL1_B13_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B13_SHIFT) +#define PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 0U +#define PORTCON_PORTB_SEL1_B13_BITS_GPIOB13 (PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 << PORTCON_PORTB_SEL1_B13_SHIFT) +#define PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX 1U +#define PORTCON_PORTB_SEL1_B13_BITS_UART1_RX (PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX << PORTCON_PORTB_SEL1_B13_SHIFT) +#define PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA 2U +#define PORTCON_PORTB_SEL1_B13_BITS_IIC1_SDA (PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA << PORTCON_PORTB_SEL1_B13_SHIFT) +#define PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N 3U +#define PORTCON_PORTB_SEL1_B13_BITS_PWMP1_CH1N (PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N << PORTCON_PORTB_SEL1_B13_SHIFT) + +#define PORTCON_PORTB_SEL1_B14_SHIFT 24 +#define PORTCON_PORTB_SEL1_B14_WIDTH 4 +#define PORTCON_PORTB_SEL1_B14_MASK (((1U << PORTCON_PORTB_SEL1_B14_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B14_SHIFT) +#define PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 0U +#define PORTCON_PORTB_SEL1_B14_BITS_GPIOB14 (PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 << PORTCON_PORTB_SEL1_B14_SHIFT) +#define PORTCON_PORTB_SEL1_B14_VALUE_SWCLK 1U +#define PORTCON_PORTB_SEL1_B14_BITS_SWCLK (PORTCON_PORTB_SEL1_B14_VALUE_SWCLK << PORTCON_PORTB_SEL1_B14_SHIFT) +#define PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX 2U +#define PORTCON_PORTB_SEL1_B14_BITS_UART2_TX (PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX << PORTCON_PORTB_SEL1_B14_SHIFT) +#define PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N 3U +#define PORTCON_PORTB_SEL1_B14_BITS_PWMP1_CH2N (PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N << PORTCON_PORTB_SEL1_B14_SHIFT) + +#define PORTCON_PORTB_SEL1_B15_SHIFT 28 +#define PORTCON_PORTB_SEL1_B15_WIDTH 4 +#define PORTCON_PORTB_SEL1_B15_MASK (((1U << PORTCON_PORTB_SEL1_B15_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B15_SHIFT) +#define PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 0U +#define PORTCON_PORTB_SEL1_B15_BITS_GPIOB15 (PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 << PORTCON_PORTB_SEL1_B15_SHIFT) +#define PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN 1U +#define PORTCON_PORTB_SEL1_B15_BITS_SPI1_SSN (PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN << PORTCON_PORTB_SEL1_B15_SHIFT) +#define PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX 2U +#define PORTCON_PORTB_SEL1_B15_BITS_UART2_RX (PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX << PORTCON_PORTB_SEL1_B15_SHIFT) + +#define PORTCON_PORTC_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0010U) +#define PORTCON_PORTC_SEL0 (*(volatile uint32_t *)PORTCON_PORTC_SEL0_ADDR) +#define PORTCON_PORTC_SEL0_C0_SHIFT 0 +#define PORTCON_PORTC_SEL0_C0_WIDTH 4 +#define PORTCON_PORTC_SEL0_C0_MASK (((1U << PORTCON_PORTC_SEL0_C0_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C0_SHIFT) +#define PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 0U +#define PORTCON_PORTC_SEL0_C0_BITS_GPIOC0 (PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 << PORTCON_PORTC_SEL0_C0_SHIFT) +#define PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK 1U +#define PORTCON_PORTC_SEL0_C0_BITS_SPI1_CLK (PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK << PORTCON_PORTC_SEL0_C0_SHIFT) +#define PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS 2U +#define PORTCON_PORTC_SEL0_C0_BITS_UART2_CTS (PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS << PORTCON_PORTC_SEL0_C0_SHIFT) +#define PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 3U +#define PORTCON_PORTC_SEL0_C0_BITS_PWMB1_CH0 (PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 << PORTCON_PORTC_SEL0_C0_SHIFT) + +#define PORTCON_PORTC_SEL0_C1_SHIFT 4 +#define PORTCON_PORTC_SEL0_C1_WIDTH 4 +#define PORTCON_PORTC_SEL0_C1_MASK (((1U << PORTCON_PORTC_SEL0_C1_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C1_SHIFT) +#define PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 0U +#define PORTCON_PORTC_SEL0_C1_BITS_GPIOC1 (PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 << PORTCON_PORTC_SEL0_C1_SHIFT) +#define PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO 1U +#define PORTCON_PORTC_SEL0_C1_BITS_SPI1_MISO (PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO << PORTCON_PORTC_SEL0_C1_SHIFT) +#define PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS 2U +#define PORTCON_PORTC_SEL0_C1_BITS_UART2_RTS (PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS << PORTCON_PORTC_SEL0_C1_SHIFT) +#define PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 3U +#define PORTCON_PORTC_SEL0_C1_BITS_PWMB1_CH1 (PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 << PORTCON_PORTC_SEL0_C1_SHIFT) +#define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 4U +#define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_IN0 (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 << PORTCON_PORTC_SEL0_C1_SHIFT) +#define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L 5U +#define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_OUT_L (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L << PORTCON_PORTC_SEL0_C1_SHIFT) + +#define PORTCON_PORTC_SEL0_C2_SHIFT 8 +#define PORTCON_PORTC_SEL0_C2_WIDTH 4 +#define PORTCON_PORTC_SEL0_C2_MASK (((1U << PORTCON_PORTC_SEL0_C2_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C2_SHIFT) +#define PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 0U +#define PORTCON_PORTC_SEL0_C2_BITS_GPIOC2 (PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 << PORTCON_PORTC_SEL0_C2_SHIFT) +#define PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI 1U +#define PORTCON_PORTC_SEL0_C2_BITS_SPI1_MOSI (PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI << PORTCON_PORTC_SEL0_C2_SHIFT) +#define PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 2U +#define PORTCON_PORTC_SEL0_C2_BITS_PWMB1_CH2 (PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 << PORTCON_PORTC_SEL0_C2_SHIFT) +#define PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 3U +#define PORTCON_PORTC_SEL0_C2_BITS_PWMP1_BRAKE2 (PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 << PORTCON_PORTC_SEL0_C2_SHIFT) +#define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 4U +#define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_IN1 (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 << PORTCON_PORTC_SEL0_C2_SHIFT) +#define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H 5U +#define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_OUT_H (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H << PORTCON_PORTC_SEL0_C2_SHIFT) + +#define PORTCON_PORTC_SEL0_C3_SHIFT 12 +#define PORTCON_PORTC_SEL0_C3_WIDTH 4 +#define PORTCON_PORTC_SEL0_C3_MASK (((1U << PORTCON_PORTC_SEL0_C3_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C3_SHIFT) +#define PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 0U +#define PORTCON_PORTC_SEL0_C3_BITS_GPIOC3 (PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 << PORTCON_PORTC_SEL0_C3_SHIFT) +#define PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX 1U +#define PORTCON_PORTC_SEL0_C3_BITS_UART0_TX (PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX << PORTCON_PORTC_SEL0_C3_SHIFT) +#define PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL 2U +#define PORTCON_PORTC_SEL0_C3_BITS_IIC0_SCL (PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL << PORTCON_PORTC_SEL0_C3_SHIFT) +#define PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N 3U +#define PORTCON_PORTC_SEL0_C3_BITS_PWMP1_CH1N (PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N << PORTCON_PORTC_SEL0_C3_SHIFT) +#define PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 4U +#define PORTCON_PORTC_SEL0_C3_BITS_TIMERP0_HALL0 (PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 << PORTCON_PORTC_SEL0_C3_SHIFT) +#define PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN 5U +#define PORTCON_PORTC_SEL0_C3_BITS_CMP2_VN (PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN << PORTCON_PORTC_SEL0_C3_SHIFT) + +#define PORTCON_PORTC_SEL0_C4_SHIFT 16 +#define PORTCON_PORTC_SEL0_C4_WIDTH 4 +#define PORTCON_PORTC_SEL0_C4_MASK (((1U << PORTCON_PORTC_SEL0_C4_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C4_SHIFT) +#define PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 0U +#define PORTCON_PORTC_SEL0_C4_BITS_GPIOC4 (PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 << PORTCON_PORTC_SEL0_C4_SHIFT) +#define PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX 1U +#define PORTCON_PORTC_SEL0_C4_BITS_UART0_RX (PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX << PORTCON_PORTC_SEL0_C4_SHIFT) +#define PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA 2U +#define PORTCON_PORTC_SEL0_C4_BITS_IIC0_SDA (PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA << PORTCON_PORTC_SEL0_C4_SHIFT) +#define PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N 3U +#define PORTCON_PORTC_SEL0_C4_BITS_PWMP1_CH2N (PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N << PORTCON_PORTC_SEL0_C4_SHIFT) +#define PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 4U +#define PORTCON_PORTC_SEL0_C4_BITS_TIMERP0_HALL1 (PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 << PORTCON_PORTC_SEL0_C4_SHIFT) +#define PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP 5U +#define PORTCON_PORTC_SEL0_C4_BITS_CMP2_VP (PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP << PORTCON_PORTC_SEL0_C4_SHIFT) + +#define PORTCON_PORTC_SEL0_C5_SHIFT 20 +#define PORTCON_PORTC_SEL0_C5_WIDTH 4 +#define PORTCON_PORTC_SEL0_C5_MASK (((1U << PORTCON_PORTC_SEL0_C5_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C5_SHIFT) +#define PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 0U +#define PORTCON_PORTC_SEL0_C5_BITS_GPIOC5 (PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 << PORTCON_PORTC_SEL0_C5_SHIFT) +#define PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 1U +#define PORTCON_PORTC_SEL0_C5_BITS_TIMERP0_HALL2 (PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 << PORTCON_PORTC_SEL0_C5_SHIFT) +#define PORTCON_PORTC_SEL0_C5_VALUE_TM 2U +#define PORTCON_PORTC_SEL0_C5_BITS_TM (PORTCON_PORTC_SEL0_C5_VALUE_TM << PORTCON_PORTC_SEL0_C5_SHIFT) +#define PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP 3U +#define PORTCON_PORTC_SEL0_C5_BITS_OPA1_VP (PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP << PORTCON_PORTC_SEL0_C5_SHIFT) + +#define PORTCON_PORTC_SEL0_C6_SHIFT 24 +#define PORTCON_PORTC_SEL0_C6_WIDTH 4 +#define PORTCON_PORTC_SEL0_C6_MASK (((1U << PORTCON_PORTC_SEL0_C6_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C6_SHIFT) +#define PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 0U +#define PORTCON_PORTC_SEL0_C6_BITS_GPIOC6 (PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 << PORTCON_PORTC_SEL0_C6_SHIFT) +#define PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL 1U +#define PORTCON_PORTC_SEL0_C6_BITS_IIC1_SCL (PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL << PORTCON_PORTC_SEL0_C6_SHIFT) +#define PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 2U +#define PORTCON_PORTC_SEL0_C6_BITS_PWMP1_CH1 (PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 << PORTCON_PORTC_SEL0_C6_SHIFT) +#define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 3U +#define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_IN1 (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 << PORTCON_PORTC_SEL0_C6_SHIFT) +#define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H 4U +#define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_OUT_H (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H << PORTCON_PORTC_SEL0_C6_SHIFT) +#define PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN 5U +#define PORTCON_PORTC_SEL0_C6_BITS_OPA1_VN (PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN << PORTCON_PORTC_SEL0_C6_SHIFT) + +#define PORTCON_PORTC_SEL0_C7_SHIFT 28 +#define PORTCON_PORTC_SEL0_C7_WIDTH 4 +#define PORTCON_PORTC_SEL0_C7_MASK (((1U << PORTCON_PORTC_SEL0_C7_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C7_SHIFT) +#define PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 0U +#define PORTCON_PORTC_SEL0_C7_BITS_GPIOC7 (PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 << PORTCON_PORTC_SEL0_C7_SHIFT) +#define PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA 1U +#define PORTCON_PORTC_SEL0_C7_BITS_IIC1_SDA (PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA << PORTCON_PORTC_SEL0_C7_SHIFT) +#define PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 2U +#define PORTCON_PORTC_SEL0_C7_BITS_PWMP1_CH2 (PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 << PORTCON_PORTC_SEL0_C7_SHIFT) +#define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 3U +#define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_IN0 (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 << PORTCON_PORTC_SEL0_C7_SHIFT) +#define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L 4U +#define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_OUT_L (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L << PORTCON_PORTC_SEL0_C7_SHIFT) +#define PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT 5U +#define PORTCON_PORTC_SEL0_C7_BITS_OPA1_OUT (PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT << PORTCON_PORTC_SEL0_C7_SHIFT) + +#define PORTCON_PORTA_IE_ADDR (PORTCON_BASE_ADDR + 0x0100U) +#define PORTCON_PORTA_IE (*(volatile uint32_t *)PORTCON_PORTA_IE_ADDR) +#define PORTCON_PORTA_IE_A0_SHIFT 0 +#define PORTCON_PORTA_IE_A0_WIDTH 1 +#define PORTCON_PORTA_IE_A0_MASK (((1U << PORTCON_PORTA_IE_A0_WIDTH) - 1U) << PORTCON_PORTA_IE_A0_SHIFT) +#define PORTCON_PORTA_IE_A0_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A0_BITS_DISABLE (PORTCON_PORTA_IE_A0_VALUE_DISABLE << PORTCON_PORTA_IE_A0_SHIFT) +#define PORTCON_PORTA_IE_A0_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A0_BITS_ENABLE (PORTCON_PORTA_IE_A0_VALUE_ENABLE << PORTCON_PORTA_IE_A0_SHIFT) + +#define PORTCON_PORTA_IE_A1_SHIFT 1 +#define PORTCON_PORTA_IE_A1_WIDTH 1 +#define PORTCON_PORTA_IE_A1_MASK (((1U << PORTCON_PORTA_IE_A1_WIDTH) - 1U) << PORTCON_PORTA_IE_A1_SHIFT) +#define PORTCON_PORTA_IE_A1_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A1_BITS_DISABLE (PORTCON_PORTA_IE_A1_VALUE_DISABLE << PORTCON_PORTA_IE_A1_SHIFT) +#define PORTCON_PORTA_IE_A1_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A1_BITS_ENABLE (PORTCON_PORTA_IE_A1_VALUE_ENABLE << PORTCON_PORTA_IE_A1_SHIFT) + +#define PORTCON_PORTA_IE_A2_SHIFT 2 +#define PORTCON_PORTA_IE_A2_WIDTH 1 +#define PORTCON_PORTA_IE_A2_MASK (((1U << PORTCON_PORTA_IE_A2_WIDTH) - 1U) << PORTCON_PORTA_IE_A2_SHIFT) +#define PORTCON_PORTA_IE_A2_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A2_BITS_DISABLE (PORTCON_PORTA_IE_A2_VALUE_DISABLE << PORTCON_PORTA_IE_A2_SHIFT) +#define PORTCON_PORTA_IE_A2_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A2_BITS_ENABLE (PORTCON_PORTA_IE_A2_VALUE_ENABLE << PORTCON_PORTA_IE_A2_SHIFT) + +#define PORTCON_PORTA_IE_A3_SHIFT 3 +#define PORTCON_PORTA_IE_A3_WIDTH 1 +#define PORTCON_PORTA_IE_A3_MASK (((1U << PORTCON_PORTA_IE_A3_WIDTH) - 1U) << PORTCON_PORTA_IE_A3_SHIFT) +#define PORTCON_PORTA_IE_A3_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A3_BITS_DISABLE (PORTCON_PORTA_IE_A3_VALUE_DISABLE << PORTCON_PORTA_IE_A3_SHIFT) +#define PORTCON_PORTA_IE_A3_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A3_BITS_ENABLE (PORTCON_PORTA_IE_A3_VALUE_ENABLE << PORTCON_PORTA_IE_A3_SHIFT) + +#define PORTCON_PORTA_IE_A4_SHIFT 4 +#define PORTCON_PORTA_IE_A4_WIDTH 1 +#define PORTCON_PORTA_IE_A4_MASK (((1U << PORTCON_PORTA_IE_A4_WIDTH) - 1U) << PORTCON_PORTA_IE_A4_SHIFT) +#define PORTCON_PORTA_IE_A4_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A4_BITS_DISABLE (PORTCON_PORTA_IE_A4_VALUE_DISABLE << PORTCON_PORTA_IE_A4_SHIFT) +#define PORTCON_PORTA_IE_A4_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A4_BITS_ENABLE (PORTCON_PORTA_IE_A4_VALUE_ENABLE << PORTCON_PORTA_IE_A4_SHIFT) + +#define PORTCON_PORTA_IE_A5_SHIFT 5 +#define PORTCON_PORTA_IE_A5_WIDTH 1 +#define PORTCON_PORTA_IE_A5_MASK (((1U << PORTCON_PORTA_IE_A5_WIDTH) - 1U) << PORTCON_PORTA_IE_A5_SHIFT) +#define PORTCON_PORTA_IE_A5_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A5_BITS_DISABLE (PORTCON_PORTA_IE_A5_VALUE_DISABLE << PORTCON_PORTA_IE_A5_SHIFT) +#define PORTCON_PORTA_IE_A5_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A5_BITS_ENABLE (PORTCON_PORTA_IE_A5_VALUE_ENABLE << PORTCON_PORTA_IE_A5_SHIFT) + +#define PORTCON_PORTA_IE_A6_SHIFT 6 +#define PORTCON_PORTA_IE_A6_WIDTH 1 +#define PORTCON_PORTA_IE_A6_MASK (((1U << PORTCON_PORTA_IE_A6_WIDTH) - 1U) << PORTCON_PORTA_IE_A6_SHIFT) +#define PORTCON_PORTA_IE_A6_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A6_BITS_DISABLE (PORTCON_PORTA_IE_A6_VALUE_DISABLE << PORTCON_PORTA_IE_A6_SHIFT) +#define PORTCON_PORTA_IE_A6_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A6_BITS_ENABLE (PORTCON_PORTA_IE_A6_VALUE_ENABLE << PORTCON_PORTA_IE_A6_SHIFT) + +#define PORTCON_PORTA_IE_A7_SHIFT 7 +#define PORTCON_PORTA_IE_A7_WIDTH 1 +#define PORTCON_PORTA_IE_A7_MASK (((1U << PORTCON_PORTA_IE_A7_WIDTH) - 1U) << PORTCON_PORTA_IE_A7_SHIFT) +#define PORTCON_PORTA_IE_A7_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A7_BITS_DISABLE (PORTCON_PORTA_IE_A7_VALUE_DISABLE << PORTCON_PORTA_IE_A7_SHIFT) +#define PORTCON_PORTA_IE_A7_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A7_BITS_ENABLE (PORTCON_PORTA_IE_A7_VALUE_ENABLE << PORTCON_PORTA_IE_A7_SHIFT) + +#define PORTCON_PORTA_IE_A8_SHIFT 8 +#define PORTCON_PORTA_IE_A8_WIDTH 1 +#define PORTCON_PORTA_IE_A8_MASK (((1U << PORTCON_PORTA_IE_A8_WIDTH) - 1U) << PORTCON_PORTA_IE_A8_SHIFT) +#define PORTCON_PORTA_IE_A8_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A8_BITS_DISABLE (PORTCON_PORTA_IE_A8_VALUE_DISABLE << PORTCON_PORTA_IE_A8_SHIFT) +#define PORTCON_PORTA_IE_A8_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A8_BITS_ENABLE (PORTCON_PORTA_IE_A8_VALUE_ENABLE << PORTCON_PORTA_IE_A8_SHIFT) + +#define PORTCON_PORTA_IE_A9_SHIFT 9 +#define PORTCON_PORTA_IE_A9_WIDTH 1 +#define PORTCON_PORTA_IE_A9_MASK (((1U << PORTCON_PORTA_IE_A9_WIDTH) - 1U) << PORTCON_PORTA_IE_A9_SHIFT) +#define PORTCON_PORTA_IE_A9_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A9_BITS_DISABLE (PORTCON_PORTA_IE_A9_VALUE_DISABLE << PORTCON_PORTA_IE_A9_SHIFT) +#define PORTCON_PORTA_IE_A9_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A9_BITS_ENABLE (PORTCON_PORTA_IE_A9_VALUE_ENABLE << PORTCON_PORTA_IE_A9_SHIFT) + +#define PORTCON_PORTA_IE_A10_SHIFT 10 +#define PORTCON_PORTA_IE_A10_WIDTH 1 +#define PORTCON_PORTA_IE_A10_MASK (((1U << PORTCON_PORTA_IE_A10_WIDTH) - 1U) << PORTCON_PORTA_IE_A10_SHIFT) +#define PORTCON_PORTA_IE_A10_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A10_BITS_DISABLE (PORTCON_PORTA_IE_A10_VALUE_DISABLE << PORTCON_PORTA_IE_A10_SHIFT) +#define PORTCON_PORTA_IE_A10_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A10_BITS_ENABLE (PORTCON_PORTA_IE_A10_VALUE_ENABLE << PORTCON_PORTA_IE_A10_SHIFT) + +#define PORTCON_PORTA_IE_A11_SHIFT 11 +#define PORTCON_PORTA_IE_A11_WIDTH 1 +#define PORTCON_PORTA_IE_A11_MASK (((1U << PORTCON_PORTA_IE_A11_WIDTH) - 1U) << PORTCON_PORTA_IE_A11_SHIFT) +#define PORTCON_PORTA_IE_A11_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A11_BITS_DISABLE (PORTCON_PORTA_IE_A11_VALUE_DISABLE << PORTCON_PORTA_IE_A11_SHIFT) +#define PORTCON_PORTA_IE_A11_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A11_BITS_ENABLE (PORTCON_PORTA_IE_A11_VALUE_ENABLE << PORTCON_PORTA_IE_A11_SHIFT) + +#define PORTCON_PORTA_IE_A12_SHIFT 12 +#define PORTCON_PORTA_IE_A12_WIDTH 1 +#define PORTCON_PORTA_IE_A12_MASK (((1U << PORTCON_PORTA_IE_A12_WIDTH) - 1U) << PORTCON_PORTA_IE_A12_SHIFT) +#define PORTCON_PORTA_IE_A12_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A12_BITS_DISABLE (PORTCON_PORTA_IE_A12_VALUE_DISABLE << PORTCON_PORTA_IE_A12_SHIFT) +#define PORTCON_PORTA_IE_A12_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A12_BITS_ENABLE (PORTCON_PORTA_IE_A12_VALUE_ENABLE << PORTCON_PORTA_IE_A12_SHIFT) + +#define PORTCON_PORTA_IE_A13_SHIFT 13 +#define PORTCON_PORTA_IE_A13_WIDTH 1 +#define PORTCON_PORTA_IE_A13_MASK (((1U << PORTCON_PORTA_IE_A13_WIDTH) - 1U) << PORTCON_PORTA_IE_A13_SHIFT) +#define PORTCON_PORTA_IE_A13_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A13_BITS_DISABLE (PORTCON_PORTA_IE_A13_VALUE_DISABLE << PORTCON_PORTA_IE_A13_SHIFT) +#define PORTCON_PORTA_IE_A13_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A13_BITS_ENABLE (PORTCON_PORTA_IE_A13_VALUE_ENABLE << PORTCON_PORTA_IE_A13_SHIFT) + +#define PORTCON_PORTA_IE_A14_SHIFT 14 +#define PORTCON_PORTA_IE_A14_WIDTH 1 +#define PORTCON_PORTA_IE_A14_MASK (((1U << PORTCON_PORTA_IE_A14_WIDTH) - 1U) << PORTCON_PORTA_IE_A14_SHIFT) +#define PORTCON_PORTA_IE_A14_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A14_BITS_DISABLE (PORTCON_PORTA_IE_A14_VALUE_DISABLE << PORTCON_PORTA_IE_A14_SHIFT) +#define PORTCON_PORTA_IE_A14_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A14_BITS_ENABLE (PORTCON_PORTA_IE_A14_VALUE_ENABLE << PORTCON_PORTA_IE_A14_SHIFT) + +#define PORTCON_PORTA_IE_A15_SHIFT 15 +#define PORTCON_PORTA_IE_A15_WIDTH 1 +#define PORTCON_PORTA_IE_A15_MASK (((1U << PORTCON_PORTA_IE_A15_WIDTH) - 1U) << PORTCON_PORTA_IE_A15_SHIFT) +#define PORTCON_PORTA_IE_A15_VALUE_DISABLE 0U +#define PORTCON_PORTA_IE_A15_BITS_DISABLE (PORTCON_PORTA_IE_A15_VALUE_DISABLE << PORTCON_PORTA_IE_A15_SHIFT) +#define PORTCON_PORTA_IE_A15_VALUE_ENABLE 1U +#define PORTCON_PORTA_IE_A15_BITS_ENABLE (PORTCON_PORTA_IE_A15_VALUE_ENABLE << PORTCON_PORTA_IE_A15_SHIFT) + +#define PORTCON_PORTB_IE_ADDR (PORTCON_BASE_ADDR + 0x0104U) +#define PORTCON_PORTB_IE (*(volatile uint32_t *)PORTCON_PORTB_IE_ADDR) +#define PORTCON_PORTB_IE_B0_SHIFT 0 +#define PORTCON_PORTB_IE_B0_WIDTH 1 +#define PORTCON_PORTB_IE_B0_MASK (((1U << PORTCON_PORTB_IE_B0_WIDTH) - 1U) << PORTCON_PORTB_IE_B0_SHIFT) +#define PORTCON_PORTB_IE_B0_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B0_BITS_DISABLE (PORTCON_PORTB_IE_B0_VALUE_DISABLE << PORTCON_PORTB_IE_B0_SHIFT) +#define PORTCON_PORTB_IE_B0_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B0_BITS_ENABLE (PORTCON_PORTB_IE_B0_VALUE_ENABLE << PORTCON_PORTB_IE_B0_SHIFT) + +#define PORTCON_PORTB_IE_B1_SHIFT 1 +#define PORTCON_PORTB_IE_B1_WIDTH 1 +#define PORTCON_PORTB_IE_B1_MASK (((1U << PORTCON_PORTB_IE_B1_WIDTH) - 1U) << PORTCON_PORTB_IE_B1_SHIFT) +#define PORTCON_PORTB_IE_B1_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B1_BITS_DISABLE (PORTCON_PORTB_IE_B1_VALUE_DISABLE << PORTCON_PORTB_IE_B1_SHIFT) +#define PORTCON_PORTB_IE_B1_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B1_BITS_ENABLE (PORTCON_PORTB_IE_B1_VALUE_ENABLE << PORTCON_PORTB_IE_B1_SHIFT) + +#define PORTCON_PORTB_IE_B2_SHIFT 2 +#define PORTCON_PORTB_IE_B2_WIDTH 1 +#define PORTCON_PORTB_IE_B2_MASK (((1U << PORTCON_PORTB_IE_B2_WIDTH) - 1U) << PORTCON_PORTB_IE_B2_SHIFT) +#define PORTCON_PORTB_IE_B2_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B2_BITS_DISABLE (PORTCON_PORTB_IE_B2_VALUE_DISABLE << PORTCON_PORTB_IE_B2_SHIFT) +#define PORTCON_PORTB_IE_B2_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B2_BITS_ENABLE (PORTCON_PORTB_IE_B2_VALUE_ENABLE << PORTCON_PORTB_IE_B2_SHIFT) + +#define PORTCON_PORTB_IE_B3_SHIFT 3 +#define PORTCON_PORTB_IE_B3_WIDTH 1 +#define PORTCON_PORTB_IE_B3_MASK (((1U << PORTCON_PORTB_IE_B3_WIDTH) - 1U) << PORTCON_PORTB_IE_B3_SHIFT) +#define PORTCON_PORTB_IE_B3_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B3_BITS_DISABLE (PORTCON_PORTB_IE_B3_VALUE_DISABLE << PORTCON_PORTB_IE_B3_SHIFT) +#define PORTCON_PORTB_IE_B3_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B3_BITS_ENABLE (PORTCON_PORTB_IE_B3_VALUE_ENABLE << PORTCON_PORTB_IE_B3_SHIFT) + +#define PORTCON_PORTB_IE_B4_SHIFT 4 +#define PORTCON_PORTB_IE_B4_WIDTH 1 +#define PORTCON_PORTB_IE_B4_MASK (((1U << PORTCON_PORTB_IE_B4_WIDTH) - 1U) << PORTCON_PORTB_IE_B4_SHIFT) +#define PORTCON_PORTB_IE_B4_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B4_BITS_DISABLE (PORTCON_PORTB_IE_B4_VALUE_DISABLE << PORTCON_PORTB_IE_B4_SHIFT) +#define PORTCON_PORTB_IE_B4_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B4_BITS_ENABLE (PORTCON_PORTB_IE_B4_VALUE_ENABLE << PORTCON_PORTB_IE_B4_SHIFT) + +#define PORTCON_PORTB_IE_B5_SHIFT 5 +#define PORTCON_PORTB_IE_B5_WIDTH 1 +#define PORTCON_PORTB_IE_B5_MASK (((1U << PORTCON_PORTB_IE_B5_WIDTH) - 1U) << PORTCON_PORTB_IE_B5_SHIFT) +#define PORTCON_PORTB_IE_B5_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B5_BITS_DISABLE (PORTCON_PORTB_IE_B5_VALUE_DISABLE << PORTCON_PORTB_IE_B5_SHIFT) +#define PORTCON_PORTB_IE_B5_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B5_BITS_ENABLE (PORTCON_PORTB_IE_B5_VALUE_ENABLE << PORTCON_PORTB_IE_B5_SHIFT) + +#define PORTCON_PORTB_IE_B6_SHIFT 6 +#define PORTCON_PORTB_IE_B6_WIDTH 1 +#define PORTCON_PORTB_IE_B6_MASK (((1U << PORTCON_PORTB_IE_B6_WIDTH) - 1U) << PORTCON_PORTB_IE_B6_SHIFT) +#define PORTCON_PORTB_IE_B6_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B6_BITS_DISABLE (PORTCON_PORTB_IE_B6_VALUE_DISABLE << PORTCON_PORTB_IE_B6_SHIFT) +#define PORTCON_PORTB_IE_B6_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B6_BITS_ENABLE (PORTCON_PORTB_IE_B6_VALUE_ENABLE << PORTCON_PORTB_IE_B6_SHIFT) + +#define PORTCON_PORTB_IE_B7_SHIFT 7 +#define PORTCON_PORTB_IE_B7_WIDTH 1 +#define PORTCON_PORTB_IE_B7_MASK (((1U << PORTCON_PORTB_IE_B7_WIDTH) - 1U) << PORTCON_PORTB_IE_B7_SHIFT) +#define PORTCON_PORTB_IE_B7_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B7_BITS_DISABLE (PORTCON_PORTB_IE_B7_VALUE_DISABLE << PORTCON_PORTB_IE_B7_SHIFT) +#define PORTCON_PORTB_IE_B7_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B7_BITS_ENABLE (PORTCON_PORTB_IE_B7_VALUE_ENABLE << PORTCON_PORTB_IE_B7_SHIFT) + +#define PORTCON_PORTB_IE_B8_SHIFT 8 +#define PORTCON_PORTB_IE_B8_WIDTH 1 +#define PORTCON_PORTB_IE_B8_MASK (((1U << PORTCON_PORTB_IE_B8_WIDTH) - 1U) << PORTCON_PORTB_IE_B8_SHIFT) +#define PORTCON_PORTB_IE_B8_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B8_BITS_DISABLE (PORTCON_PORTB_IE_B8_VALUE_DISABLE << PORTCON_PORTB_IE_B8_SHIFT) +#define PORTCON_PORTB_IE_B8_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B8_BITS_ENABLE (PORTCON_PORTB_IE_B8_VALUE_ENABLE << PORTCON_PORTB_IE_B8_SHIFT) + +#define PORTCON_PORTB_IE_B9_SHIFT 9 +#define PORTCON_PORTB_IE_B9_WIDTH 1 +#define PORTCON_PORTB_IE_B9_MASK (((1U << PORTCON_PORTB_IE_B9_WIDTH) - 1U) << PORTCON_PORTB_IE_B9_SHIFT) +#define PORTCON_PORTB_IE_B9_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B9_BITS_DISABLE (PORTCON_PORTB_IE_B9_VALUE_DISABLE << PORTCON_PORTB_IE_B9_SHIFT) +#define PORTCON_PORTB_IE_B9_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B9_BITS_ENABLE (PORTCON_PORTB_IE_B9_VALUE_ENABLE << PORTCON_PORTB_IE_B9_SHIFT) + +#define PORTCON_PORTB_IE_B10_SHIFT 10 +#define PORTCON_PORTB_IE_B10_WIDTH 1 +#define PORTCON_PORTB_IE_B10_MASK (((1U << PORTCON_PORTB_IE_B10_WIDTH) - 1U) << PORTCON_PORTB_IE_B10_SHIFT) +#define PORTCON_PORTB_IE_B10_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B10_BITS_DISABLE (PORTCON_PORTB_IE_B10_VALUE_DISABLE << PORTCON_PORTB_IE_B10_SHIFT) +#define PORTCON_PORTB_IE_B10_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B10_BITS_ENABLE (PORTCON_PORTB_IE_B10_VALUE_ENABLE << PORTCON_PORTB_IE_B10_SHIFT) + +#define PORTCON_PORTB_IE_B11_SHIFT 11 +#define PORTCON_PORTB_IE_B11_WIDTH 1 +#define PORTCON_PORTB_IE_B11_MASK (((1U << PORTCON_PORTB_IE_B11_WIDTH) - 1U) << PORTCON_PORTB_IE_B11_SHIFT) +#define PORTCON_PORTB_IE_B11_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B11_BITS_DISABLE (PORTCON_PORTB_IE_B11_VALUE_DISABLE << PORTCON_PORTB_IE_B11_SHIFT) +#define PORTCON_PORTB_IE_B11_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B11_BITS_ENABLE (PORTCON_PORTB_IE_B11_VALUE_ENABLE << PORTCON_PORTB_IE_B11_SHIFT) + +#define PORTCON_PORTB_IE_B12_SHIFT 12 +#define PORTCON_PORTB_IE_B12_WIDTH 1 +#define PORTCON_PORTB_IE_B12_MASK (((1U << PORTCON_PORTB_IE_B12_WIDTH) - 1U) << PORTCON_PORTB_IE_B12_SHIFT) +#define PORTCON_PORTB_IE_B12_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B12_BITS_DISABLE (PORTCON_PORTB_IE_B12_VALUE_DISABLE << PORTCON_PORTB_IE_B12_SHIFT) +#define PORTCON_PORTB_IE_B12_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B12_BITS_ENABLE (PORTCON_PORTB_IE_B12_VALUE_ENABLE << PORTCON_PORTB_IE_B12_SHIFT) + +#define PORTCON_PORTB_IE_B13_SHIFT 13 +#define PORTCON_PORTB_IE_B13_WIDTH 1 +#define PORTCON_PORTB_IE_B13_MASK (((1U << PORTCON_PORTB_IE_B13_WIDTH) - 1U) << PORTCON_PORTB_IE_B13_SHIFT) +#define PORTCON_PORTB_IE_B13_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B13_BITS_DISABLE (PORTCON_PORTB_IE_B13_VALUE_DISABLE << PORTCON_PORTB_IE_B13_SHIFT) +#define PORTCON_PORTB_IE_B13_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B13_BITS_ENABLE (PORTCON_PORTB_IE_B13_VALUE_ENABLE << PORTCON_PORTB_IE_B13_SHIFT) + +#define PORTCON_PORTB_IE_B14_SHIFT 14 +#define PORTCON_PORTB_IE_B14_WIDTH 1 +#define PORTCON_PORTB_IE_B14_MASK (((1U << PORTCON_PORTB_IE_B14_WIDTH) - 1U) << PORTCON_PORTB_IE_B14_SHIFT) +#define PORTCON_PORTB_IE_B14_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B14_BITS_DISABLE (PORTCON_PORTB_IE_B14_VALUE_DISABLE << PORTCON_PORTB_IE_B14_SHIFT) +#define PORTCON_PORTB_IE_B14_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B14_BITS_ENABLE (PORTCON_PORTB_IE_B14_VALUE_ENABLE << PORTCON_PORTB_IE_B14_SHIFT) + +#define PORTCON_PORTB_IE_B15_SHIFT 15 +#define PORTCON_PORTB_IE_B15_WIDTH 1 +#define PORTCON_PORTB_IE_B15_MASK (((1U << PORTCON_PORTB_IE_B15_WIDTH) - 1U) << PORTCON_PORTB_IE_B15_SHIFT) +#define PORTCON_PORTB_IE_B15_VALUE_DISABLE 0U +#define PORTCON_PORTB_IE_B15_BITS_DISABLE (PORTCON_PORTB_IE_B15_VALUE_DISABLE << PORTCON_PORTB_IE_B15_SHIFT) +#define PORTCON_PORTB_IE_B15_VALUE_ENABLE 1U +#define PORTCON_PORTB_IE_B15_BITS_ENABLE (PORTCON_PORTB_IE_B15_VALUE_ENABLE << PORTCON_PORTB_IE_B15_SHIFT) + +#define PORTCON_PORTC_IE_ADDR (PORTCON_BASE_ADDR + 0x0108U) +#define PORTCON_PORTC_IE (*(volatile uint32_t *)PORTCON_PORTC_IE_ADDR) +#define PORTCON_PORTC_IE_C0_SHIFT 0 +#define PORTCON_PORTC_IE_C0_WIDTH 1 +#define PORTCON_PORTC_IE_C0_MASK (((1U << PORTCON_PORTC_IE_C0_WIDTH) - 1U) << PORTCON_PORTC_IE_C0_SHIFT) +#define PORTCON_PORTC_IE_C0_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C0_BITS_DISABLE (PORTCON_PORTC_IE_C0_VALUE_DISABLE << PORTCON_PORTC_IE_C0_SHIFT) +#define PORTCON_PORTC_IE_C0_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C0_BITS_ENABLE (PORTCON_PORTC_IE_C0_VALUE_ENABLE << PORTCON_PORTC_IE_C0_SHIFT) + +#define PORTCON_PORTC_IE_C1_SHIFT 1 +#define PORTCON_PORTC_IE_C1_WIDTH 1 +#define PORTCON_PORTC_IE_C1_MASK (((1U << PORTCON_PORTC_IE_C1_WIDTH) - 1U) << PORTCON_PORTC_IE_C1_SHIFT) +#define PORTCON_PORTC_IE_C1_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C1_BITS_DISABLE (PORTCON_PORTC_IE_C1_VALUE_DISABLE << PORTCON_PORTC_IE_C1_SHIFT) +#define PORTCON_PORTC_IE_C1_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C1_BITS_ENABLE (PORTCON_PORTC_IE_C1_VALUE_ENABLE << PORTCON_PORTC_IE_C1_SHIFT) + +#define PORTCON_PORTC_IE_C2_SHIFT 2 +#define PORTCON_PORTC_IE_C2_WIDTH 1 +#define PORTCON_PORTC_IE_C2_MASK (((1U << PORTCON_PORTC_IE_C2_WIDTH) - 1U) << PORTCON_PORTC_IE_C2_SHIFT) +#define PORTCON_PORTC_IE_C2_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C2_BITS_DISABLE (PORTCON_PORTC_IE_C2_VALUE_DISABLE << PORTCON_PORTC_IE_C2_SHIFT) +#define PORTCON_PORTC_IE_C2_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C2_BITS_ENABLE (PORTCON_PORTC_IE_C2_VALUE_ENABLE << PORTCON_PORTC_IE_C2_SHIFT) + +#define PORTCON_PORTC_IE_C3_SHIFT 3 +#define PORTCON_PORTC_IE_C3_WIDTH 1 +#define PORTCON_PORTC_IE_C3_MASK (((1U << PORTCON_PORTC_IE_C3_WIDTH) - 1U) << PORTCON_PORTC_IE_C3_SHIFT) +#define PORTCON_PORTC_IE_C3_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C3_BITS_DISABLE (PORTCON_PORTC_IE_C3_VALUE_DISABLE << PORTCON_PORTC_IE_C3_SHIFT) +#define PORTCON_PORTC_IE_C3_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C3_BITS_ENABLE (PORTCON_PORTC_IE_C3_VALUE_ENABLE << PORTCON_PORTC_IE_C3_SHIFT) + +#define PORTCON_PORTC_IE_C4_SHIFT 4 +#define PORTCON_PORTC_IE_C4_WIDTH 1 +#define PORTCON_PORTC_IE_C4_MASK (((1U << PORTCON_PORTC_IE_C4_WIDTH) - 1U) << PORTCON_PORTC_IE_C4_SHIFT) +#define PORTCON_PORTC_IE_C4_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C4_BITS_DISABLE (PORTCON_PORTC_IE_C4_VALUE_DISABLE << PORTCON_PORTC_IE_C4_SHIFT) +#define PORTCON_PORTC_IE_C4_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C4_BITS_ENABLE (PORTCON_PORTC_IE_C4_VALUE_ENABLE << PORTCON_PORTC_IE_C4_SHIFT) + +#define PORTCON_PORTC_IE_C5_SHIFT 5 +#define PORTCON_PORTC_IE_C5_WIDTH 1 +#define PORTCON_PORTC_IE_C5_MASK (((1U << PORTCON_PORTC_IE_C5_WIDTH) - 1U) << PORTCON_PORTC_IE_C5_SHIFT) +#define PORTCON_PORTC_IE_C5_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C5_BITS_DISABLE (PORTCON_PORTC_IE_C5_VALUE_DISABLE << PORTCON_PORTC_IE_C5_SHIFT) +#define PORTCON_PORTC_IE_C5_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C5_BITS_ENABLE (PORTCON_PORTC_IE_C5_VALUE_ENABLE << PORTCON_PORTC_IE_C5_SHIFT) + +#define PORTCON_PORTC_IE_C6_SHIFT 6 +#define PORTCON_PORTC_IE_C6_WIDTH 1 +#define PORTCON_PORTC_IE_C6_MASK (((1U << PORTCON_PORTC_IE_C6_WIDTH) - 1U) << PORTCON_PORTC_IE_C6_SHIFT) +#define PORTCON_PORTC_IE_C6_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C6_BITS_DISABLE (PORTCON_PORTC_IE_C6_VALUE_DISABLE << PORTCON_PORTC_IE_C6_SHIFT) +#define PORTCON_PORTC_IE_C6_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C6_BITS_ENABLE (PORTCON_PORTC_IE_C6_VALUE_ENABLE << PORTCON_PORTC_IE_C6_SHIFT) + +#define PORTCON_PORTC_IE_C7_SHIFT 7 +#define PORTCON_PORTC_IE_C7_WIDTH 1 +#define PORTCON_PORTC_IE_C7_MASK (((1U << PORTCON_PORTC_IE_C7_WIDTH) - 1U) << PORTCON_PORTC_IE_C7_SHIFT) +#define PORTCON_PORTC_IE_C7_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C7_BITS_DISABLE (PORTCON_PORTC_IE_C7_VALUE_DISABLE << PORTCON_PORTC_IE_C7_SHIFT) +#define PORTCON_PORTC_IE_C7_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C7_BITS_ENABLE (PORTCON_PORTC_IE_C7_VALUE_ENABLE << PORTCON_PORTC_IE_C7_SHIFT) + +#define PORTCON_PORTC_IE_C8_SHIFT 8 +#define PORTCON_PORTC_IE_C8_WIDTH 1 +#define PORTCON_PORTC_IE_C8_MASK (((1U << PORTCON_PORTC_IE_C8_WIDTH) - 1U) << PORTCON_PORTC_IE_C8_SHIFT) +#define PORTCON_PORTC_IE_C8_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C8_BITS_DISABLE (PORTCON_PORTC_IE_C8_VALUE_DISABLE << PORTCON_PORTC_IE_C8_SHIFT) +#define PORTCON_PORTC_IE_C8_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C8_BITS_ENABLE (PORTCON_PORTC_IE_C8_VALUE_ENABLE << PORTCON_PORTC_IE_C8_SHIFT) + +#define PORTCON_PORTC_IE_C9_SHIFT 9 +#define PORTCON_PORTC_IE_C9_WIDTH 1 +#define PORTCON_PORTC_IE_C9_MASK (((1U << PORTCON_PORTC_IE_C9_WIDTH) - 1U) << PORTCON_PORTC_IE_C9_SHIFT) +#define PORTCON_PORTC_IE_C9_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C9_BITS_DISABLE (PORTCON_PORTC_IE_C9_VALUE_DISABLE << PORTCON_PORTC_IE_C9_SHIFT) +#define PORTCON_PORTC_IE_C9_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C9_BITS_ENABLE (PORTCON_PORTC_IE_C9_VALUE_ENABLE << PORTCON_PORTC_IE_C9_SHIFT) + +#define PORTCON_PORTC_IE_C10_SHIFT 10 +#define PORTCON_PORTC_IE_C10_WIDTH 1 +#define PORTCON_PORTC_IE_C10_MASK (((1U << PORTCON_PORTC_IE_C10_WIDTH) - 1U) << PORTCON_PORTC_IE_C10_SHIFT) +#define PORTCON_PORTC_IE_C10_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C10_BITS_DISABLE (PORTCON_PORTC_IE_C10_VALUE_DISABLE << PORTCON_PORTC_IE_C10_SHIFT) +#define PORTCON_PORTC_IE_C10_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C10_BITS_ENABLE (PORTCON_PORTC_IE_C10_VALUE_ENABLE << PORTCON_PORTC_IE_C10_SHIFT) + +#define PORTCON_PORTC_IE_C11_SHIFT 11 +#define PORTCON_PORTC_IE_C11_WIDTH 1 +#define PORTCON_PORTC_IE_C11_MASK (((1U << PORTCON_PORTC_IE_C11_WIDTH) - 1U) << PORTCON_PORTC_IE_C11_SHIFT) +#define PORTCON_PORTC_IE_C11_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C11_BITS_DISABLE (PORTCON_PORTC_IE_C11_VALUE_DISABLE << PORTCON_PORTC_IE_C11_SHIFT) +#define PORTCON_PORTC_IE_C11_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C11_BITS_ENABLE (PORTCON_PORTC_IE_C11_VALUE_ENABLE << PORTCON_PORTC_IE_C11_SHIFT) + +#define PORTCON_PORTC_IE_C12_SHIFT 12 +#define PORTCON_PORTC_IE_C12_WIDTH 1 +#define PORTCON_PORTC_IE_C12_MASK (((1U << PORTCON_PORTC_IE_C12_WIDTH) - 1U) << PORTCON_PORTC_IE_C12_SHIFT) +#define PORTCON_PORTC_IE_C12_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C12_BITS_DISABLE (PORTCON_PORTC_IE_C12_VALUE_DISABLE << PORTCON_PORTC_IE_C12_SHIFT) +#define PORTCON_PORTC_IE_C12_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C12_BITS_ENABLE (PORTCON_PORTC_IE_C12_VALUE_ENABLE << PORTCON_PORTC_IE_C12_SHIFT) + +#define PORTCON_PORTC_IE_C13_SHIFT 13 +#define PORTCON_PORTC_IE_C13_WIDTH 1 +#define PORTCON_PORTC_IE_C13_MASK (((1U << PORTCON_PORTC_IE_C13_WIDTH) - 1U) << PORTCON_PORTC_IE_C13_SHIFT) +#define PORTCON_PORTC_IE_C13_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C13_BITS_DISABLE (PORTCON_PORTC_IE_C13_VALUE_DISABLE << PORTCON_PORTC_IE_C13_SHIFT) +#define PORTCON_PORTC_IE_C13_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C13_BITS_ENABLE (PORTCON_PORTC_IE_C13_VALUE_ENABLE << PORTCON_PORTC_IE_C13_SHIFT) + +#define PORTCON_PORTC_IE_C14_SHIFT 14 +#define PORTCON_PORTC_IE_C14_WIDTH 1 +#define PORTCON_PORTC_IE_C14_MASK (((1U << PORTCON_PORTC_IE_C14_WIDTH) - 1U) << PORTCON_PORTC_IE_C14_SHIFT) +#define PORTCON_PORTC_IE_C14_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C14_BITS_DISABLE (PORTCON_PORTC_IE_C14_VALUE_DISABLE << PORTCON_PORTC_IE_C14_SHIFT) +#define PORTCON_PORTC_IE_C14_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C14_BITS_ENABLE (PORTCON_PORTC_IE_C14_VALUE_ENABLE << PORTCON_PORTC_IE_C14_SHIFT) + +#define PORTCON_PORTC_IE_C15_SHIFT 15 +#define PORTCON_PORTC_IE_C15_WIDTH 1 +#define PORTCON_PORTC_IE_C15_MASK (((1U << PORTCON_PORTC_IE_C15_WIDTH) - 1U) << PORTCON_PORTC_IE_C15_SHIFT) +#define PORTCON_PORTC_IE_C15_VALUE_DISABLE 0U +#define PORTCON_PORTC_IE_C15_BITS_DISABLE (PORTCON_PORTC_IE_C15_VALUE_DISABLE << PORTCON_PORTC_IE_C15_SHIFT) +#define PORTCON_PORTC_IE_C15_VALUE_ENABLE 1U +#define PORTCON_PORTC_IE_C15_BITS_ENABLE (PORTCON_PORTC_IE_C15_VALUE_ENABLE << PORTCON_PORTC_IE_C15_SHIFT) + +#define PORTCON_PORTA_PU_ADDR (PORTCON_BASE_ADDR + 0x0200U) +#define PORTCON_PORTA_PU (*(volatile uint32_t *)PORTCON_PORTA_PU_ADDR) +#define PORTCON_PORTA_PU_A0_SHIFT 0 +#define PORTCON_PORTA_PU_A0_WIDTH 1 +#define PORTCON_PORTA_PU_A0_MASK (((1U << PORTCON_PORTA_PU_A0_WIDTH) - 1U) << PORTCON_PORTA_PU_A0_SHIFT) +#define PORTCON_PORTA_PU_A0_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A0_BITS_DISABLE (PORTCON_PORTA_PU_A0_VALUE_DISABLE << PORTCON_PORTA_PU_A0_SHIFT) +#define PORTCON_PORTA_PU_A0_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A0_BITS_ENABLE (PORTCON_PORTA_PU_A0_VALUE_ENABLE << PORTCON_PORTA_PU_A0_SHIFT) + +#define PORTCON_PORTA_PU_A1_SHIFT 1 +#define PORTCON_PORTA_PU_A1_WIDTH 1 +#define PORTCON_PORTA_PU_A1_MASK (((1U << PORTCON_PORTA_PU_A1_WIDTH) - 1U) << PORTCON_PORTA_PU_A1_SHIFT) +#define PORTCON_PORTA_PU_A1_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A1_BITS_DISABLE (PORTCON_PORTA_PU_A1_VALUE_DISABLE << PORTCON_PORTA_PU_A1_SHIFT) +#define PORTCON_PORTA_PU_A1_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A1_BITS_ENABLE (PORTCON_PORTA_PU_A1_VALUE_ENABLE << PORTCON_PORTA_PU_A1_SHIFT) + +#define PORTCON_PORTA_PU_A2_SHIFT 2 +#define PORTCON_PORTA_PU_A2_WIDTH 1 +#define PORTCON_PORTA_PU_A2_MASK (((1U << PORTCON_PORTA_PU_A2_WIDTH) - 1U) << PORTCON_PORTA_PU_A2_SHIFT) +#define PORTCON_PORTA_PU_A2_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A2_BITS_DISABLE (PORTCON_PORTA_PU_A2_VALUE_DISABLE << PORTCON_PORTA_PU_A2_SHIFT) +#define PORTCON_PORTA_PU_A2_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A2_BITS_ENABLE (PORTCON_PORTA_PU_A2_VALUE_ENABLE << PORTCON_PORTA_PU_A2_SHIFT) + +#define PORTCON_PORTA_PU_A3_SHIFT 3 +#define PORTCON_PORTA_PU_A3_WIDTH 1 +#define PORTCON_PORTA_PU_A3_MASK (((1U << PORTCON_PORTA_PU_A3_WIDTH) - 1U) << PORTCON_PORTA_PU_A3_SHIFT) +#define PORTCON_PORTA_PU_A3_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A3_BITS_DISABLE (PORTCON_PORTA_PU_A3_VALUE_DISABLE << PORTCON_PORTA_PU_A3_SHIFT) +#define PORTCON_PORTA_PU_A3_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A3_BITS_ENABLE (PORTCON_PORTA_PU_A3_VALUE_ENABLE << PORTCON_PORTA_PU_A3_SHIFT) + +#define PORTCON_PORTA_PU_A4_SHIFT 4 +#define PORTCON_PORTA_PU_A4_WIDTH 1 +#define PORTCON_PORTA_PU_A4_MASK (((1U << PORTCON_PORTA_PU_A4_WIDTH) - 1U) << PORTCON_PORTA_PU_A4_SHIFT) +#define PORTCON_PORTA_PU_A4_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A4_BITS_DISABLE (PORTCON_PORTA_PU_A4_VALUE_DISABLE << PORTCON_PORTA_PU_A4_SHIFT) +#define PORTCON_PORTA_PU_A4_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A4_BITS_ENABLE (PORTCON_PORTA_PU_A4_VALUE_ENABLE << PORTCON_PORTA_PU_A4_SHIFT) + +#define PORTCON_PORTA_PU_A5_SHIFT 5 +#define PORTCON_PORTA_PU_A5_WIDTH 1 +#define PORTCON_PORTA_PU_A5_MASK (((1U << PORTCON_PORTA_PU_A5_WIDTH) - 1U) << PORTCON_PORTA_PU_A5_SHIFT) +#define PORTCON_PORTA_PU_A5_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A5_BITS_DISABLE (PORTCON_PORTA_PU_A5_VALUE_DISABLE << PORTCON_PORTA_PU_A5_SHIFT) +#define PORTCON_PORTA_PU_A5_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A5_BITS_ENABLE (PORTCON_PORTA_PU_A5_VALUE_ENABLE << PORTCON_PORTA_PU_A5_SHIFT) + +#define PORTCON_PORTA_PU_A6_SHIFT 6 +#define PORTCON_PORTA_PU_A6_WIDTH 1 +#define PORTCON_PORTA_PU_A6_MASK (((1U << PORTCON_PORTA_PU_A6_WIDTH) - 1U) << PORTCON_PORTA_PU_A6_SHIFT) +#define PORTCON_PORTA_PU_A6_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A6_BITS_DISABLE (PORTCON_PORTA_PU_A6_VALUE_DISABLE << PORTCON_PORTA_PU_A6_SHIFT) +#define PORTCON_PORTA_PU_A6_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A6_BITS_ENABLE (PORTCON_PORTA_PU_A6_VALUE_ENABLE << PORTCON_PORTA_PU_A6_SHIFT) + +#define PORTCON_PORTA_PU_A7_SHIFT 7 +#define PORTCON_PORTA_PU_A7_WIDTH 1 +#define PORTCON_PORTA_PU_A7_MASK (((1U << PORTCON_PORTA_PU_A7_WIDTH) - 1U) << PORTCON_PORTA_PU_A7_SHIFT) +#define PORTCON_PORTA_PU_A7_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A7_BITS_DISABLE (PORTCON_PORTA_PU_A7_VALUE_DISABLE << PORTCON_PORTA_PU_A7_SHIFT) +#define PORTCON_PORTA_PU_A7_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A7_BITS_ENABLE (PORTCON_PORTA_PU_A7_VALUE_ENABLE << PORTCON_PORTA_PU_A7_SHIFT) + +#define PORTCON_PORTA_PU_A8_SHIFT 8 +#define PORTCON_PORTA_PU_A8_WIDTH 1 +#define PORTCON_PORTA_PU_A8_MASK (((1U << PORTCON_PORTA_PU_A8_WIDTH) - 1U) << PORTCON_PORTA_PU_A8_SHIFT) +#define PORTCON_PORTA_PU_A8_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A8_BITS_DISABLE (PORTCON_PORTA_PU_A8_VALUE_DISABLE << PORTCON_PORTA_PU_A8_SHIFT) +#define PORTCON_PORTA_PU_A8_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A8_BITS_ENABLE (PORTCON_PORTA_PU_A8_VALUE_ENABLE << PORTCON_PORTA_PU_A8_SHIFT) + +#define PORTCON_PORTA_PU_A9_SHIFT 9 +#define PORTCON_PORTA_PU_A9_WIDTH 1 +#define PORTCON_PORTA_PU_A9_MASK (((1U << PORTCON_PORTA_PU_A9_WIDTH) - 1U) << PORTCON_PORTA_PU_A9_SHIFT) +#define PORTCON_PORTA_PU_A9_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A9_BITS_DISABLE (PORTCON_PORTA_PU_A9_VALUE_DISABLE << PORTCON_PORTA_PU_A9_SHIFT) +#define PORTCON_PORTA_PU_A9_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A9_BITS_ENABLE (PORTCON_PORTA_PU_A9_VALUE_ENABLE << PORTCON_PORTA_PU_A9_SHIFT) + +#define PORTCON_PORTA_PU_A10_SHIFT 10 +#define PORTCON_PORTA_PU_A10_WIDTH 1 +#define PORTCON_PORTA_PU_A10_MASK (((1U << PORTCON_PORTA_PU_A10_WIDTH) - 1U) << PORTCON_PORTA_PU_A10_SHIFT) +#define PORTCON_PORTA_PU_A10_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A10_BITS_DISABLE (PORTCON_PORTA_PU_A10_VALUE_DISABLE << PORTCON_PORTA_PU_A10_SHIFT) +#define PORTCON_PORTA_PU_A10_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A10_BITS_ENABLE (PORTCON_PORTA_PU_A10_VALUE_ENABLE << PORTCON_PORTA_PU_A10_SHIFT) + +#define PORTCON_PORTA_PU_A11_SHIFT 11 +#define PORTCON_PORTA_PU_A11_WIDTH 1 +#define PORTCON_PORTA_PU_A11_MASK (((1U << PORTCON_PORTA_PU_A11_WIDTH) - 1U) << PORTCON_PORTA_PU_A11_SHIFT) +#define PORTCON_PORTA_PU_A11_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A11_BITS_DISABLE (PORTCON_PORTA_PU_A11_VALUE_DISABLE << PORTCON_PORTA_PU_A11_SHIFT) +#define PORTCON_PORTA_PU_A11_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A11_BITS_ENABLE (PORTCON_PORTA_PU_A11_VALUE_ENABLE << PORTCON_PORTA_PU_A11_SHIFT) + +#define PORTCON_PORTA_PU_A12_SHIFT 12 +#define PORTCON_PORTA_PU_A12_WIDTH 1 +#define PORTCON_PORTA_PU_A12_MASK (((1U << PORTCON_PORTA_PU_A12_WIDTH) - 1U) << PORTCON_PORTA_PU_A12_SHIFT) +#define PORTCON_PORTA_PU_A12_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A12_BITS_DISABLE (PORTCON_PORTA_PU_A12_VALUE_DISABLE << PORTCON_PORTA_PU_A12_SHIFT) +#define PORTCON_PORTA_PU_A12_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A12_BITS_ENABLE (PORTCON_PORTA_PU_A12_VALUE_ENABLE << PORTCON_PORTA_PU_A12_SHIFT) + +#define PORTCON_PORTA_PU_A13_SHIFT 13 +#define PORTCON_PORTA_PU_A13_WIDTH 1 +#define PORTCON_PORTA_PU_A13_MASK (((1U << PORTCON_PORTA_PU_A13_WIDTH) - 1U) << PORTCON_PORTA_PU_A13_SHIFT) +#define PORTCON_PORTA_PU_A13_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A13_BITS_DISABLE (PORTCON_PORTA_PU_A13_VALUE_DISABLE << PORTCON_PORTA_PU_A13_SHIFT) +#define PORTCON_PORTA_PU_A13_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A13_BITS_ENABLE (PORTCON_PORTA_PU_A13_VALUE_ENABLE << PORTCON_PORTA_PU_A13_SHIFT) + +#define PORTCON_PORTA_PU_A14_SHIFT 14 +#define PORTCON_PORTA_PU_A14_WIDTH 1 +#define PORTCON_PORTA_PU_A14_MASK (((1U << PORTCON_PORTA_PU_A14_WIDTH) - 1U) << PORTCON_PORTA_PU_A14_SHIFT) +#define PORTCON_PORTA_PU_A14_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A14_BITS_DISABLE (PORTCON_PORTA_PU_A14_VALUE_DISABLE << PORTCON_PORTA_PU_A14_SHIFT) +#define PORTCON_PORTA_PU_A14_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A14_BITS_ENABLE (PORTCON_PORTA_PU_A14_VALUE_ENABLE << PORTCON_PORTA_PU_A14_SHIFT) + +#define PORTCON_PORTA_PU_A15_SHIFT 15 +#define PORTCON_PORTA_PU_A15_WIDTH 1 +#define PORTCON_PORTA_PU_A15_MASK (((1U << PORTCON_PORTA_PU_A15_WIDTH) - 1U) << PORTCON_PORTA_PU_A15_SHIFT) +#define PORTCON_PORTA_PU_A15_VALUE_DISABLE 0U +#define PORTCON_PORTA_PU_A15_BITS_DISABLE (PORTCON_PORTA_PU_A15_VALUE_DISABLE << PORTCON_PORTA_PU_A15_SHIFT) +#define PORTCON_PORTA_PU_A15_VALUE_ENABLE 1U +#define PORTCON_PORTA_PU_A15_BITS_ENABLE (PORTCON_PORTA_PU_A15_VALUE_ENABLE << PORTCON_PORTA_PU_A15_SHIFT) + +#define PORTCON_PORTB_PU_ADDR (PORTCON_BASE_ADDR + 0x0204U) +#define PORTCON_PORTB_PU (*(volatile uint32_t *)PORTCON_PORTB_PU_ADDR) +#define PORTCON_PORTB_PU_B0_SHIFT 0 +#define PORTCON_PORTB_PU_B0_WIDTH 1 +#define PORTCON_PORTB_PU_B0_MASK (((1U << PORTCON_PORTB_PU_B0_WIDTH) - 1U) << PORTCON_PORTB_PU_B0_SHIFT) +#define PORTCON_PORTB_PU_B0_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B0_BITS_DISABLE (PORTCON_PORTB_PU_B0_VALUE_DISABLE << PORTCON_PORTB_PU_B0_SHIFT) +#define PORTCON_PORTB_PU_B0_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B0_BITS_ENABLE (PORTCON_PORTB_PU_B0_VALUE_ENABLE << PORTCON_PORTB_PU_B0_SHIFT) + +#define PORTCON_PORTB_PU_B1_SHIFT 1 +#define PORTCON_PORTB_PU_B1_WIDTH 1 +#define PORTCON_PORTB_PU_B1_MASK (((1U << PORTCON_PORTB_PU_B1_WIDTH) - 1U) << PORTCON_PORTB_PU_B1_SHIFT) +#define PORTCON_PORTB_PU_B1_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B1_BITS_DISABLE (PORTCON_PORTB_PU_B1_VALUE_DISABLE << PORTCON_PORTB_PU_B1_SHIFT) +#define PORTCON_PORTB_PU_B1_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B1_BITS_ENABLE (PORTCON_PORTB_PU_B1_VALUE_ENABLE << PORTCON_PORTB_PU_B1_SHIFT) + +#define PORTCON_PORTB_PU_B2_SHIFT 2 +#define PORTCON_PORTB_PU_B2_WIDTH 1 +#define PORTCON_PORTB_PU_B2_MASK (((1U << PORTCON_PORTB_PU_B2_WIDTH) - 1U) << PORTCON_PORTB_PU_B2_SHIFT) +#define PORTCON_PORTB_PU_B2_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B2_BITS_DISABLE (PORTCON_PORTB_PU_B2_VALUE_DISABLE << PORTCON_PORTB_PU_B2_SHIFT) +#define PORTCON_PORTB_PU_B2_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B2_BITS_ENABLE (PORTCON_PORTB_PU_B2_VALUE_ENABLE << PORTCON_PORTB_PU_B2_SHIFT) + +#define PORTCON_PORTB_PU_B3_SHIFT 3 +#define PORTCON_PORTB_PU_B3_WIDTH 1 +#define PORTCON_PORTB_PU_B3_MASK (((1U << PORTCON_PORTB_PU_B3_WIDTH) - 1U) << PORTCON_PORTB_PU_B3_SHIFT) +#define PORTCON_PORTB_PU_B3_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B3_BITS_DISABLE (PORTCON_PORTB_PU_B3_VALUE_DISABLE << PORTCON_PORTB_PU_B3_SHIFT) +#define PORTCON_PORTB_PU_B3_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B3_BITS_ENABLE (PORTCON_PORTB_PU_B3_VALUE_ENABLE << PORTCON_PORTB_PU_B3_SHIFT) + +#define PORTCON_PORTB_PU_B4_SHIFT 4 +#define PORTCON_PORTB_PU_B4_WIDTH 1 +#define PORTCON_PORTB_PU_B4_MASK (((1U << PORTCON_PORTB_PU_B4_WIDTH) - 1U) << PORTCON_PORTB_PU_B4_SHIFT) +#define PORTCON_PORTB_PU_B4_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B4_BITS_DISABLE (PORTCON_PORTB_PU_B4_VALUE_DISABLE << PORTCON_PORTB_PU_B4_SHIFT) +#define PORTCON_PORTB_PU_B4_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B4_BITS_ENABLE (PORTCON_PORTB_PU_B4_VALUE_ENABLE << PORTCON_PORTB_PU_B4_SHIFT) + +#define PORTCON_PORTB_PU_B5_SHIFT 5 +#define PORTCON_PORTB_PU_B5_WIDTH 1 +#define PORTCON_PORTB_PU_B5_MASK (((1U << PORTCON_PORTB_PU_B5_WIDTH) - 1U) << PORTCON_PORTB_PU_B5_SHIFT) +#define PORTCON_PORTB_PU_B5_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B5_BITS_DISABLE (PORTCON_PORTB_PU_B5_VALUE_DISABLE << PORTCON_PORTB_PU_B5_SHIFT) +#define PORTCON_PORTB_PU_B5_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B5_BITS_ENABLE (PORTCON_PORTB_PU_B5_VALUE_ENABLE << PORTCON_PORTB_PU_B5_SHIFT) + +#define PORTCON_PORTB_PU_B6_SHIFT 6 +#define PORTCON_PORTB_PU_B6_WIDTH 1 +#define PORTCON_PORTB_PU_B6_MASK (((1U << PORTCON_PORTB_PU_B6_WIDTH) - 1U) << PORTCON_PORTB_PU_B6_SHIFT) +#define PORTCON_PORTB_PU_B6_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B6_BITS_DISABLE (PORTCON_PORTB_PU_B6_VALUE_DISABLE << PORTCON_PORTB_PU_B6_SHIFT) +#define PORTCON_PORTB_PU_B6_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B6_BITS_ENABLE (PORTCON_PORTB_PU_B6_VALUE_ENABLE << PORTCON_PORTB_PU_B6_SHIFT) + +#define PORTCON_PORTB_PU_B7_SHIFT 7 +#define PORTCON_PORTB_PU_B7_WIDTH 1 +#define PORTCON_PORTB_PU_B7_MASK (((1U << PORTCON_PORTB_PU_B7_WIDTH) - 1U) << PORTCON_PORTB_PU_B7_SHIFT) +#define PORTCON_PORTB_PU_B7_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B7_BITS_DISABLE (PORTCON_PORTB_PU_B7_VALUE_DISABLE << PORTCON_PORTB_PU_B7_SHIFT) +#define PORTCON_PORTB_PU_B7_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B7_BITS_ENABLE (PORTCON_PORTB_PU_B7_VALUE_ENABLE << PORTCON_PORTB_PU_B7_SHIFT) + +#define PORTCON_PORTB_PU_B8_SHIFT 8 +#define PORTCON_PORTB_PU_B8_WIDTH 1 +#define PORTCON_PORTB_PU_B8_MASK (((1U << PORTCON_PORTB_PU_B8_WIDTH) - 1U) << PORTCON_PORTB_PU_B8_SHIFT) +#define PORTCON_PORTB_PU_B8_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B8_BITS_DISABLE (PORTCON_PORTB_PU_B8_VALUE_DISABLE << PORTCON_PORTB_PU_B8_SHIFT) +#define PORTCON_PORTB_PU_B8_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B8_BITS_ENABLE (PORTCON_PORTB_PU_B8_VALUE_ENABLE << PORTCON_PORTB_PU_B8_SHIFT) + +#define PORTCON_PORTB_PU_B9_SHIFT 9 +#define PORTCON_PORTB_PU_B9_WIDTH 1 +#define PORTCON_PORTB_PU_B9_MASK (((1U << PORTCON_PORTB_PU_B9_WIDTH) - 1U) << PORTCON_PORTB_PU_B9_SHIFT) +#define PORTCON_PORTB_PU_B9_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B9_BITS_DISABLE (PORTCON_PORTB_PU_B9_VALUE_DISABLE << PORTCON_PORTB_PU_B9_SHIFT) +#define PORTCON_PORTB_PU_B9_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B9_BITS_ENABLE (PORTCON_PORTB_PU_B9_VALUE_ENABLE << PORTCON_PORTB_PU_B9_SHIFT) + +#define PORTCON_PORTB_PU_B10_SHIFT 10 +#define PORTCON_PORTB_PU_B10_WIDTH 1 +#define PORTCON_PORTB_PU_B10_MASK (((1U << PORTCON_PORTB_PU_B10_WIDTH) - 1U) << PORTCON_PORTB_PU_B10_SHIFT) +#define PORTCON_PORTB_PU_B10_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B10_BITS_DISABLE (PORTCON_PORTB_PU_B10_VALUE_DISABLE << PORTCON_PORTB_PU_B10_SHIFT) +#define PORTCON_PORTB_PU_B10_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B10_BITS_ENABLE (PORTCON_PORTB_PU_B10_VALUE_ENABLE << PORTCON_PORTB_PU_B10_SHIFT) + +#define PORTCON_PORTB_PU_B11_SHIFT 11 +#define PORTCON_PORTB_PU_B11_WIDTH 1 +#define PORTCON_PORTB_PU_B11_MASK (((1U << PORTCON_PORTB_PU_B11_WIDTH) - 1U) << PORTCON_PORTB_PU_B11_SHIFT) +#define PORTCON_PORTB_PU_B11_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B11_BITS_DISABLE (PORTCON_PORTB_PU_B11_VALUE_DISABLE << PORTCON_PORTB_PU_B11_SHIFT) +#define PORTCON_PORTB_PU_B11_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B11_BITS_ENABLE (PORTCON_PORTB_PU_B11_VALUE_ENABLE << PORTCON_PORTB_PU_B11_SHIFT) + +#define PORTCON_PORTB_PU_B12_SHIFT 12 +#define PORTCON_PORTB_PU_B12_WIDTH 1 +#define PORTCON_PORTB_PU_B12_MASK (((1U << PORTCON_PORTB_PU_B12_WIDTH) - 1U) << PORTCON_PORTB_PU_B12_SHIFT) +#define PORTCON_PORTB_PU_B12_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B12_BITS_DISABLE (PORTCON_PORTB_PU_B12_VALUE_DISABLE << PORTCON_PORTB_PU_B12_SHIFT) +#define PORTCON_PORTB_PU_B12_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B12_BITS_ENABLE (PORTCON_PORTB_PU_B12_VALUE_ENABLE << PORTCON_PORTB_PU_B12_SHIFT) + +#define PORTCON_PORTB_PU_B13_SHIFT 13 +#define PORTCON_PORTB_PU_B13_WIDTH 1 +#define PORTCON_PORTB_PU_B13_MASK (((1U << PORTCON_PORTB_PU_B13_WIDTH) - 1U) << PORTCON_PORTB_PU_B13_SHIFT) +#define PORTCON_PORTB_PU_B13_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B13_BITS_DISABLE (PORTCON_PORTB_PU_B13_VALUE_DISABLE << PORTCON_PORTB_PU_B13_SHIFT) +#define PORTCON_PORTB_PU_B13_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B13_BITS_ENABLE (PORTCON_PORTB_PU_B13_VALUE_ENABLE << PORTCON_PORTB_PU_B13_SHIFT) + +#define PORTCON_PORTB_PU_B14_SHIFT 14 +#define PORTCON_PORTB_PU_B14_WIDTH 1 +#define PORTCON_PORTB_PU_B14_MASK (((1U << PORTCON_PORTB_PU_B14_WIDTH) - 1U) << PORTCON_PORTB_PU_B14_SHIFT) +#define PORTCON_PORTB_PU_B14_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B14_BITS_DISABLE (PORTCON_PORTB_PU_B14_VALUE_DISABLE << PORTCON_PORTB_PU_B14_SHIFT) +#define PORTCON_PORTB_PU_B14_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B14_BITS_ENABLE (PORTCON_PORTB_PU_B14_VALUE_ENABLE << PORTCON_PORTB_PU_B14_SHIFT) + +#define PORTCON_PORTB_PU_B15_SHIFT 15 +#define PORTCON_PORTB_PU_B15_WIDTH 1 +#define PORTCON_PORTB_PU_B15_MASK (((1U << PORTCON_PORTB_PU_B15_WIDTH) - 1U) << PORTCON_PORTB_PU_B15_SHIFT) +#define PORTCON_PORTB_PU_B15_VALUE_DISABLE 0U +#define PORTCON_PORTB_PU_B15_BITS_DISABLE (PORTCON_PORTB_PU_B15_VALUE_DISABLE << PORTCON_PORTB_PU_B15_SHIFT) +#define PORTCON_PORTB_PU_B15_VALUE_ENABLE 1U +#define PORTCON_PORTB_PU_B15_BITS_ENABLE (PORTCON_PORTB_PU_B15_VALUE_ENABLE << PORTCON_PORTB_PU_B15_SHIFT) + +#define PORTCON_PORTC_PU_ADDR (PORTCON_BASE_ADDR + 0x0208U) +#define PORTCON_PORTC_PU (*(volatile uint32_t *)PORTCON_PORTC_PU_ADDR) +#define PORTCON_PORTC_PU_C0_SHIFT 0 +#define PORTCON_PORTC_PU_C0_WIDTH 1 +#define PORTCON_PORTC_PU_C0_MASK (((1U << PORTCON_PORTC_PU_C0_WIDTH) - 1U) << PORTCON_PORTC_PU_C0_SHIFT) +#define PORTCON_PORTC_PU_C0_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C0_BITS_DISABLE (PORTCON_PORTC_PU_C0_VALUE_DISABLE << PORTCON_PORTC_PU_C0_SHIFT) +#define PORTCON_PORTC_PU_C0_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C0_BITS_ENABLE (PORTCON_PORTC_PU_C0_VALUE_ENABLE << PORTCON_PORTC_PU_C0_SHIFT) + +#define PORTCON_PORTC_PU_C1_SHIFT 1 +#define PORTCON_PORTC_PU_C1_WIDTH 1 +#define PORTCON_PORTC_PU_C1_MASK (((1U << PORTCON_PORTC_PU_C1_WIDTH) - 1U) << PORTCON_PORTC_PU_C1_SHIFT) +#define PORTCON_PORTC_PU_C1_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C1_BITS_DISABLE (PORTCON_PORTC_PU_C1_VALUE_DISABLE << PORTCON_PORTC_PU_C1_SHIFT) +#define PORTCON_PORTC_PU_C1_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C1_BITS_ENABLE (PORTCON_PORTC_PU_C1_VALUE_ENABLE << PORTCON_PORTC_PU_C1_SHIFT) + +#define PORTCON_PORTC_PU_C2_SHIFT 2 +#define PORTCON_PORTC_PU_C2_WIDTH 1 +#define PORTCON_PORTC_PU_C2_MASK (((1U << PORTCON_PORTC_PU_C2_WIDTH) - 1U) << PORTCON_PORTC_PU_C2_SHIFT) +#define PORTCON_PORTC_PU_C2_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C2_BITS_DISABLE (PORTCON_PORTC_PU_C2_VALUE_DISABLE << PORTCON_PORTC_PU_C2_SHIFT) +#define PORTCON_PORTC_PU_C2_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C2_BITS_ENABLE (PORTCON_PORTC_PU_C2_VALUE_ENABLE << PORTCON_PORTC_PU_C2_SHIFT) + +#define PORTCON_PORTC_PU_C3_SHIFT 3 +#define PORTCON_PORTC_PU_C3_WIDTH 1 +#define PORTCON_PORTC_PU_C3_MASK (((1U << PORTCON_PORTC_PU_C3_WIDTH) - 1U) << PORTCON_PORTC_PU_C3_SHIFT) +#define PORTCON_PORTC_PU_C3_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C3_BITS_DISABLE (PORTCON_PORTC_PU_C3_VALUE_DISABLE << PORTCON_PORTC_PU_C3_SHIFT) +#define PORTCON_PORTC_PU_C3_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C3_BITS_ENABLE (PORTCON_PORTC_PU_C3_VALUE_ENABLE << PORTCON_PORTC_PU_C3_SHIFT) + +#define PORTCON_PORTC_PU_C4_SHIFT 4 +#define PORTCON_PORTC_PU_C4_WIDTH 1 +#define PORTCON_PORTC_PU_C4_MASK (((1U << PORTCON_PORTC_PU_C4_WIDTH) - 1U) << PORTCON_PORTC_PU_C4_SHIFT) +#define PORTCON_PORTC_PU_C4_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C4_BITS_DISABLE (PORTCON_PORTC_PU_C4_VALUE_DISABLE << PORTCON_PORTC_PU_C4_SHIFT) +#define PORTCON_PORTC_PU_C4_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C4_BITS_ENABLE (PORTCON_PORTC_PU_C4_VALUE_ENABLE << PORTCON_PORTC_PU_C4_SHIFT) + +#define PORTCON_PORTC_PU_C5_SHIFT 5 +#define PORTCON_PORTC_PU_C5_WIDTH 1 +#define PORTCON_PORTC_PU_C5_MASK (((1U << PORTCON_PORTC_PU_C5_WIDTH) - 1U) << PORTCON_PORTC_PU_C5_SHIFT) +#define PORTCON_PORTC_PU_C5_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C5_BITS_DISABLE (PORTCON_PORTC_PU_C5_VALUE_DISABLE << PORTCON_PORTC_PU_C5_SHIFT) +#define PORTCON_PORTC_PU_C5_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C5_BITS_ENABLE (PORTCON_PORTC_PU_C5_VALUE_ENABLE << PORTCON_PORTC_PU_C5_SHIFT) + +#define PORTCON_PORTC_PU_C6_SHIFT 6 +#define PORTCON_PORTC_PU_C6_WIDTH 1 +#define PORTCON_PORTC_PU_C6_MASK (((1U << PORTCON_PORTC_PU_C6_WIDTH) - 1U) << PORTCON_PORTC_PU_C6_SHIFT) +#define PORTCON_PORTC_PU_C6_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C6_BITS_DISABLE (PORTCON_PORTC_PU_C6_VALUE_DISABLE << PORTCON_PORTC_PU_C6_SHIFT) +#define PORTCON_PORTC_PU_C6_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C6_BITS_ENABLE (PORTCON_PORTC_PU_C6_VALUE_ENABLE << PORTCON_PORTC_PU_C6_SHIFT) + +#define PORTCON_PORTC_PU_C7_SHIFT 7 +#define PORTCON_PORTC_PU_C7_WIDTH 1 +#define PORTCON_PORTC_PU_C7_MASK (((1U << PORTCON_PORTC_PU_C7_WIDTH) - 1U) << PORTCON_PORTC_PU_C7_SHIFT) +#define PORTCON_PORTC_PU_C7_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C7_BITS_DISABLE (PORTCON_PORTC_PU_C7_VALUE_DISABLE << PORTCON_PORTC_PU_C7_SHIFT) +#define PORTCON_PORTC_PU_C7_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C7_BITS_ENABLE (PORTCON_PORTC_PU_C7_VALUE_ENABLE << PORTCON_PORTC_PU_C7_SHIFT) + +#define PORTCON_PORTC_PU_C8_SHIFT 8 +#define PORTCON_PORTC_PU_C8_WIDTH 1 +#define PORTCON_PORTC_PU_C8_MASK (((1U << PORTCON_PORTC_PU_C8_WIDTH) - 1U) << PORTCON_PORTC_PU_C8_SHIFT) +#define PORTCON_PORTC_PU_C8_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C8_BITS_DISABLE (PORTCON_PORTC_PU_C8_VALUE_DISABLE << PORTCON_PORTC_PU_C8_SHIFT) +#define PORTCON_PORTC_PU_C8_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C8_BITS_ENABLE (PORTCON_PORTC_PU_C8_VALUE_ENABLE << PORTCON_PORTC_PU_C8_SHIFT) + +#define PORTCON_PORTC_PU_C9_SHIFT 9 +#define PORTCON_PORTC_PU_C9_WIDTH 1 +#define PORTCON_PORTC_PU_C9_MASK (((1U << PORTCON_PORTC_PU_C9_WIDTH) - 1U) << PORTCON_PORTC_PU_C9_SHIFT) +#define PORTCON_PORTC_PU_C9_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C9_BITS_DISABLE (PORTCON_PORTC_PU_C9_VALUE_DISABLE << PORTCON_PORTC_PU_C9_SHIFT) +#define PORTCON_PORTC_PU_C9_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C9_BITS_ENABLE (PORTCON_PORTC_PU_C9_VALUE_ENABLE << PORTCON_PORTC_PU_C9_SHIFT) + +#define PORTCON_PORTC_PU_C10_SHIFT 10 +#define PORTCON_PORTC_PU_C10_WIDTH 1 +#define PORTCON_PORTC_PU_C10_MASK (((1U << PORTCON_PORTC_PU_C10_WIDTH) - 1U) << PORTCON_PORTC_PU_C10_SHIFT) +#define PORTCON_PORTC_PU_C10_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C10_BITS_DISABLE (PORTCON_PORTC_PU_C10_VALUE_DISABLE << PORTCON_PORTC_PU_C10_SHIFT) +#define PORTCON_PORTC_PU_C10_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C10_BITS_ENABLE (PORTCON_PORTC_PU_C10_VALUE_ENABLE << PORTCON_PORTC_PU_C10_SHIFT) + +#define PORTCON_PORTC_PU_C11_SHIFT 11 +#define PORTCON_PORTC_PU_C11_WIDTH 1 +#define PORTCON_PORTC_PU_C11_MASK (((1U << PORTCON_PORTC_PU_C11_WIDTH) - 1U) << PORTCON_PORTC_PU_C11_SHIFT) +#define PORTCON_PORTC_PU_C11_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C11_BITS_DISABLE (PORTCON_PORTC_PU_C11_VALUE_DISABLE << PORTCON_PORTC_PU_C11_SHIFT) +#define PORTCON_PORTC_PU_C11_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C11_BITS_ENABLE (PORTCON_PORTC_PU_C11_VALUE_ENABLE << PORTCON_PORTC_PU_C11_SHIFT) + +#define PORTCON_PORTC_PU_C12_SHIFT 12 +#define PORTCON_PORTC_PU_C12_WIDTH 1 +#define PORTCON_PORTC_PU_C12_MASK (((1U << PORTCON_PORTC_PU_C12_WIDTH) - 1U) << PORTCON_PORTC_PU_C12_SHIFT) +#define PORTCON_PORTC_PU_C12_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C12_BITS_DISABLE (PORTCON_PORTC_PU_C12_VALUE_DISABLE << PORTCON_PORTC_PU_C12_SHIFT) +#define PORTCON_PORTC_PU_C12_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C12_BITS_ENABLE (PORTCON_PORTC_PU_C12_VALUE_ENABLE << PORTCON_PORTC_PU_C12_SHIFT) + +#define PORTCON_PORTC_PU_C13_SHIFT 13 +#define PORTCON_PORTC_PU_C13_WIDTH 1 +#define PORTCON_PORTC_PU_C13_MASK (((1U << PORTCON_PORTC_PU_C13_WIDTH) - 1U) << PORTCON_PORTC_PU_C13_SHIFT) +#define PORTCON_PORTC_PU_C13_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C13_BITS_DISABLE (PORTCON_PORTC_PU_C13_VALUE_DISABLE << PORTCON_PORTC_PU_C13_SHIFT) +#define PORTCON_PORTC_PU_C13_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C13_BITS_ENABLE (PORTCON_PORTC_PU_C13_VALUE_ENABLE << PORTCON_PORTC_PU_C13_SHIFT) + +#define PORTCON_PORTC_PU_C14_SHIFT 14 +#define PORTCON_PORTC_PU_C14_WIDTH 1 +#define PORTCON_PORTC_PU_C14_MASK (((1U << PORTCON_PORTC_PU_C14_WIDTH) - 1U) << PORTCON_PORTC_PU_C14_SHIFT) +#define PORTCON_PORTC_PU_C14_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C14_BITS_DISABLE (PORTCON_PORTC_PU_C14_VALUE_DISABLE << PORTCON_PORTC_PU_C14_SHIFT) +#define PORTCON_PORTC_PU_C14_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C14_BITS_ENABLE (PORTCON_PORTC_PU_C14_VALUE_ENABLE << PORTCON_PORTC_PU_C14_SHIFT) + +#define PORTCON_PORTC_PU_C15_SHIFT 15 +#define PORTCON_PORTC_PU_C15_WIDTH 1 +#define PORTCON_PORTC_PU_C15_MASK (((1U << PORTCON_PORTC_PU_C15_WIDTH) - 1U) << PORTCON_PORTC_PU_C15_SHIFT) +#define PORTCON_PORTC_PU_C15_VALUE_DISABLE 0U +#define PORTCON_PORTC_PU_C15_BITS_DISABLE (PORTCON_PORTC_PU_C15_VALUE_DISABLE << PORTCON_PORTC_PU_C15_SHIFT) +#define PORTCON_PORTC_PU_C15_VALUE_ENABLE 1U +#define PORTCON_PORTC_PU_C15_BITS_ENABLE (PORTCON_PORTC_PU_C15_VALUE_ENABLE << PORTCON_PORTC_PU_C15_SHIFT) + +#define PORTCON_PORTA_PD_ADDR (PORTCON_BASE_ADDR + 0x0300U) +#define PORTCON_PORTA_PD (*(volatile uint32_t *)PORTCON_PORTA_PD_ADDR) +#define PORTCON_PORTA_PD_A0_SHIFT 0 +#define PORTCON_PORTA_PD_A0_WIDTH 1 +#define PORTCON_PORTA_PD_A0_MASK (((1U << PORTCON_PORTA_PD_A0_WIDTH) - 1U) << PORTCON_PORTA_PD_A0_SHIFT) +#define PORTCON_PORTA_PD_A0_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A0_BITS_DISABLE (PORTCON_PORTA_PD_A0_VALUE_DISABLE << PORTCON_PORTA_PD_A0_SHIFT) +#define PORTCON_PORTA_PD_A0_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A0_BITS_ENABLE (PORTCON_PORTA_PD_A0_VALUE_ENABLE << PORTCON_PORTA_PD_A0_SHIFT) + +#define PORTCON_PORTA_PD_A1_SHIFT 1 +#define PORTCON_PORTA_PD_A1_WIDTH 1 +#define PORTCON_PORTA_PD_A1_MASK (((1U << PORTCON_PORTA_PD_A1_WIDTH) - 1U) << PORTCON_PORTA_PD_A1_SHIFT) +#define PORTCON_PORTA_PD_A1_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A1_BITS_DISABLE (PORTCON_PORTA_PD_A1_VALUE_DISABLE << PORTCON_PORTA_PD_A1_SHIFT) +#define PORTCON_PORTA_PD_A1_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A1_BITS_ENABLE (PORTCON_PORTA_PD_A1_VALUE_ENABLE << PORTCON_PORTA_PD_A1_SHIFT) + +#define PORTCON_PORTA_PD_A2_SHIFT 2 +#define PORTCON_PORTA_PD_A2_WIDTH 1 +#define PORTCON_PORTA_PD_A2_MASK (((1U << PORTCON_PORTA_PD_A2_WIDTH) - 1U) << PORTCON_PORTA_PD_A2_SHIFT) +#define PORTCON_PORTA_PD_A2_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A2_BITS_DISABLE (PORTCON_PORTA_PD_A2_VALUE_DISABLE << PORTCON_PORTA_PD_A2_SHIFT) +#define PORTCON_PORTA_PD_A2_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A2_BITS_ENABLE (PORTCON_PORTA_PD_A2_VALUE_ENABLE << PORTCON_PORTA_PD_A2_SHIFT) + +#define PORTCON_PORTA_PD_A3_SHIFT 3 +#define PORTCON_PORTA_PD_A3_WIDTH 1 +#define PORTCON_PORTA_PD_A3_MASK (((1U << PORTCON_PORTA_PD_A3_WIDTH) - 1U) << PORTCON_PORTA_PD_A3_SHIFT) +#define PORTCON_PORTA_PD_A3_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A3_BITS_DISABLE (PORTCON_PORTA_PD_A3_VALUE_DISABLE << PORTCON_PORTA_PD_A3_SHIFT) +#define PORTCON_PORTA_PD_A3_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A3_BITS_ENABLE (PORTCON_PORTA_PD_A3_VALUE_ENABLE << PORTCON_PORTA_PD_A3_SHIFT) + +#define PORTCON_PORTA_PD_A4_SHIFT 4 +#define PORTCON_PORTA_PD_A4_WIDTH 1 +#define PORTCON_PORTA_PD_A4_MASK (((1U << PORTCON_PORTA_PD_A4_WIDTH) - 1U) << PORTCON_PORTA_PD_A4_SHIFT) +#define PORTCON_PORTA_PD_A4_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A4_BITS_DISABLE (PORTCON_PORTA_PD_A4_VALUE_DISABLE << PORTCON_PORTA_PD_A4_SHIFT) +#define PORTCON_PORTA_PD_A4_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A4_BITS_ENABLE (PORTCON_PORTA_PD_A4_VALUE_ENABLE << PORTCON_PORTA_PD_A4_SHIFT) + +#define PORTCON_PORTA_PD_A5_SHIFT 5 +#define PORTCON_PORTA_PD_A5_WIDTH 1 +#define PORTCON_PORTA_PD_A5_MASK (((1U << PORTCON_PORTA_PD_A5_WIDTH) - 1U) << PORTCON_PORTA_PD_A5_SHIFT) +#define PORTCON_PORTA_PD_A5_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A5_BITS_DISABLE (PORTCON_PORTA_PD_A5_VALUE_DISABLE << PORTCON_PORTA_PD_A5_SHIFT) +#define PORTCON_PORTA_PD_A5_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A5_BITS_ENABLE (PORTCON_PORTA_PD_A5_VALUE_ENABLE << PORTCON_PORTA_PD_A5_SHIFT) + +#define PORTCON_PORTA_PD_A6_SHIFT 6 +#define PORTCON_PORTA_PD_A6_WIDTH 1 +#define PORTCON_PORTA_PD_A6_MASK (((1U << PORTCON_PORTA_PD_A6_WIDTH) - 1U) << PORTCON_PORTA_PD_A6_SHIFT) +#define PORTCON_PORTA_PD_A6_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A6_BITS_DISABLE (PORTCON_PORTA_PD_A6_VALUE_DISABLE << PORTCON_PORTA_PD_A6_SHIFT) +#define PORTCON_PORTA_PD_A6_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A6_BITS_ENABLE (PORTCON_PORTA_PD_A6_VALUE_ENABLE << PORTCON_PORTA_PD_A6_SHIFT) + +#define PORTCON_PORTA_PD_A7_SHIFT 7 +#define PORTCON_PORTA_PD_A7_WIDTH 1 +#define PORTCON_PORTA_PD_A7_MASK (((1U << PORTCON_PORTA_PD_A7_WIDTH) - 1U) << PORTCON_PORTA_PD_A7_SHIFT) +#define PORTCON_PORTA_PD_A7_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A7_BITS_DISABLE (PORTCON_PORTA_PD_A7_VALUE_DISABLE << PORTCON_PORTA_PD_A7_SHIFT) +#define PORTCON_PORTA_PD_A7_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A7_BITS_ENABLE (PORTCON_PORTA_PD_A7_VALUE_ENABLE << PORTCON_PORTA_PD_A7_SHIFT) + +#define PORTCON_PORTA_PD_A8_SHIFT 8 +#define PORTCON_PORTA_PD_A8_WIDTH 1 +#define PORTCON_PORTA_PD_A8_MASK (((1U << PORTCON_PORTA_PD_A8_WIDTH) - 1U) << PORTCON_PORTA_PD_A8_SHIFT) +#define PORTCON_PORTA_PD_A8_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A8_BITS_DISABLE (PORTCON_PORTA_PD_A8_VALUE_DISABLE << PORTCON_PORTA_PD_A8_SHIFT) +#define PORTCON_PORTA_PD_A8_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A8_BITS_ENABLE (PORTCON_PORTA_PD_A8_VALUE_ENABLE << PORTCON_PORTA_PD_A8_SHIFT) + +#define PORTCON_PORTA_PD_A9_SHIFT 9 +#define PORTCON_PORTA_PD_A9_WIDTH 1 +#define PORTCON_PORTA_PD_A9_MASK (((1U << PORTCON_PORTA_PD_A9_WIDTH) - 1U) << PORTCON_PORTA_PD_A9_SHIFT) +#define PORTCON_PORTA_PD_A9_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A9_BITS_DISABLE (PORTCON_PORTA_PD_A9_VALUE_DISABLE << PORTCON_PORTA_PD_A9_SHIFT) +#define PORTCON_PORTA_PD_A9_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A9_BITS_ENABLE (PORTCON_PORTA_PD_A9_VALUE_ENABLE << PORTCON_PORTA_PD_A9_SHIFT) + +#define PORTCON_PORTA_PD_A10_SHIFT 10 +#define PORTCON_PORTA_PD_A10_WIDTH 1 +#define PORTCON_PORTA_PD_A10_MASK (((1U << PORTCON_PORTA_PD_A10_WIDTH) - 1U) << PORTCON_PORTA_PD_A10_SHIFT) +#define PORTCON_PORTA_PD_A10_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A10_BITS_DISABLE (PORTCON_PORTA_PD_A10_VALUE_DISABLE << PORTCON_PORTA_PD_A10_SHIFT) +#define PORTCON_PORTA_PD_A10_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A10_BITS_ENABLE (PORTCON_PORTA_PD_A10_VALUE_ENABLE << PORTCON_PORTA_PD_A10_SHIFT) + +#define PORTCON_PORTA_PD_A11_SHIFT 11 +#define PORTCON_PORTA_PD_A11_WIDTH 1 +#define PORTCON_PORTA_PD_A11_MASK (((1U << PORTCON_PORTA_PD_A11_WIDTH) - 1U) << PORTCON_PORTA_PD_A11_SHIFT) +#define PORTCON_PORTA_PD_A11_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A11_BITS_DISABLE (PORTCON_PORTA_PD_A11_VALUE_DISABLE << PORTCON_PORTA_PD_A11_SHIFT) +#define PORTCON_PORTA_PD_A11_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A11_BITS_ENABLE (PORTCON_PORTA_PD_A11_VALUE_ENABLE << PORTCON_PORTA_PD_A11_SHIFT) + +#define PORTCON_PORTA_PD_A12_SHIFT 12 +#define PORTCON_PORTA_PD_A12_WIDTH 1 +#define PORTCON_PORTA_PD_A12_MASK (((1U << PORTCON_PORTA_PD_A12_WIDTH) - 1U) << PORTCON_PORTA_PD_A12_SHIFT) +#define PORTCON_PORTA_PD_A12_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A12_BITS_DISABLE (PORTCON_PORTA_PD_A12_VALUE_DISABLE << PORTCON_PORTA_PD_A12_SHIFT) +#define PORTCON_PORTA_PD_A12_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A12_BITS_ENABLE (PORTCON_PORTA_PD_A12_VALUE_ENABLE << PORTCON_PORTA_PD_A12_SHIFT) + +#define PORTCON_PORTA_PD_A13_SHIFT 13 +#define PORTCON_PORTA_PD_A13_WIDTH 1 +#define PORTCON_PORTA_PD_A13_MASK (((1U << PORTCON_PORTA_PD_A13_WIDTH) - 1U) << PORTCON_PORTA_PD_A13_SHIFT) +#define PORTCON_PORTA_PD_A13_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A13_BITS_DISABLE (PORTCON_PORTA_PD_A13_VALUE_DISABLE << PORTCON_PORTA_PD_A13_SHIFT) +#define PORTCON_PORTA_PD_A13_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A13_BITS_ENABLE (PORTCON_PORTA_PD_A13_VALUE_ENABLE << PORTCON_PORTA_PD_A13_SHIFT) + +#define PORTCON_PORTA_PD_A14_SHIFT 14 +#define PORTCON_PORTA_PD_A14_WIDTH 1 +#define PORTCON_PORTA_PD_A14_MASK (((1U << PORTCON_PORTA_PD_A14_WIDTH) - 1U) << PORTCON_PORTA_PD_A14_SHIFT) +#define PORTCON_PORTA_PD_A14_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A14_BITS_DISABLE (PORTCON_PORTA_PD_A14_VALUE_DISABLE << PORTCON_PORTA_PD_A14_SHIFT) +#define PORTCON_PORTA_PD_A14_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A14_BITS_ENABLE (PORTCON_PORTA_PD_A14_VALUE_ENABLE << PORTCON_PORTA_PD_A14_SHIFT) + +#define PORTCON_PORTA_PD_A15_SHIFT 15 +#define PORTCON_PORTA_PD_A15_WIDTH 1 +#define PORTCON_PORTA_PD_A15_MASK (((1U << PORTCON_PORTA_PD_A15_WIDTH) - 1U) << PORTCON_PORTA_PD_A15_SHIFT) +#define PORTCON_PORTA_PD_A15_VALUE_DISABLE 0U +#define PORTCON_PORTA_PD_A15_BITS_DISABLE (PORTCON_PORTA_PD_A15_VALUE_DISABLE << PORTCON_PORTA_PD_A15_SHIFT) +#define PORTCON_PORTA_PD_A15_VALUE_ENABLE 1U +#define PORTCON_PORTA_PD_A15_BITS_ENABLE (PORTCON_PORTA_PD_A15_VALUE_ENABLE << PORTCON_PORTA_PD_A15_SHIFT) + +#define PORTCON_PORTB_PD_ADDR (PORTCON_BASE_ADDR + 0x0304U) +#define PORTCON_PORTB_PD (*(volatile uint32_t *)PORTCON_PORTB_PD_ADDR) +#define PORTCON_PORTB_PD_B0_SHIFT 0 +#define PORTCON_PORTB_PD_B0_WIDTH 1 +#define PORTCON_PORTB_PD_B0_MASK (((1U << PORTCON_PORTB_PD_B0_WIDTH) - 1U) << PORTCON_PORTB_PD_B0_SHIFT) +#define PORTCON_PORTB_PD_B0_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B0_BITS_DISABLE (PORTCON_PORTB_PD_B0_VALUE_DISABLE << PORTCON_PORTB_PD_B0_SHIFT) +#define PORTCON_PORTB_PD_B0_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B0_BITS_ENABLE (PORTCON_PORTB_PD_B0_VALUE_ENABLE << PORTCON_PORTB_PD_B0_SHIFT) + +#define PORTCON_PORTB_PD_B1_SHIFT 1 +#define PORTCON_PORTB_PD_B1_WIDTH 1 +#define PORTCON_PORTB_PD_B1_MASK (((1U << PORTCON_PORTB_PD_B1_WIDTH) - 1U) << PORTCON_PORTB_PD_B1_SHIFT) +#define PORTCON_PORTB_PD_B1_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B1_BITS_DISABLE (PORTCON_PORTB_PD_B1_VALUE_DISABLE << PORTCON_PORTB_PD_B1_SHIFT) +#define PORTCON_PORTB_PD_B1_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B1_BITS_ENABLE (PORTCON_PORTB_PD_B1_VALUE_ENABLE << PORTCON_PORTB_PD_B1_SHIFT) + +#define PORTCON_PORTB_PD_B2_SHIFT 2 +#define PORTCON_PORTB_PD_B2_WIDTH 1 +#define PORTCON_PORTB_PD_B2_MASK (((1U << PORTCON_PORTB_PD_B2_WIDTH) - 1U) << PORTCON_PORTB_PD_B2_SHIFT) +#define PORTCON_PORTB_PD_B2_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B2_BITS_DISABLE (PORTCON_PORTB_PD_B2_VALUE_DISABLE << PORTCON_PORTB_PD_B2_SHIFT) +#define PORTCON_PORTB_PD_B2_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B2_BITS_ENABLE (PORTCON_PORTB_PD_B2_VALUE_ENABLE << PORTCON_PORTB_PD_B2_SHIFT) + +#define PORTCON_PORTB_PD_B3_SHIFT 3 +#define PORTCON_PORTB_PD_B3_WIDTH 1 +#define PORTCON_PORTB_PD_B3_MASK (((1U << PORTCON_PORTB_PD_B3_WIDTH) - 1U) << PORTCON_PORTB_PD_B3_SHIFT) +#define PORTCON_PORTB_PD_B3_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B3_BITS_DISABLE (PORTCON_PORTB_PD_B3_VALUE_DISABLE << PORTCON_PORTB_PD_B3_SHIFT) +#define PORTCON_PORTB_PD_B3_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B3_BITS_ENABLE (PORTCON_PORTB_PD_B3_VALUE_ENABLE << PORTCON_PORTB_PD_B3_SHIFT) + +#define PORTCON_PORTB_PD_B4_SHIFT 4 +#define PORTCON_PORTB_PD_B4_WIDTH 1 +#define PORTCON_PORTB_PD_B4_MASK (((1U << PORTCON_PORTB_PD_B4_WIDTH) - 1U) << PORTCON_PORTB_PD_B4_SHIFT) +#define PORTCON_PORTB_PD_B4_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B4_BITS_DISABLE (PORTCON_PORTB_PD_B4_VALUE_DISABLE << PORTCON_PORTB_PD_B4_SHIFT) +#define PORTCON_PORTB_PD_B4_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B4_BITS_ENABLE (PORTCON_PORTB_PD_B4_VALUE_ENABLE << PORTCON_PORTB_PD_B4_SHIFT) + +#define PORTCON_PORTB_PD_B5_SHIFT 5 +#define PORTCON_PORTB_PD_B5_WIDTH 1 +#define PORTCON_PORTB_PD_B5_MASK (((1U << PORTCON_PORTB_PD_B5_WIDTH) - 1U) << PORTCON_PORTB_PD_B5_SHIFT) +#define PORTCON_PORTB_PD_B5_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B5_BITS_DISABLE (PORTCON_PORTB_PD_B5_VALUE_DISABLE << PORTCON_PORTB_PD_B5_SHIFT) +#define PORTCON_PORTB_PD_B5_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B5_BITS_ENABLE (PORTCON_PORTB_PD_B5_VALUE_ENABLE << PORTCON_PORTB_PD_B5_SHIFT) + +#define PORTCON_PORTB_PD_B6_SHIFT 6 +#define PORTCON_PORTB_PD_B6_WIDTH 1 +#define PORTCON_PORTB_PD_B6_MASK (((1U << PORTCON_PORTB_PD_B6_WIDTH) - 1U) << PORTCON_PORTB_PD_B6_SHIFT) +#define PORTCON_PORTB_PD_B6_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B6_BITS_DISABLE (PORTCON_PORTB_PD_B6_VALUE_DISABLE << PORTCON_PORTB_PD_B6_SHIFT) +#define PORTCON_PORTB_PD_B6_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B6_BITS_ENABLE (PORTCON_PORTB_PD_B6_VALUE_ENABLE << PORTCON_PORTB_PD_B6_SHIFT) + +#define PORTCON_PORTB_PD_B7_SHIFT 7 +#define PORTCON_PORTB_PD_B7_WIDTH 1 +#define PORTCON_PORTB_PD_B7_MASK (((1U << PORTCON_PORTB_PD_B7_WIDTH) - 1U) << PORTCON_PORTB_PD_B7_SHIFT) +#define PORTCON_PORTB_PD_B7_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B7_BITS_DISABLE (PORTCON_PORTB_PD_B7_VALUE_DISABLE << PORTCON_PORTB_PD_B7_SHIFT) +#define PORTCON_PORTB_PD_B7_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B7_BITS_ENABLE (PORTCON_PORTB_PD_B7_VALUE_ENABLE << PORTCON_PORTB_PD_B7_SHIFT) + +#define PORTCON_PORTB_PD_B8_SHIFT 8 +#define PORTCON_PORTB_PD_B8_WIDTH 1 +#define PORTCON_PORTB_PD_B8_MASK (((1U << PORTCON_PORTB_PD_B8_WIDTH) - 1U) << PORTCON_PORTB_PD_B8_SHIFT) +#define PORTCON_PORTB_PD_B8_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B8_BITS_DISABLE (PORTCON_PORTB_PD_B8_VALUE_DISABLE << PORTCON_PORTB_PD_B8_SHIFT) +#define PORTCON_PORTB_PD_B8_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B8_BITS_ENABLE (PORTCON_PORTB_PD_B8_VALUE_ENABLE << PORTCON_PORTB_PD_B8_SHIFT) + +#define PORTCON_PORTB_PD_B9_SHIFT 9 +#define PORTCON_PORTB_PD_B9_WIDTH 1 +#define PORTCON_PORTB_PD_B9_MASK (((1U << PORTCON_PORTB_PD_B9_WIDTH) - 1U) << PORTCON_PORTB_PD_B9_SHIFT) +#define PORTCON_PORTB_PD_B9_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B9_BITS_DISABLE (PORTCON_PORTB_PD_B9_VALUE_DISABLE << PORTCON_PORTB_PD_B9_SHIFT) +#define PORTCON_PORTB_PD_B9_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B9_BITS_ENABLE (PORTCON_PORTB_PD_B9_VALUE_ENABLE << PORTCON_PORTB_PD_B9_SHIFT) + +#define PORTCON_PORTB_PD_B10_SHIFT 10 +#define PORTCON_PORTB_PD_B10_WIDTH 1 +#define PORTCON_PORTB_PD_B10_MASK (((1U << PORTCON_PORTB_PD_B10_WIDTH) - 1U) << PORTCON_PORTB_PD_B10_SHIFT) +#define PORTCON_PORTB_PD_B10_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B10_BITS_DISABLE (PORTCON_PORTB_PD_B10_VALUE_DISABLE << PORTCON_PORTB_PD_B10_SHIFT) +#define PORTCON_PORTB_PD_B10_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B10_BITS_ENABLE (PORTCON_PORTB_PD_B10_VALUE_ENABLE << PORTCON_PORTB_PD_B10_SHIFT) + +#define PORTCON_PORTB_PD_B11_SHIFT 11 +#define PORTCON_PORTB_PD_B11_WIDTH 1 +#define PORTCON_PORTB_PD_B11_MASK (((1U << PORTCON_PORTB_PD_B11_WIDTH) - 1U) << PORTCON_PORTB_PD_B11_SHIFT) +#define PORTCON_PORTB_PD_B11_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B11_BITS_DISABLE (PORTCON_PORTB_PD_B11_VALUE_DISABLE << PORTCON_PORTB_PD_B11_SHIFT) +#define PORTCON_PORTB_PD_B11_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B11_BITS_ENABLE (PORTCON_PORTB_PD_B11_VALUE_ENABLE << PORTCON_PORTB_PD_B11_SHIFT) + +#define PORTCON_PORTB_PD_B12_SHIFT 12 +#define PORTCON_PORTB_PD_B12_WIDTH 1 +#define PORTCON_PORTB_PD_B12_MASK (((1U << PORTCON_PORTB_PD_B12_WIDTH) - 1U) << PORTCON_PORTB_PD_B12_SHIFT) +#define PORTCON_PORTB_PD_B12_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B12_BITS_DISABLE (PORTCON_PORTB_PD_B12_VALUE_DISABLE << PORTCON_PORTB_PD_B12_SHIFT) +#define PORTCON_PORTB_PD_B12_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B12_BITS_ENABLE (PORTCON_PORTB_PD_B12_VALUE_ENABLE << PORTCON_PORTB_PD_B12_SHIFT) + +#define PORTCON_PORTB_PD_B13_SHIFT 13 +#define PORTCON_PORTB_PD_B13_WIDTH 1 +#define PORTCON_PORTB_PD_B13_MASK (((1U << PORTCON_PORTB_PD_B13_WIDTH) - 1U) << PORTCON_PORTB_PD_B13_SHIFT) +#define PORTCON_PORTB_PD_B13_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B13_BITS_DISABLE (PORTCON_PORTB_PD_B13_VALUE_DISABLE << PORTCON_PORTB_PD_B13_SHIFT) +#define PORTCON_PORTB_PD_B13_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B13_BITS_ENABLE (PORTCON_PORTB_PD_B13_VALUE_ENABLE << PORTCON_PORTB_PD_B13_SHIFT) + +#define PORTCON_PORTB_PD_B14_SHIFT 14 +#define PORTCON_PORTB_PD_B14_WIDTH 1 +#define PORTCON_PORTB_PD_B14_MASK (((1U << PORTCON_PORTB_PD_B14_WIDTH) - 1U) << PORTCON_PORTB_PD_B14_SHIFT) +#define PORTCON_PORTB_PD_B14_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B14_BITS_DISABLE (PORTCON_PORTB_PD_B14_VALUE_DISABLE << PORTCON_PORTB_PD_B14_SHIFT) +#define PORTCON_PORTB_PD_B14_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B14_BITS_ENABLE (PORTCON_PORTB_PD_B14_VALUE_ENABLE << PORTCON_PORTB_PD_B14_SHIFT) + +#define PORTCON_PORTB_PD_B15_SHIFT 15 +#define PORTCON_PORTB_PD_B15_WIDTH 1 +#define PORTCON_PORTB_PD_B15_MASK (((1U << PORTCON_PORTB_PD_B15_WIDTH) - 1U) << PORTCON_PORTB_PD_B15_SHIFT) +#define PORTCON_PORTB_PD_B15_VALUE_DISABLE 0U +#define PORTCON_PORTB_PD_B15_BITS_DISABLE (PORTCON_PORTB_PD_B15_VALUE_DISABLE << PORTCON_PORTB_PD_B15_SHIFT) +#define PORTCON_PORTB_PD_B15_VALUE_ENABLE 1U +#define PORTCON_PORTB_PD_B15_BITS_ENABLE (PORTCON_PORTB_PD_B15_VALUE_ENABLE << PORTCON_PORTB_PD_B15_SHIFT) + +#define PORTCON_PORTC_PD_ADDR (PORTCON_BASE_ADDR + 0x0308U) +#define PORTCON_PORTC_PD (*(volatile uint32_t *)PORTCON_PORTC_PD_ADDR) +#define PORTCON_PORTC_PD_C0_SHIFT 0 +#define PORTCON_PORTC_PD_C0_WIDTH 1 +#define PORTCON_PORTC_PD_C0_MASK (((1U << PORTCON_PORTC_PD_C0_WIDTH) - 1U) << PORTCON_PORTC_PD_C0_SHIFT) +#define PORTCON_PORTC_PD_C0_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C0_BITS_DISABLE (PORTCON_PORTC_PD_C0_VALUE_DISABLE << PORTCON_PORTC_PD_C0_SHIFT) +#define PORTCON_PORTC_PD_C0_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C0_BITS_ENABLE (PORTCON_PORTC_PD_C0_VALUE_ENABLE << PORTCON_PORTC_PD_C0_SHIFT) + +#define PORTCON_PORTC_PD_C1_SHIFT 1 +#define PORTCON_PORTC_PD_C1_WIDTH 1 +#define PORTCON_PORTC_PD_C1_MASK (((1U << PORTCON_PORTC_PD_C1_WIDTH) - 1U) << PORTCON_PORTC_PD_C1_SHIFT) +#define PORTCON_PORTC_PD_C1_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C1_BITS_DISABLE (PORTCON_PORTC_PD_C1_VALUE_DISABLE << PORTCON_PORTC_PD_C1_SHIFT) +#define PORTCON_PORTC_PD_C1_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C1_BITS_ENABLE (PORTCON_PORTC_PD_C1_VALUE_ENABLE << PORTCON_PORTC_PD_C1_SHIFT) + +#define PORTCON_PORTC_PD_C2_SHIFT 2 +#define PORTCON_PORTC_PD_C2_WIDTH 1 +#define PORTCON_PORTC_PD_C2_MASK (((1U << PORTCON_PORTC_PD_C2_WIDTH) - 1U) << PORTCON_PORTC_PD_C2_SHIFT) +#define PORTCON_PORTC_PD_C2_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C2_BITS_DISABLE (PORTCON_PORTC_PD_C2_VALUE_DISABLE << PORTCON_PORTC_PD_C2_SHIFT) +#define PORTCON_PORTC_PD_C2_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C2_BITS_ENABLE (PORTCON_PORTC_PD_C2_VALUE_ENABLE << PORTCON_PORTC_PD_C2_SHIFT) + +#define PORTCON_PORTC_PD_C3_SHIFT 3 +#define PORTCON_PORTC_PD_C3_WIDTH 1 +#define PORTCON_PORTC_PD_C3_MASK (((1U << PORTCON_PORTC_PD_C3_WIDTH) - 1U) << PORTCON_PORTC_PD_C3_SHIFT) +#define PORTCON_PORTC_PD_C3_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C3_BITS_DISABLE (PORTCON_PORTC_PD_C3_VALUE_DISABLE << PORTCON_PORTC_PD_C3_SHIFT) +#define PORTCON_PORTC_PD_C3_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C3_BITS_ENABLE (PORTCON_PORTC_PD_C3_VALUE_ENABLE << PORTCON_PORTC_PD_C3_SHIFT) + +#define PORTCON_PORTC_PD_C4_SHIFT 4 +#define PORTCON_PORTC_PD_C4_WIDTH 1 +#define PORTCON_PORTC_PD_C4_MASK (((1U << PORTCON_PORTC_PD_C4_WIDTH) - 1U) << PORTCON_PORTC_PD_C4_SHIFT) +#define PORTCON_PORTC_PD_C4_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C4_BITS_DISABLE (PORTCON_PORTC_PD_C4_VALUE_DISABLE << PORTCON_PORTC_PD_C4_SHIFT) +#define PORTCON_PORTC_PD_C4_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C4_BITS_ENABLE (PORTCON_PORTC_PD_C4_VALUE_ENABLE << PORTCON_PORTC_PD_C4_SHIFT) + +#define PORTCON_PORTC_PD_C5_SHIFT 5 +#define PORTCON_PORTC_PD_C5_WIDTH 1 +#define PORTCON_PORTC_PD_C5_MASK (((1U << PORTCON_PORTC_PD_C5_WIDTH) - 1U) << PORTCON_PORTC_PD_C5_SHIFT) +#define PORTCON_PORTC_PD_C5_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C5_BITS_DISABLE (PORTCON_PORTC_PD_C5_VALUE_DISABLE << PORTCON_PORTC_PD_C5_SHIFT) +#define PORTCON_PORTC_PD_C5_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C5_BITS_ENABLE (PORTCON_PORTC_PD_C5_VALUE_ENABLE << PORTCON_PORTC_PD_C5_SHIFT) + +#define PORTCON_PORTC_PD_C6_SHIFT 6 +#define PORTCON_PORTC_PD_C6_WIDTH 1 +#define PORTCON_PORTC_PD_C6_MASK (((1U << PORTCON_PORTC_PD_C6_WIDTH) - 1U) << PORTCON_PORTC_PD_C6_SHIFT) +#define PORTCON_PORTC_PD_C6_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C6_BITS_DISABLE (PORTCON_PORTC_PD_C6_VALUE_DISABLE << PORTCON_PORTC_PD_C6_SHIFT) +#define PORTCON_PORTC_PD_C6_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C6_BITS_ENABLE (PORTCON_PORTC_PD_C6_VALUE_ENABLE << PORTCON_PORTC_PD_C6_SHIFT) + +#define PORTCON_PORTC_PD_C7_SHIFT 7 +#define PORTCON_PORTC_PD_C7_WIDTH 1 +#define PORTCON_PORTC_PD_C7_MASK (((1U << PORTCON_PORTC_PD_C7_WIDTH) - 1U) << PORTCON_PORTC_PD_C7_SHIFT) +#define PORTCON_PORTC_PD_C7_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C7_BITS_DISABLE (PORTCON_PORTC_PD_C7_VALUE_DISABLE << PORTCON_PORTC_PD_C7_SHIFT) +#define PORTCON_PORTC_PD_C7_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C7_BITS_ENABLE (PORTCON_PORTC_PD_C7_VALUE_ENABLE << PORTCON_PORTC_PD_C7_SHIFT) + +#define PORTCON_PORTC_PD_C8_SHIFT 8 +#define PORTCON_PORTC_PD_C8_WIDTH 1 +#define PORTCON_PORTC_PD_C8_MASK (((1U << PORTCON_PORTC_PD_C8_WIDTH) - 1U) << PORTCON_PORTC_PD_C8_SHIFT) +#define PORTCON_PORTC_PD_C8_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C8_BITS_DISABLE (PORTCON_PORTC_PD_C8_VALUE_DISABLE << PORTCON_PORTC_PD_C8_SHIFT) +#define PORTCON_PORTC_PD_C8_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C8_BITS_ENABLE (PORTCON_PORTC_PD_C8_VALUE_ENABLE << PORTCON_PORTC_PD_C8_SHIFT) + +#define PORTCON_PORTC_PD_C9_SHIFT 9 +#define PORTCON_PORTC_PD_C9_WIDTH 1 +#define PORTCON_PORTC_PD_C9_MASK (((1U << PORTCON_PORTC_PD_C9_WIDTH) - 1U) << PORTCON_PORTC_PD_C9_SHIFT) +#define PORTCON_PORTC_PD_C9_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C9_BITS_DISABLE (PORTCON_PORTC_PD_C9_VALUE_DISABLE << PORTCON_PORTC_PD_C9_SHIFT) +#define PORTCON_PORTC_PD_C9_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C9_BITS_ENABLE (PORTCON_PORTC_PD_C9_VALUE_ENABLE << PORTCON_PORTC_PD_C9_SHIFT) + +#define PORTCON_PORTC_PD_C10_SHIFT 10 +#define PORTCON_PORTC_PD_C10_WIDTH 1 +#define PORTCON_PORTC_PD_C10_MASK (((1U << PORTCON_PORTC_PD_C10_WIDTH) - 1U) << PORTCON_PORTC_PD_C10_SHIFT) +#define PORTCON_PORTC_PD_C10_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C10_BITS_DISABLE (PORTCON_PORTC_PD_C10_VALUE_DISABLE << PORTCON_PORTC_PD_C10_SHIFT) +#define PORTCON_PORTC_PD_C10_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C10_BITS_ENABLE (PORTCON_PORTC_PD_C10_VALUE_ENABLE << PORTCON_PORTC_PD_C10_SHIFT) + +#define PORTCON_PORTC_PD_C11_SHIFT 11 +#define PORTCON_PORTC_PD_C11_WIDTH 1 +#define PORTCON_PORTC_PD_C11_MASK (((1U << PORTCON_PORTC_PD_C11_WIDTH) - 1U) << PORTCON_PORTC_PD_C11_SHIFT) +#define PORTCON_PORTC_PD_C11_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C11_BITS_DISABLE (PORTCON_PORTC_PD_C11_VALUE_DISABLE << PORTCON_PORTC_PD_C11_SHIFT) +#define PORTCON_PORTC_PD_C11_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C11_BITS_ENABLE (PORTCON_PORTC_PD_C11_VALUE_ENABLE << PORTCON_PORTC_PD_C11_SHIFT) + +#define PORTCON_PORTC_PD_C12_SHIFT 12 +#define PORTCON_PORTC_PD_C12_WIDTH 1 +#define PORTCON_PORTC_PD_C12_MASK (((1U << PORTCON_PORTC_PD_C12_WIDTH) - 1U) << PORTCON_PORTC_PD_C12_SHIFT) +#define PORTCON_PORTC_PD_C12_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C12_BITS_DISABLE (PORTCON_PORTC_PD_C12_VALUE_DISABLE << PORTCON_PORTC_PD_C12_SHIFT) +#define PORTCON_PORTC_PD_C12_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C12_BITS_ENABLE (PORTCON_PORTC_PD_C12_VALUE_ENABLE << PORTCON_PORTC_PD_C12_SHIFT) + +#define PORTCON_PORTC_PD_C13_SHIFT 13 +#define PORTCON_PORTC_PD_C13_WIDTH 1 +#define PORTCON_PORTC_PD_C13_MASK (((1U << PORTCON_PORTC_PD_C13_WIDTH) - 1U) << PORTCON_PORTC_PD_C13_SHIFT) +#define PORTCON_PORTC_PD_C13_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C13_BITS_DISABLE (PORTCON_PORTC_PD_C13_VALUE_DISABLE << PORTCON_PORTC_PD_C13_SHIFT) +#define PORTCON_PORTC_PD_C13_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C13_BITS_ENABLE (PORTCON_PORTC_PD_C13_VALUE_ENABLE << PORTCON_PORTC_PD_C13_SHIFT) + +#define PORTCON_PORTC_PD_C14_SHIFT 14 +#define PORTCON_PORTC_PD_C14_WIDTH 1 +#define PORTCON_PORTC_PD_C14_MASK (((1U << PORTCON_PORTC_PD_C14_WIDTH) - 1U) << PORTCON_PORTC_PD_C14_SHIFT) +#define PORTCON_PORTC_PD_C14_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C14_BITS_DISABLE (PORTCON_PORTC_PD_C14_VALUE_DISABLE << PORTCON_PORTC_PD_C14_SHIFT) +#define PORTCON_PORTC_PD_C14_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C14_BITS_ENABLE (PORTCON_PORTC_PD_C14_VALUE_ENABLE << PORTCON_PORTC_PD_C14_SHIFT) + +#define PORTCON_PORTC_PD_C15_SHIFT 15 +#define PORTCON_PORTC_PD_C15_WIDTH 1 +#define PORTCON_PORTC_PD_C15_MASK (((1U << PORTCON_PORTC_PD_C15_WIDTH) - 1U) << PORTCON_PORTC_PD_C15_SHIFT) +#define PORTCON_PORTC_PD_C15_VALUE_DISABLE 0U +#define PORTCON_PORTC_PD_C15_BITS_DISABLE (PORTCON_PORTC_PD_C15_VALUE_DISABLE << PORTCON_PORTC_PD_C15_SHIFT) +#define PORTCON_PORTC_PD_C15_VALUE_ENABLE 1U +#define PORTCON_PORTC_PD_C15_BITS_ENABLE (PORTCON_PORTC_PD_C15_VALUE_ENABLE << PORTCON_PORTC_PD_C15_SHIFT) + +#define PORTCON_PORTA_OD_ADDR (PORTCON_BASE_ADDR + 0x0400U) +#define PORTCON_PORTA_OD (*(volatile uint32_t *)PORTCON_PORTA_OD_ADDR) +#define PORTCON_PORTA_OD_A0_SHIFT 0 +#define PORTCON_PORTA_OD_A0_WIDTH 1 +#define PORTCON_PORTA_OD_A0_MASK (((1U << PORTCON_PORTA_OD_A0_WIDTH) - 1U) << PORTCON_PORTA_OD_A0_SHIFT) +#define PORTCON_PORTA_OD_A0_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A0_BITS_DISABLE (PORTCON_PORTA_OD_A0_VALUE_DISABLE << PORTCON_PORTA_OD_A0_SHIFT) +#define PORTCON_PORTA_OD_A0_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A0_BITS_ENABLE (PORTCON_PORTA_OD_A0_VALUE_ENABLE << PORTCON_PORTA_OD_A0_SHIFT) + +#define PORTCON_PORTA_OD_A1_SHIFT 1 +#define PORTCON_PORTA_OD_A1_WIDTH 1 +#define PORTCON_PORTA_OD_A1_MASK (((1U << PORTCON_PORTA_OD_A1_WIDTH) - 1U) << PORTCON_PORTA_OD_A1_SHIFT) +#define PORTCON_PORTA_OD_A1_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A1_BITS_DISABLE (PORTCON_PORTA_OD_A1_VALUE_DISABLE << PORTCON_PORTA_OD_A1_SHIFT) +#define PORTCON_PORTA_OD_A1_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A1_BITS_ENABLE (PORTCON_PORTA_OD_A1_VALUE_ENABLE << PORTCON_PORTA_OD_A1_SHIFT) + +#define PORTCON_PORTA_OD_A2_SHIFT 2 +#define PORTCON_PORTA_OD_A2_WIDTH 1 +#define PORTCON_PORTA_OD_A2_MASK (((1U << PORTCON_PORTA_OD_A2_WIDTH) - 1U) << PORTCON_PORTA_OD_A2_SHIFT) +#define PORTCON_PORTA_OD_A2_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A2_BITS_DISABLE (PORTCON_PORTA_OD_A2_VALUE_DISABLE << PORTCON_PORTA_OD_A2_SHIFT) +#define PORTCON_PORTA_OD_A2_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A2_BITS_ENABLE (PORTCON_PORTA_OD_A2_VALUE_ENABLE << PORTCON_PORTA_OD_A2_SHIFT) + +#define PORTCON_PORTA_OD_A3_SHIFT 3 +#define PORTCON_PORTA_OD_A3_WIDTH 1 +#define PORTCON_PORTA_OD_A3_MASK (((1U << PORTCON_PORTA_OD_A3_WIDTH) - 1U) << PORTCON_PORTA_OD_A3_SHIFT) +#define PORTCON_PORTA_OD_A3_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A3_BITS_DISABLE (PORTCON_PORTA_OD_A3_VALUE_DISABLE << PORTCON_PORTA_OD_A3_SHIFT) +#define PORTCON_PORTA_OD_A3_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A3_BITS_ENABLE (PORTCON_PORTA_OD_A3_VALUE_ENABLE << PORTCON_PORTA_OD_A3_SHIFT) + +#define PORTCON_PORTA_OD_A4_SHIFT 4 +#define PORTCON_PORTA_OD_A4_WIDTH 1 +#define PORTCON_PORTA_OD_A4_MASK (((1U << PORTCON_PORTA_OD_A4_WIDTH) - 1U) << PORTCON_PORTA_OD_A4_SHIFT) +#define PORTCON_PORTA_OD_A4_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A4_BITS_DISABLE (PORTCON_PORTA_OD_A4_VALUE_DISABLE << PORTCON_PORTA_OD_A4_SHIFT) +#define PORTCON_PORTA_OD_A4_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A4_BITS_ENABLE (PORTCON_PORTA_OD_A4_VALUE_ENABLE << PORTCON_PORTA_OD_A4_SHIFT) + +#define PORTCON_PORTA_OD_A5_SHIFT 5 +#define PORTCON_PORTA_OD_A5_WIDTH 1 +#define PORTCON_PORTA_OD_A5_MASK (((1U << PORTCON_PORTA_OD_A5_WIDTH) - 1U) << PORTCON_PORTA_OD_A5_SHIFT) +#define PORTCON_PORTA_OD_A5_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A5_BITS_DISABLE (PORTCON_PORTA_OD_A5_VALUE_DISABLE << PORTCON_PORTA_OD_A5_SHIFT) +#define PORTCON_PORTA_OD_A5_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A5_BITS_ENABLE (PORTCON_PORTA_OD_A5_VALUE_ENABLE << PORTCON_PORTA_OD_A5_SHIFT) + +#define PORTCON_PORTA_OD_A6_SHIFT 6 +#define PORTCON_PORTA_OD_A6_WIDTH 1 +#define PORTCON_PORTA_OD_A6_MASK (((1U << PORTCON_PORTA_OD_A6_WIDTH) - 1U) << PORTCON_PORTA_OD_A6_SHIFT) +#define PORTCON_PORTA_OD_A6_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A6_BITS_DISABLE (PORTCON_PORTA_OD_A6_VALUE_DISABLE << PORTCON_PORTA_OD_A6_SHIFT) +#define PORTCON_PORTA_OD_A6_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A6_BITS_ENABLE (PORTCON_PORTA_OD_A6_VALUE_ENABLE << PORTCON_PORTA_OD_A6_SHIFT) + +#define PORTCON_PORTA_OD_A7_SHIFT 7 +#define PORTCON_PORTA_OD_A7_WIDTH 1 +#define PORTCON_PORTA_OD_A7_MASK (((1U << PORTCON_PORTA_OD_A7_WIDTH) - 1U) << PORTCON_PORTA_OD_A7_SHIFT) +#define PORTCON_PORTA_OD_A7_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A7_BITS_DISABLE (PORTCON_PORTA_OD_A7_VALUE_DISABLE << PORTCON_PORTA_OD_A7_SHIFT) +#define PORTCON_PORTA_OD_A7_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A7_BITS_ENABLE (PORTCON_PORTA_OD_A7_VALUE_ENABLE << PORTCON_PORTA_OD_A7_SHIFT) + +#define PORTCON_PORTA_OD_A8_SHIFT 8 +#define PORTCON_PORTA_OD_A8_WIDTH 1 +#define PORTCON_PORTA_OD_A8_MASK (((1U << PORTCON_PORTA_OD_A8_WIDTH) - 1U) << PORTCON_PORTA_OD_A8_SHIFT) +#define PORTCON_PORTA_OD_A8_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A8_BITS_DISABLE (PORTCON_PORTA_OD_A8_VALUE_DISABLE << PORTCON_PORTA_OD_A8_SHIFT) +#define PORTCON_PORTA_OD_A8_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A8_BITS_ENABLE (PORTCON_PORTA_OD_A8_VALUE_ENABLE << PORTCON_PORTA_OD_A8_SHIFT) + +#define PORTCON_PORTA_OD_A9_SHIFT 9 +#define PORTCON_PORTA_OD_A9_WIDTH 1 +#define PORTCON_PORTA_OD_A9_MASK (((1U << PORTCON_PORTA_OD_A9_WIDTH) - 1U) << PORTCON_PORTA_OD_A9_SHIFT) +#define PORTCON_PORTA_OD_A9_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A9_BITS_DISABLE (PORTCON_PORTA_OD_A9_VALUE_DISABLE << PORTCON_PORTA_OD_A9_SHIFT) +#define PORTCON_PORTA_OD_A9_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A9_BITS_ENABLE (PORTCON_PORTA_OD_A9_VALUE_ENABLE << PORTCON_PORTA_OD_A9_SHIFT) + +#define PORTCON_PORTA_OD_A10_SHIFT 10 +#define PORTCON_PORTA_OD_A10_WIDTH 1 +#define PORTCON_PORTA_OD_A10_MASK (((1U << PORTCON_PORTA_OD_A10_WIDTH) - 1U) << PORTCON_PORTA_OD_A10_SHIFT) +#define PORTCON_PORTA_OD_A10_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A10_BITS_DISABLE (PORTCON_PORTA_OD_A10_VALUE_DISABLE << PORTCON_PORTA_OD_A10_SHIFT) +#define PORTCON_PORTA_OD_A10_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A10_BITS_ENABLE (PORTCON_PORTA_OD_A10_VALUE_ENABLE << PORTCON_PORTA_OD_A10_SHIFT) + +#define PORTCON_PORTA_OD_A11_SHIFT 11 +#define PORTCON_PORTA_OD_A11_WIDTH 1 +#define PORTCON_PORTA_OD_A11_MASK (((1U << PORTCON_PORTA_OD_A11_WIDTH) - 1U) << PORTCON_PORTA_OD_A11_SHIFT) +#define PORTCON_PORTA_OD_A11_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A11_BITS_DISABLE (PORTCON_PORTA_OD_A11_VALUE_DISABLE << PORTCON_PORTA_OD_A11_SHIFT) +#define PORTCON_PORTA_OD_A11_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A11_BITS_ENABLE (PORTCON_PORTA_OD_A11_VALUE_ENABLE << PORTCON_PORTA_OD_A11_SHIFT) + +#define PORTCON_PORTA_OD_A12_SHIFT 12 +#define PORTCON_PORTA_OD_A12_WIDTH 1 +#define PORTCON_PORTA_OD_A12_MASK (((1U << PORTCON_PORTA_OD_A12_WIDTH) - 1U) << PORTCON_PORTA_OD_A12_SHIFT) +#define PORTCON_PORTA_OD_A12_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A12_BITS_DISABLE (PORTCON_PORTA_OD_A12_VALUE_DISABLE << PORTCON_PORTA_OD_A12_SHIFT) +#define PORTCON_PORTA_OD_A12_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A12_BITS_ENABLE (PORTCON_PORTA_OD_A12_VALUE_ENABLE << PORTCON_PORTA_OD_A12_SHIFT) + +#define PORTCON_PORTA_OD_A13_SHIFT 13 +#define PORTCON_PORTA_OD_A13_WIDTH 1 +#define PORTCON_PORTA_OD_A13_MASK (((1U << PORTCON_PORTA_OD_A13_WIDTH) - 1U) << PORTCON_PORTA_OD_A13_SHIFT) +#define PORTCON_PORTA_OD_A13_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A13_BITS_DISABLE (PORTCON_PORTA_OD_A13_VALUE_DISABLE << PORTCON_PORTA_OD_A13_SHIFT) +#define PORTCON_PORTA_OD_A13_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A13_BITS_ENABLE (PORTCON_PORTA_OD_A13_VALUE_ENABLE << PORTCON_PORTA_OD_A13_SHIFT) + +#define PORTCON_PORTA_OD_A14_SHIFT 14 +#define PORTCON_PORTA_OD_A14_WIDTH 1 +#define PORTCON_PORTA_OD_A14_MASK (((1U << PORTCON_PORTA_OD_A14_WIDTH) - 1U) << PORTCON_PORTA_OD_A14_SHIFT) +#define PORTCON_PORTA_OD_A14_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A14_BITS_DISABLE (PORTCON_PORTA_OD_A14_VALUE_DISABLE << PORTCON_PORTA_OD_A14_SHIFT) +#define PORTCON_PORTA_OD_A14_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A14_BITS_ENABLE (PORTCON_PORTA_OD_A14_VALUE_ENABLE << PORTCON_PORTA_OD_A14_SHIFT) + +#define PORTCON_PORTA_OD_A15_SHIFT 15 +#define PORTCON_PORTA_OD_A15_WIDTH 1 +#define PORTCON_PORTA_OD_A15_MASK (((1U << PORTCON_PORTA_OD_A15_WIDTH) - 1U) << PORTCON_PORTA_OD_A15_SHIFT) +#define PORTCON_PORTA_OD_A15_VALUE_DISABLE 0U +#define PORTCON_PORTA_OD_A15_BITS_DISABLE (PORTCON_PORTA_OD_A15_VALUE_DISABLE << PORTCON_PORTA_OD_A15_SHIFT) +#define PORTCON_PORTA_OD_A15_VALUE_ENABLE 1U +#define PORTCON_PORTA_OD_A15_BITS_ENABLE (PORTCON_PORTA_OD_A15_VALUE_ENABLE << PORTCON_PORTA_OD_A15_SHIFT) + +#define PORTCON_PORTB_OD_ADDR (PORTCON_BASE_ADDR + 0x0404U) +#define PORTCON_PORTB_OD (*(volatile uint32_t *)PORTCON_PORTB_OD_ADDR) +#define PORTCON_PORTB_OD_B0_SHIFT 0 +#define PORTCON_PORTB_OD_B0_WIDTH 1 +#define PORTCON_PORTB_OD_B0_MASK (((1U << PORTCON_PORTB_OD_B0_WIDTH) - 1U) << PORTCON_PORTB_OD_B0_SHIFT) +#define PORTCON_PORTB_OD_B0_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B0_BITS_DISABLE (PORTCON_PORTB_OD_B0_VALUE_DISABLE << PORTCON_PORTB_OD_B0_SHIFT) +#define PORTCON_PORTB_OD_B0_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B0_BITS_ENABLE (PORTCON_PORTB_OD_B0_VALUE_ENABLE << PORTCON_PORTB_OD_B0_SHIFT) + +#define PORTCON_PORTB_OD_B1_SHIFT 1 +#define PORTCON_PORTB_OD_B1_WIDTH 1 +#define PORTCON_PORTB_OD_B1_MASK (((1U << PORTCON_PORTB_OD_B1_WIDTH) - 1U) << PORTCON_PORTB_OD_B1_SHIFT) +#define PORTCON_PORTB_OD_B1_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B1_BITS_DISABLE (PORTCON_PORTB_OD_B1_VALUE_DISABLE << PORTCON_PORTB_OD_B1_SHIFT) +#define PORTCON_PORTB_OD_B1_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B1_BITS_ENABLE (PORTCON_PORTB_OD_B1_VALUE_ENABLE << PORTCON_PORTB_OD_B1_SHIFT) + +#define PORTCON_PORTB_OD_B2_SHIFT 2 +#define PORTCON_PORTB_OD_B2_WIDTH 1 +#define PORTCON_PORTB_OD_B2_MASK (((1U << PORTCON_PORTB_OD_B2_WIDTH) - 1U) << PORTCON_PORTB_OD_B2_SHIFT) +#define PORTCON_PORTB_OD_B2_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B2_BITS_DISABLE (PORTCON_PORTB_OD_B2_VALUE_DISABLE << PORTCON_PORTB_OD_B2_SHIFT) +#define PORTCON_PORTB_OD_B2_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B2_BITS_ENABLE (PORTCON_PORTB_OD_B2_VALUE_ENABLE << PORTCON_PORTB_OD_B2_SHIFT) + +#define PORTCON_PORTB_OD_B3_SHIFT 3 +#define PORTCON_PORTB_OD_B3_WIDTH 1 +#define PORTCON_PORTB_OD_B3_MASK (((1U << PORTCON_PORTB_OD_B3_WIDTH) - 1U) << PORTCON_PORTB_OD_B3_SHIFT) +#define PORTCON_PORTB_OD_B3_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B3_BITS_DISABLE (PORTCON_PORTB_OD_B3_VALUE_DISABLE << PORTCON_PORTB_OD_B3_SHIFT) +#define PORTCON_PORTB_OD_B3_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B3_BITS_ENABLE (PORTCON_PORTB_OD_B3_VALUE_ENABLE << PORTCON_PORTB_OD_B3_SHIFT) + +#define PORTCON_PORTB_OD_B4_SHIFT 4 +#define PORTCON_PORTB_OD_B4_WIDTH 1 +#define PORTCON_PORTB_OD_B4_MASK (((1U << PORTCON_PORTB_OD_B4_WIDTH) - 1U) << PORTCON_PORTB_OD_B4_SHIFT) +#define PORTCON_PORTB_OD_B4_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B4_BITS_DISABLE (PORTCON_PORTB_OD_B4_VALUE_DISABLE << PORTCON_PORTB_OD_B4_SHIFT) +#define PORTCON_PORTB_OD_B4_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B4_BITS_ENABLE (PORTCON_PORTB_OD_B4_VALUE_ENABLE << PORTCON_PORTB_OD_B4_SHIFT) + +#define PORTCON_PORTB_OD_B5_SHIFT 5 +#define PORTCON_PORTB_OD_B5_WIDTH 1 +#define PORTCON_PORTB_OD_B5_MASK (((1U << PORTCON_PORTB_OD_B5_WIDTH) - 1U) << PORTCON_PORTB_OD_B5_SHIFT) +#define PORTCON_PORTB_OD_B5_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B5_BITS_DISABLE (PORTCON_PORTB_OD_B5_VALUE_DISABLE << PORTCON_PORTB_OD_B5_SHIFT) +#define PORTCON_PORTB_OD_B5_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B5_BITS_ENABLE (PORTCON_PORTB_OD_B5_VALUE_ENABLE << PORTCON_PORTB_OD_B5_SHIFT) + +#define PORTCON_PORTB_OD_B6_SHIFT 6 +#define PORTCON_PORTB_OD_B6_WIDTH 1 +#define PORTCON_PORTB_OD_B6_MASK (((1U << PORTCON_PORTB_OD_B6_WIDTH) - 1U) << PORTCON_PORTB_OD_B6_SHIFT) +#define PORTCON_PORTB_OD_B6_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B6_BITS_DISABLE (PORTCON_PORTB_OD_B6_VALUE_DISABLE << PORTCON_PORTB_OD_B6_SHIFT) +#define PORTCON_PORTB_OD_B6_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B6_BITS_ENABLE (PORTCON_PORTB_OD_B6_VALUE_ENABLE << PORTCON_PORTB_OD_B6_SHIFT) + +#define PORTCON_PORTB_OD_B7_SHIFT 7 +#define PORTCON_PORTB_OD_B7_WIDTH 1 +#define PORTCON_PORTB_OD_B7_MASK (((1U << PORTCON_PORTB_OD_B7_WIDTH) - 1U) << PORTCON_PORTB_OD_B7_SHIFT) +#define PORTCON_PORTB_OD_B7_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B7_BITS_DISABLE (PORTCON_PORTB_OD_B7_VALUE_DISABLE << PORTCON_PORTB_OD_B7_SHIFT) +#define PORTCON_PORTB_OD_B7_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B7_BITS_ENABLE (PORTCON_PORTB_OD_B7_VALUE_ENABLE << PORTCON_PORTB_OD_B7_SHIFT) + +#define PORTCON_PORTB_OD_B8_SHIFT 8 +#define PORTCON_PORTB_OD_B8_WIDTH 1 +#define PORTCON_PORTB_OD_B8_MASK (((1U << PORTCON_PORTB_OD_B8_WIDTH) - 1U) << PORTCON_PORTB_OD_B8_SHIFT) +#define PORTCON_PORTB_OD_B8_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B8_BITS_DISABLE (PORTCON_PORTB_OD_B8_VALUE_DISABLE << PORTCON_PORTB_OD_B8_SHIFT) +#define PORTCON_PORTB_OD_B8_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B8_BITS_ENABLE (PORTCON_PORTB_OD_B8_VALUE_ENABLE << PORTCON_PORTB_OD_B8_SHIFT) + +#define PORTCON_PORTB_OD_B9_SHIFT 9 +#define PORTCON_PORTB_OD_B9_WIDTH 1 +#define PORTCON_PORTB_OD_B9_MASK (((1U << PORTCON_PORTB_OD_B9_WIDTH) - 1U) << PORTCON_PORTB_OD_B9_SHIFT) +#define PORTCON_PORTB_OD_B9_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B9_BITS_DISABLE (PORTCON_PORTB_OD_B9_VALUE_DISABLE << PORTCON_PORTB_OD_B9_SHIFT) +#define PORTCON_PORTB_OD_B9_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B9_BITS_ENABLE (PORTCON_PORTB_OD_B9_VALUE_ENABLE << PORTCON_PORTB_OD_B9_SHIFT) + +#define PORTCON_PORTB_OD_B10_SHIFT 10 +#define PORTCON_PORTB_OD_B10_WIDTH 1 +#define PORTCON_PORTB_OD_B10_MASK (((1U << PORTCON_PORTB_OD_B10_WIDTH) - 1U) << PORTCON_PORTB_OD_B10_SHIFT) +#define PORTCON_PORTB_OD_B10_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B10_BITS_DISABLE (PORTCON_PORTB_OD_B10_VALUE_DISABLE << PORTCON_PORTB_OD_B10_SHIFT) +#define PORTCON_PORTB_OD_B10_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B10_BITS_ENABLE (PORTCON_PORTB_OD_B10_VALUE_ENABLE << PORTCON_PORTB_OD_B10_SHIFT) + +#define PORTCON_PORTB_OD_B11_SHIFT 11 +#define PORTCON_PORTB_OD_B11_WIDTH 1 +#define PORTCON_PORTB_OD_B11_MASK (((1U << PORTCON_PORTB_OD_B11_WIDTH) - 1U) << PORTCON_PORTB_OD_B11_SHIFT) +#define PORTCON_PORTB_OD_B11_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B11_BITS_DISABLE (PORTCON_PORTB_OD_B11_VALUE_DISABLE << PORTCON_PORTB_OD_B11_SHIFT) +#define PORTCON_PORTB_OD_B11_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B11_BITS_ENABLE (PORTCON_PORTB_OD_B11_VALUE_ENABLE << PORTCON_PORTB_OD_B11_SHIFT) + +#define PORTCON_PORTB_OD_B12_SHIFT 12 +#define PORTCON_PORTB_OD_B12_WIDTH 1 +#define PORTCON_PORTB_OD_B12_MASK (((1U << PORTCON_PORTB_OD_B12_WIDTH) - 1U) << PORTCON_PORTB_OD_B12_SHIFT) +#define PORTCON_PORTB_OD_B12_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B12_BITS_DISABLE (PORTCON_PORTB_OD_B12_VALUE_DISABLE << PORTCON_PORTB_OD_B12_SHIFT) +#define PORTCON_PORTB_OD_B12_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B12_BITS_ENABLE (PORTCON_PORTB_OD_B12_VALUE_ENABLE << PORTCON_PORTB_OD_B12_SHIFT) + +#define PORTCON_PORTB_OD_B13_SHIFT 13 +#define PORTCON_PORTB_OD_B13_WIDTH 1 +#define PORTCON_PORTB_OD_B13_MASK (((1U << PORTCON_PORTB_OD_B13_WIDTH) - 1U) << PORTCON_PORTB_OD_B13_SHIFT) +#define PORTCON_PORTB_OD_B13_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B13_BITS_DISABLE (PORTCON_PORTB_OD_B13_VALUE_DISABLE << PORTCON_PORTB_OD_B13_SHIFT) +#define PORTCON_PORTB_OD_B13_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B13_BITS_ENABLE (PORTCON_PORTB_OD_B13_VALUE_ENABLE << PORTCON_PORTB_OD_B13_SHIFT) + +#define PORTCON_PORTB_OD_B14_SHIFT 14 +#define PORTCON_PORTB_OD_B14_WIDTH 1 +#define PORTCON_PORTB_OD_B14_MASK (((1U << PORTCON_PORTB_OD_B14_WIDTH) - 1U) << PORTCON_PORTB_OD_B14_SHIFT) +#define PORTCON_PORTB_OD_B14_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B14_BITS_DISABLE (PORTCON_PORTB_OD_B14_VALUE_DISABLE << PORTCON_PORTB_OD_B14_SHIFT) +#define PORTCON_PORTB_OD_B14_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B14_BITS_ENABLE (PORTCON_PORTB_OD_B14_VALUE_ENABLE << PORTCON_PORTB_OD_B14_SHIFT) + +#define PORTCON_PORTB_OD_B15_SHIFT 15 +#define PORTCON_PORTB_OD_B15_WIDTH 1 +#define PORTCON_PORTB_OD_B15_MASK (((1U << PORTCON_PORTB_OD_B15_WIDTH) - 1U) << PORTCON_PORTB_OD_B15_SHIFT) +#define PORTCON_PORTB_OD_B15_VALUE_DISABLE 0U +#define PORTCON_PORTB_OD_B15_BITS_DISABLE (PORTCON_PORTB_OD_B15_VALUE_DISABLE << PORTCON_PORTB_OD_B15_SHIFT) +#define PORTCON_PORTB_OD_B15_VALUE_ENABLE 1U +#define PORTCON_PORTB_OD_B15_BITS_ENABLE (PORTCON_PORTB_OD_B15_VALUE_ENABLE << PORTCON_PORTB_OD_B15_SHIFT) + +#define PORTCON_PORTC_OD_ADDR (PORTCON_BASE_ADDR + 0x0408U) +#define PORTCON_PORTC_OD (*(volatile uint32_t *)PORTCON_PORTC_OD_ADDR) +#define PORTCON_PORTC_OD_C0_SHIFT 0 +#define PORTCON_PORTC_OD_C0_WIDTH 1 +#define PORTCON_PORTC_OD_C0_MASK (((1U << PORTCON_PORTC_OD_C0_WIDTH) - 1U) << PORTCON_PORTC_OD_C0_SHIFT) +#define PORTCON_PORTC_OD_C0_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C0_BITS_DISABLE (PORTCON_PORTC_OD_C0_VALUE_DISABLE << PORTCON_PORTC_OD_C0_SHIFT) +#define PORTCON_PORTC_OD_C0_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C0_BITS_ENABLE (PORTCON_PORTC_OD_C0_VALUE_ENABLE << PORTCON_PORTC_OD_C0_SHIFT) + +#define PORTCON_PORTC_OD_C1_SHIFT 1 +#define PORTCON_PORTC_OD_C1_WIDTH 1 +#define PORTCON_PORTC_OD_C1_MASK (((1U << PORTCON_PORTC_OD_C1_WIDTH) - 1U) << PORTCON_PORTC_OD_C1_SHIFT) +#define PORTCON_PORTC_OD_C1_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C1_BITS_DISABLE (PORTCON_PORTC_OD_C1_VALUE_DISABLE << PORTCON_PORTC_OD_C1_SHIFT) +#define PORTCON_PORTC_OD_C1_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C1_BITS_ENABLE (PORTCON_PORTC_OD_C1_VALUE_ENABLE << PORTCON_PORTC_OD_C1_SHIFT) + +#define PORTCON_PORTC_OD_C2_SHIFT 2 +#define PORTCON_PORTC_OD_C2_WIDTH 1 +#define PORTCON_PORTC_OD_C2_MASK (((1U << PORTCON_PORTC_OD_C2_WIDTH) - 1U) << PORTCON_PORTC_OD_C2_SHIFT) +#define PORTCON_PORTC_OD_C2_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C2_BITS_DISABLE (PORTCON_PORTC_OD_C2_VALUE_DISABLE << PORTCON_PORTC_OD_C2_SHIFT) +#define PORTCON_PORTC_OD_C2_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C2_BITS_ENABLE (PORTCON_PORTC_OD_C2_VALUE_ENABLE << PORTCON_PORTC_OD_C2_SHIFT) + +#define PORTCON_PORTC_OD_C3_SHIFT 3 +#define PORTCON_PORTC_OD_C3_WIDTH 1 +#define PORTCON_PORTC_OD_C3_MASK (((1U << PORTCON_PORTC_OD_C3_WIDTH) - 1U) << PORTCON_PORTC_OD_C3_SHIFT) +#define PORTCON_PORTC_OD_C3_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C3_BITS_DISABLE (PORTCON_PORTC_OD_C3_VALUE_DISABLE << PORTCON_PORTC_OD_C3_SHIFT) +#define PORTCON_PORTC_OD_C3_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C3_BITS_ENABLE (PORTCON_PORTC_OD_C3_VALUE_ENABLE << PORTCON_PORTC_OD_C3_SHIFT) + +#define PORTCON_PORTC_OD_C4_SHIFT 4 +#define PORTCON_PORTC_OD_C4_WIDTH 1 +#define PORTCON_PORTC_OD_C4_MASK (((1U << PORTCON_PORTC_OD_C4_WIDTH) - 1U) << PORTCON_PORTC_OD_C4_SHIFT) +#define PORTCON_PORTC_OD_C4_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C4_BITS_DISABLE (PORTCON_PORTC_OD_C4_VALUE_DISABLE << PORTCON_PORTC_OD_C4_SHIFT) +#define PORTCON_PORTC_OD_C4_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C4_BITS_ENABLE (PORTCON_PORTC_OD_C4_VALUE_ENABLE << PORTCON_PORTC_OD_C4_SHIFT) + +#define PORTCON_PORTC_OD_C5_SHIFT 5 +#define PORTCON_PORTC_OD_C5_WIDTH 1 +#define PORTCON_PORTC_OD_C5_MASK (((1U << PORTCON_PORTC_OD_C5_WIDTH) - 1U) << PORTCON_PORTC_OD_C5_SHIFT) +#define PORTCON_PORTC_OD_C5_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C5_BITS_DISABLE (PORTCON_PORTC_OD_C5_VALUE_DISABLE << PORTCON_PORTC_OD_C5_SHIFT) +#define PORTCON_PORTC_OD_C5_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C5_BITS_ENABLE (PORTCON_PORTC_OD_C5_VALUE_ENABLE << PORTCON_PORTC_OD_C5_SHIFT) + +#define PORTCON_PORTC_OD_C6_SHIFT 6 +#define PORTCON_PORTC_OD_C6_WIDTH 1 +#define PORTCON_PORTC_OD_C6_MASK (((1U << PORTCON_PORTC_OD_C6_WIDTH) - 1U) << PORTCON_PORTC_OD_C6_SHIFT) +#define PORTCON_PORTC_OD_C6_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C6_BITS_DISABLE (PORTCON_PORTC_OD_C6_VALUE_DISABLE << PORTCON_PORTC_OD_C6_SHIFT) +#define PORTCON_PORTC_OD_C6_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C6_BITS_ENABLE (PORTCON_PORTC_OD_C6_VALUE_ENABLE << PORTCON_PORTC_OD_C6_SHIFT) + +#define PORTCON_PORTC_OD_C7_SHIFT 7 +#define PORTCON_PORTC_OD_C7_WIDTH 1 +#define PORTCON_PORTC_OD_C7_MASK (((1U << PORTCON_PORTC_OD_C7_WIDTH) - 1U) << PORTCON_PORTC_OD_C7_SHIFT) +#define PORTCON_PORTC_OD_C7_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C7_BITS_DISABLE (PORTCON_PORTC_OD_C7_VALUE_DISABLE << PORTCON_PORTC_OD_C7_SHIFT) +#define PORTCON_PORTC_OD_C7_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C7_BITS_ENABLE (PORTCON_PORTC_OD_C7_VALUE_ENABLE << PORTCON_PORTC_OD_C7_SHIFT) + +#define PORTCON_PORTC_OD_C8_SHIFT 8 +#define PORTCON_PORTC_OD_C8_WIDTH 1 +#define PORTCON_PORTC_OD_C8_MASK (((1U << PORTCON_PORTC_OD_C8_WIDTH) - 1U) << PORTCON_PORTC_OD_C8_SHIFT) +#define PORTCON_PORTC_OD_C8_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C8_BITS_DISABLE (PORTCON_PORTC_OD_C8_VALUE_DISABLE << PORTCON_PORTC_OD_C8_SHIFT) +#define PORTCON_PORTC_OD_C8_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C8_BITS_ENABLE (PORTCON_PORTC_OD_C8_VALUE_ENABLE << PORTCON_PORTC_OD_C8_SHIFT) + +#define PORTCON_PORTC_OD_C9_SHIFT 9 +#define PORTCON_PORTC_OD_C9_WIDTH 1 +#define PORTCON_PORTC_OD_C9_MASK (((1U << PORTCON_PORTC_OD_C9_WIDTH) - 1U) << PORTCON_PORTC_OD_C9_SHIFT) +#define PORTCON_PORTC_OD_C9_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C9_BITS_DISABLE (PORTCON_PORTC_OD_C9_VALUE_DISABLE << PORTCON_PORTC_OD_C9_SHIFT) +#define PORTCON_PORTC_OD_C9_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C9_BITS_ENABLE (PORTCON_PORTC_OD_C9_VALUE_ENABLE << PORTCON_PORTC_OD_C9_SHIFT) + +#define PORTCON_PORTC_OD_C10_SHIFT 10 +#define PORTCON_PORTC_OD_C10_WIDTH 1 +#define PORTCON_PORTC_OD_C10_MASK (((1U << PORTCON_PORTC_OD_C10_WIDTH) - 1U) << PORTCON_PORTC_OD_C10_SHIFT) +#define PORTCON_PORTC_OD_C10_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C10_BITS_DISABLE (PORTCON_PORTC_OD_C10_VALUE_DISABLE << PORTCON_PORTC_OD_C10_SHIFT) +#define PORTCON_PORTC_OD_C10_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C10_BITS_ENABLE (PORTCON_PORTC_OD_C10_VALUE_ENABLE << PORTCON_PORTC_OD_C10_SHIFT) + +#define PORTCON_PORTC_OD_C11_SHIFT 11 +#define PORTCON_PORTC_OD_C11_WIDTH 1 +#define PORTCON_PORTC_OD_C11_MASK (((1U << PORTCON_PORTC_OD_C11_WIDTH) - 1U) << PORTCON_PORTC_OD_C11_SHIFT) +#define PORTCON_PORTC_OD_C11_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C11_BITS_DISABLE (PORTCON_PORTC_OD_C11_VALUE_DISABLE << PORTCON_PORTC_OD_C11_SHIFT) +#define PORTCON_PORTC_OD_C11_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C11_BITS_ENABLE (PORTCON_PORTC_OD_C11_VALUE_ENABLE << PORTCON_PORTC_OD_C11_SHIFT) + +#define PORTCON_PORTC_OD_C12_SHIFT 12 +#define PORTCON_PORTC_OD_C12_WIDTH 1 +#define PORTCON_PORTC_OD_C12_MASK (((1U << PORTCON_PORTC_OD_C12_WIDTH) - 1U) << PORTCON_PORTC_OD_C12_SHIFT) +#define PORTCON_PORTC_OD_C12_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C12_BITS_DISABLE (PORTCON_PORTC_OD_C12_VALUE_DISABLE << PORTCON_PORTC_OD_C12_SHIFT) +#define PORTCON_PORTC_OD_C12_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C12_BITS_ENABLE (PORTCON_PORTC_OD_C12_VALUE_ENABLE << PORTCON_PORTC_OD_C12_SHIFT) + +#define PORTCON_PORTC_OD_C13_SHIFT 13 +#define PORTCON_PORTC_OD_C13_WIDTH 1 +#define PORTCON_PORTC_OD_C13_MASK (((1U << PORTCON_PORTC_OD_C13_WIDTH) - 1U) << PORTCON_PORTC_OD_C13_SHIFT) +#define PORTCON_PORTC_OD_C13_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C13_BITS_DISABLE (PORTCON_PORTC_OD_C13_VALUE_DISABLE << PORTCON_PORTC_OD_C13_SHIFT) +#define PORTCON_PORTC_OD_C13_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C13_BITS_ENABLE (PORTCON_PORTC_OD_C13_VALUE_ENABLE << PORTCON_PORTC_OD_C13_SHIFT) + +#define PORTCON_PORTC_OD_C14_SHIFT 14 +#define PORTCON_PORTC_OD_C14_WIDTH 1 +#define PORTCON_PORTC_OD_C14_MASK (((1U << PORTCON_PORTC_OD_C14_WIDTH) - 1U) << PORTCON_PORTC_OD_C14_SHIFT) +#define PORTCON_PORTC_OD_C14_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C14_BITS_DISABLE (PORTCON_PORTC_OD_C14_VALUE_DISABLE << PORTCON_PORTC_OD_C14_SHIFT) +#define PORTCON_PORTC_OD_C14_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C14_BITS_ENABLE (PORTCON_PORTC_OD_C14_VALUE_ENABLE << PORTCON_PORTC_OD_C14_SHIFT) + +#define PORTCON_PORTC_OD_C15_SHIFT 15 +#define PORTCON_PORTC_OD_C15_WIDTH 1 +#define PORTCON_PORTC_OD_C15_MASK (((1U << PORTCON_PORTC_OD_C15_WIDTH) - 1U) << PORTCON_PORTC_OD_C15_SHIFT) +#define PORTCON_PORTC_OD_C15_VALUE_DISABLE 0U +#define PORTCON_PORTC_OD_C15_BITS_DISABLE (PORTCON_PORTC_OD_C15_VALUE_DISABLE << PORTCON_PORTC_OD_C15_SHIFT) +#define PORTCON_PORTC_OD_C15_VALUE_ENABLE 1U +#define PORTCON_PORTC_OD_C15_BITS_ENABLE (PORTCON_PORTC_OD_C15_VALUE_ENABLE << PORTCON_PORTC_OD_C15_SHIFT) #endif diff --git a/bsp/dp32g030/spi.h b/bsp/dp32g030/spi.h index e468a11..a8e744f 100644 --- a/bsp/dp32g030/spi.h +++ b/bsp/dp32g030/spi.h @@ -22,14 +22,14 @@ #endif /* -------- SPI0 -------- */ -#define SPI0_BASE_ADDR 0x400B8000U -#define SPI0_BASE_SIZE 0x00000800U -#define SPI0 ((volatile SPI_Port_t *)SPI0_BASE_ADDR) +#define SPI0_BASE_ADDR 0x400B8000U +#define SPI0_BASE_SIZE 0x00000800U +#define SPI0 ((volatile SPI_Port_t *)SPI0_BASE_ADDR) /* -------- SPI1 -------- */ -#define SPI1_BASE_ADDR 0x400B8800U -#define SPI1_BASE_SIZE 0x00000800U -#define SPI1 ((volatile SPI_Port_t *)SPI1_BASE_ADDR) +#define SPI1_BASE_ADDR 0x400B8800U +#define SPI1_BASE_SIZE 0x00000800U +#define SPI1 ((volatile SPI_Port_t *)SPI1_BASE_ADDR) /* -------- SPI -------- */ @@ -43,147 +43,197 @@ typedef struct { uint32_t FIFOST; } SPI_Port_t; -#define SPI_CR_SPR_SHIFT 0 -#define SPI_CR_SPR_WIDTH 3 -#define SPI_CR_SPR_MASK (((1U << SPI_CR_SPR_WIDTH) - 1U) << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_4 (0U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_8 (1U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_16 (2U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_32 (3U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_64 (4U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_128 (5U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_256 (6U << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_FPCLK_DIV_512 (7U << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_SHIFT 0 +#define SPI_CR_SPR_WIDTH 3 +#define SPI_CR_SPR_MASK (((1U << SPI_CR_SPR_WIDTH) - 1U) << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_4 0U +#define SPI_CR_SPR_BITS_FPCLK_DIV_4 (SPI_CR_SPR_VALUE_FPCLK_DIV_4 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_8 1U +#define SPI_CR_SPR_BITS_FPCLK_DIV_8 (SPI_CR_SPR_VALUE_FPCLK_DIV_8 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_16 2U +#define SPI_CR_SPR_BITS_FPCLK_DIV_16 (SPI_CR_SPR_VALUE_FPCLK_DIV_16 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_32 3U +#define SPI_CR_SPR_BITS_FPCLK_DIV_32 (SPI_CR_SPR_VALUE_FPCLK_DIV_32 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_64 4U +#define SPI_CR_SPR_BITS_FPCLK_DIV_64 (SPI_CR_SPR_VALUE_FPCLK_DIV_64 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_128 5U +#define SPI_CR_SPR_BITS_FPCLK_DIV_128 (SPI_CR_SPR_VALUE_FPCLK_DIV_128 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_256 6U +#define SPI_CR_SPR_BITS_FPCLK_DIV_256 (SPI_CR_SPR_VALUE_FPCLK_DIV_256 << SPI_CR_SPR_SHIFT) +#define SPI_CR_SPR_VALUE_FPCLK_DIV_512 7U +#define SPI_CR_SPR_BITS_FPCLK_DIV_512 (SPI_CR_SPR_VALUE_FPCLK_DIV_512 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPE_SHIFT 3 -#define SPI_CR_SPE_WIDTH 1 -#define SPI_CR_SPE_MASK (((1U << SPI_CR_SPE_WIDTH) - 1U) << SPI_CR_SPE_SHIFT) -#define SPI_CR_SPE_DISABLE (0U << SPI_CR_SPE_SHIFT) -#define SPI_CR_SPE_ENABLE (1U << SPI_CR_SPE_SHIFT) +#define SPI_CR_SPE_SHIFT 3 +#define SPI_CR_SPE_WIDTH 1 +#define SPI_CR_SPE_MASK (((1U << SPI_CR_SPE_WIDTH) - 1U) << SPI_CR_SPE_SHIFT) +#define SPI_CR_SPE_VALUE_DISABLE 0U +#define SPI_CR_SPE_BITS_DISABLE (SPI_CR_SPE_VALUE_DISABLE << SPI_CR_SPE_SHIFT) +#define SPI_CR_SPE_VALUE_ENABLE 1U +#define SPI_CR_SPE_BITS_ENABLE (SPI_CR_SPE_VALUE_ENABLE << SPI_CR_SPE_SHIFT) -#define SPI_CR_CPHA_SHIFT 4 -#define SPI_CR_CPHA_WIDTH 1 -#define SPI_CR_CPHA_MASK (((1U << SPI_CR_CPHA_WIDTH) - 1U) << SPI_CR_CPHA_SHIFT) -#define SPI_CR_CPOL_SHIFT 5 -#define SPI_CR_CPOL_WIDTH 1 -#define SPI_CR_CPOL_MASK (((1U << SPI_CR_CPOL_WIDTH) - 1U) << SPI_CR_CPOL_SHIFT) -#define SPI_CR_MSTR_SHIFT 6 -#define SPI_CR_MSTR_WIDTH 1 -#define SPI_CR_MSTR_MASK (((1U << SPI_CR_MSTR_WIDTH) - 1U) << SPI_CR_MSTR_SHIFT) -#define SPI_CR_LSB_SHIFT 7 -#define SPI_CR_LSB_WIDTH 1 -#define SPI_CR_LSB_MASK (((1U << SPI_CR_LSB_WIDTH) - 1U) << SPI_CR_LSB_SHIFT) -#define SPI_CR_CPHA_DATA_HOLD_S_SHIFT 8 -#define SPI_CR_CPHA_DATA_HOLD_S_WIDTH 4 -#define SPI_CR_CPHA_DATA_HOLD_S_MASK (((1U << SPI_CR_CPHA_DATA_HOLD_S_WIDTH) - 1U) << SPI_CR_CPHA_DATA_HOLD_S_SHIFT) -#define SPI_CR_MSR_SSN_SHIFT 12 -#define SPI_CR_MSR_SSN_WIDTH 1 -#define SPI_CR_MSR_SSN_MASK (((1U << SPI_CR_MSR_SSN_WIDTH) - 1U) << SPI_CR_MSR_SSN_SHIFT) -#define SPI_CR_MSR_SSN_DISABLE (0U << SPI_CR_MSR_SSN_SHIFT) -#define SPI_CR_MSR_SSN_ENABLE (1U << SPI_CR_MSR_SSN_SHIFT) +#define SPI_CR_CPHA_SHIFT 4 +#define SPI_CR_CPHA_WIDTH 1 +#define SPI_CR_CPHA_MASK (((1U << SPI_CR_CPHA_WIDTH) - 1U) << SPI_CR_CPHA_SHIFT) +#define SPI_CR_CPOL_SHIFT 5 +#define SPI_CR_CPOL_WIDTH 1 +#define SPI_CR_CPOL_MASK (((1U << SPI_CR_CPOL_WIDTH) - 1U) << SPI_CR_CPOL_SHIFT) +#define SPI_CR_MSTR_SHIFT 6 +#define SPI_CR_MSTR_WIDTH 1 +#define SPI_CR_MSTR_MASK (((1U << SPI_CR_MSTR_WIDTH) - 1U) << SPI_CR_MSTR_SHIFT) +#define SPI_CR_LSB_SHIFT 7 +#define SPI_CR_LSB_WIDTH 1 +#define SPI_CR_LSB_MASK (((1U << SPI_CR_LSB_WIDTH) - 1U) << SPI_CR_LSB_SHIFT) +#define SPI_CR_CPHA_DATA_HOLD_S_SHIFT 8 +#define SPI_CR_CPHA_DATA_HOLD_S_WIDTH 4 +#define SPI_CR_CPHA_DATA_HOLD_S_MASK (((1U << SPI_CR_CPHA_DATA_HOLD_S_WIDTH) - 1U) << SPI_CR_CPHA_DATA_HOLD_S_SHIFT) +#define SPI_CR_MSR_SSN_SHIFT 12 +#define SPI_CR_MSR_SSN_WIDTH 1 +#define SPI_CR_MSR_SSN_MASK (((1U << SPI_CR_MSR_SSN_WIDTH) - 1U) << SPI_CR_MSR_SSN_SHIFT) +#define SPI_CR_MSR_SSN_VALUE_DISABLE 0U +#define SPI_CR_MSR_SSN_BITS_DISABLE (SPI_CR_MSR_SSN_VALUE_DISABLE << SPI_CR_MSR_SSN_SHIFT) +#define SPI_CR_MSR_SSN_VALUE_ENABLE 1U +#define SPI_CR_MSR_SSN_BITS_ENABLE (SPI_CR_MSR_SSN_VALUE_ENABLE << SPI_CR_MSR_SSN_SHIFT) -#define SPI_CR_RXDMAEN_SHIFT 13 -#define SPI_CR_RXDMAEN_WIDTH 1 -#define SPI_CR_RXDMAEN_MASK (((1U << SPI_CR_RXDMAEN_WIDTH) - 1U) << SPI_CR_RXDMAEN_SHIFT) -#define SPI_CR_TXDMAEN_SHIFT 14 -#define SPI_CR_TXDMAEN_WIDTH 1 -#define SPI_CR_TXDMAEN_MASK (((1U << SPI_CR_TXDMAEN_WIDTH) - 1U) << SPI_CR_TXDMAEN_SHIFT) -#define SPI_CR_RF_CLR_SHIFT 15 -#define SPI_CR_RF_CLR_WIDTH 1 -#define SPI_CR_RF_CLR_MASK (((1U << SPI_CR_RF_CLR_WIDTH) - 1U) << SPI_CR_RF_CLR_SHIFT) -#define SPI_CR_TF_CLR_SHIFT 16 -#define SPI_CR_TF_CLR_WIDTH 1 -#define SPI_CR_TF_CLR_MASK (((1U << SPI_CR_TF_CLR_WIDTH) - 1U) << SPI_CR_TF_CLR_SHIFT) +#define SPI_CR_RXDMAEN_SHIFT 13 +#define SPI_CR_RXDMAEN_WIDTH 1 +#define SPI_CR_RXDMAEN_MASK (((1U << SPI_CR_RXDMAEN_WIDTH) - 1U) << SPI_CR_RXDMAEN_SHIFT) +#define SPI_CR_TXDMAEN_SHIFT 14 +#define SPI_CR_TXDMAEN_WIDTH 1 +#define SPI_CR_TXDMAEN_MASK (((1U << SPI_CR_TXDMAEN_WIDTH) - 1U) << SPI_CR_TXDMAEN_SHIFT) +#define SPI_CR_RF_CLR_SHIFT 15 +#define SPI_CR_RF_CLR_WIDTH 1 +#define SPI_CR_RF_CLR_MASK (((1U << SPI_CR_RF_CLR_WIDTH) - 1U) << SPI_CR_RF_CLR_SHIFT) +#define SPI_CR_TF_CLR_SHIFT 16 +#define SPI_CR_TF_CLR_WIDTH 1 +#define SPI_CR_TF_CLR_MASK (((1U << SPI_CR_TF_CLR_WIDTH) - 1U) << SPI_CR_TF_CLR_SHIFT) -#define SPI_IE_RXFIFO_OVF_SHIFT 0 -#define SPI_IE_RXFIFO_OVF_WIDTH 1 -#define SPI_IE_RXFIFO_OVF_MASK (((1U << SPI_IE_RXFIFO_OVF_WIDTH) - 1U) << SPI_IE_RXFIFO_OVF_SHIFT) -#define SPI_IE_RXFIFO_OVF_DISABLE (0U << SPI_IE_RXFIFO_OVF_SHIFT) -#define SPI_IE_RXFIFO_OVF_ENABLE (1U << SPI_IE_RXFIFO_OVF_SHIFT) +#define SPI_IE_RXFIFO_OVF_SHIFT 0 +#define SPI_IE_RXFIFO_OVF_WIDTH 1 +#define SPI_IE_RXFIFO_OVF_MASK (((1U << SPI_IE_RXFIFO_OVF_WIDTH) - 1U) << SPI_IE_RXFIFO_OVF_SHIFT) +#define SPI_IE_RXFIFO_OVF_VALUE_DISABLE 0U +#define SPI_IE_RXFIFO_OVF_BITS_DISABLE (SPI_IE_RXFIFO_OVF_VALUE_DISABLE << SPI_IE_RXFIFO_OVF_SHIFT) +#define SPI_IE_RXFIFO_OVF_VALUE_ENABLE 1U +#define SPI_IE_RXFIFO_OVF_BITS_ENABLE (SPI_IE_RXFIFO_OVF_VALUE_ENABLE << SPI_IE_RXFIFO_OVF_SHIFT) -#define SPI_IE_RXFIFO_FULL_SHIFT 1 -#define SPI_IE_RXFIFO_FULL_WIDTH 1 -#define SPI_IE_RXFIFO_FULL_MASK (((1U << SPI_IE_RXFIFO_FULL_WIDTH) - 1U) << SPI_IE_RXFIFO_FULL_SHIFT) -#define SPI_IE_RXFIFO_FULL_DISABLE (0U << SPI_IE_RXFIFO_FULL_SHIFT) -#define SPI_IE_RXFIFO_FULL_ENABLE (1U << SPI_IE_RXFIFO_FULL_SHIFT) +#define SPI_IE_RXFIFO_FULL_SHIFT 1 +#define SPI_IE_RXFIFO_FULL_WIDTH 1 +#define SPI_IE_RXFIFO_FULL_MASK (((1U << SPI_IE_RXFIFO_FULL_WIDTH) - 1U) << SPI_IE_RXFIFO_FULL_SHIFT) +#define SPI_IE_RXFIFO_FULL_VALUE_DISABLE 0U +#define SPI_IE_RXFIFO_FULL_BITS_DISABLE (SPI_IE_RXFIFO_FULL_VALUE_DISABLE << SPI_IE_RXFIFO_FULL_SHIFT) +#define SPI_IE_RXFIFO_FULL_VALUE_ENABLE 1U +#define SPI_IE_RXFIFO_FULL_BITS_ENABLE (SPI_IE_RXFIFO_FULL_VALUE_ENABLE << SPI_IE_RXFIFO_FULL_SHIFT) -#define SPI_IE_RXFIFO_HFULL_SHIFT 2 -#define SPI_IE_RXFIFO_HFULL_WIDTH 1 -#define SPI_IE_RXFIFO_HFULL_MASK (((1U << SPI_IE_RXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_RXFIFO_HFULL_SHIFT) -#define SPI_IE_RXFIFO_HFULL_DISABLE (0U << SPI_IE_RXFIFO_HFULL_SHIFT) -#define SPI_IE_RXFIFO_HFULL_ENABLE (1U << SPI_IE_RXFIFO_HFULL_SHIFT) +#define SPI_IE_RXFIFO_HFULL_SHIFT 2 +#define SPI_IE_RXFIFO_HFULL_WIDTH 1 +#define SPI_IE_RXFIFO_HFULL_MASK (((1U << SPI_IE_RXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_RXFIFO_HFULL_SHIFT) +#define SPI_IE_RXFIFO_HFULL_VALUE_DISABLE 0U +#define SPI_IE_RXFIFO_HFULL_BITS_DISABLE (SPI_IE_RXFIFO_HFULL_VALUE_DISABLE << SPI_IE_RXFIFO_HFULL_SHIFT) +#define SPI_IE_RXFIFO_HFULL_VALUE_ENABLE 1U +#define SPI_IE_RXFIFO_HFULL_BITS_ENABLE (SPI_IE_RXFIFO_HFULL_VALUE_ENABLE << SPI_IE_RXFIFO_HFULL_SHIFT) -#define SPI_IE_TXFIFO_EMPTY_SHIFT 3 -#define SPI_IE_TXFIFO_EMPTY_WIDTH 1 -#define SPI_IE_TXFIFO_EMPTY_MASK (((1U << SPI_IE_TXFIFO_EMPTY_WIDTH) - 1U) << SPI_IE_TXFIFO_EMPTY_SHIFT) -#define SPI_IE_TXFIFO_EMPTY_DISABLE (0U << SPI_IE_TXFIFO_EMPTY_SHIFT) -#define SPI_IE_TXFIFO_EMPTY_ENABLE (1U << SPI_IE_TXFIFO_EMPTY_SHIFT) +#define SPI_IE_TXFIFO_EMPTY_SHIFT 3 +#define SPI_IE_TXFIFO_EMPTY_WIDTH 1 +#define SPI_IE_TXFIFO_EMPTY_MASK (((1U << SPI_IE_TXFIFO_EMPTY_WIDTH) - 1U) << SPI_IE_TXFIFO_EMPTY_SHIFT) +#define SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE 0U +#define SPI_IE_TXFIFO_EMPTY_BITS_DISABLE (SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE << SPI_IE_TXFIFO_EMPTY_SHIFT) +#define SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE 1U +#define SPI_IE_TXFIFO_EMPTY_BITS_ENABLE (SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE << SPI_IE_TXFIFO_EMPTY_SHIFT) -#define SPI_IE_TXFIFO_HFULL_SHIFT 4 -#define SPI_IE_TXFIFO_HFULL_WIDTH 1 -#define SPI_IE_TXFIFO_HFULL_MASK (((1U << SPI_IE_TXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_TXFIFO_HFULL_SHIFT) -#define SPI_IE_TXFIFO_HFULL_DISABLE (0U << SPI_IE_TXFIFO_HFULL_SHIFT) -#define SPI_IE_TXFIFO_HFULL_ENABLE (1U << SPI_IE_TXFIFO_HFULL_SHIFT) +#define SPI_IE_TXFIFO_HFULL_SHIFT 4 +#define SPI_IE_TXFIFO_HFULL_WIDTH 1 +#define SPI_IE_TXFIFO_HFULL_MASK (((1U << SPI_IE_TXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_TXFIFO_HFULL_SHIFT) +#define SPI_IE_TXFIFO_HFULL_VALUE_DISABLE 0U +#define SPI_IE_TXFIFO_HFULL_BITS_DISABLE (SPI_IE_TXFIFO_HFULL_VALUE_DISABLE << SPI_IE_TXFIFO_HFULL_SHIFT) +#define SPI_IE_TXFIFO_HFULL_VALUE_ENABLE 1U +#define SPI_IE_TXFIFO_HFULL_BITS_ENABLE (SPI_IE_TXFIFO_HFULL_VALUE_ENABLE << SPI_IE_TXFIFO_HFULL_SHIFT) -#define SPI_FIFOST_RFE_SHIFT 0 -#define SPI_FIFOST_RFE_WIDTH 1 -#define SPI_FIFOST_RFE_MASK (((1U << SPI_FIFOST_RFE_WIDTH) - 1U) << SPI_FIFOST_RFE_SHIFT) -#define SPI_FIFOST_RFE_NOT_EMPTY (0U << SPI_FIFOST_RFE_SHIFT) -#define SPI_FIFOST_RFE_EMPTY (1U << SPI_FIFOST_RFE_SHIFT) +#define SPI_FIFOST_RFE_SHIFT 0 +#define SPI_FIFOST_RFE_WIDTH 1 +#define SPI_FIFOST_RFE_MASK (((1U << SPI_FIFOST_RFE_WIDTH) - 1U) << SPI_FIFOST_RFE_SHIFT) +#define SPI_FIFOST_RFE_VALUE_NOT_EMPTY 0U +#define SPI_FIFOST_RFE_BITS_NOT_EMPTY (SPI_FIFOST_RFE_VALUE_NOT_EMPTY << SPI_FIFOST_RFE_SHIFT) +#define SPI_FIFOST_RFE_VALUE_EMPTY 1U +#define SPI_FIFOST_RFE_BITS_EMPTY (SPI_FIFOST_RFE_VALUE_EMPTY << SPI_FIFOST_RFE_SHIFT) -#define SPI_FIFOST_RFF_SHIFT 1 -#define SPI_FIFOST_RFF_WIDTH 1 -#define SPI_FIFOST_RFF_MASK (((1U << SPI_FIFOST_RFF_WIDTH) - 1U) << SPI_FIFOST_RFF_SHIFT) -#define SPI_FIFOST_RFF_NOT_FULL (0U << SPI_FIFOST_RFF_SHIFT) -#define SPI_FIFOST_RFF_FULL (1U << SPI_FIFOST_RFF_SHIFT) +#define SPI_FIFOST_RFF_SHIFT 1 +#define SPI_FIFOST_RFF_WIDTH 1 +#define SPI_FIFOST_RFF_MASK (((1U << SPI_FIFOST_RFF_WIDTH) - 1U) << SPI_FIFOST_RFF_SHIFT) +#define SPI_FIFOST_RFF_VALUE_NOT_FULL 0U +#define SPI_FIFOST_RFF_BITS_NOT_FULL (SPI_FIFOST_RFF_VALUE_NOT_FULL << SPI_FIFOST_RFF_SHIFT) +#define SPI_FIFOST_RFF_VALUE_FULL 1U +#define SPI_FIFOST_RFF_BITS_FULL (SPI_FIFOST_RFF_VALUE_FULL << SPI_FIFOST_RFF_SHIFT) -#define SPI_FIFOST_RFHF_SHIFT 2 -#define SPI_FIFOST_RFHF_WIDTH 1 -#define SPI_FIFOST_RFHF_MASK (((1U << SPI_FIFOST_RFHF_WIDTH) - 1U) << SPI_FIFOST_RFHF_SHIFT) -#define SPI_FIFOST_RFHF_NOT_HALF_FULL (0U << SPI_FIFOST_RFHF_SHIFT) -#define SPI_FIFOST_RFHF_HALF_FULL (1U << SPI_FIFOST_RFHF_SHIFT) +#define SPI_FIFOST_RFHF_SHIFT 2 +#define SPI_FIFOST_RFHF_WIDTH 1 +#define SPI_FIFOST_RFHF_MASK (((1U << SPI_FIFOST_RFHF_WIDTH) - 1U) << SPI_FIFOST_RFHF_SHIFT) +#define SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL 0U +#define SPI_FIFOST_RFHF_BITS_NOT_HALF_FULL (SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_RFHF_SHIFT) +#define SPI_FIFOST_RFHF_VALUE_HALF_FULL 1U +#define SPI_FIFOST_RFHF_BITS_HALF_FULL (SPI_FIFOST_RFHF_VALUE_HALF_FULL << SPI_FIFOST_RFHF_SHIFT) -#define SPI_FIFOST_TFE_SHIFT 3 -#define SPI_FIFOST_TFE_WIDTH 1 -#define SPI_FIFOST_TFE_MASK (((1U << SPI_FIFOST_TFE_WIDTH) - 1U) << SPI_FIFOST_TFE_SHIFT) -#define SPI_FIFOST_TFE_NOT_EMPTY (0U << SPI_FIFOST_TFE_SHIFT) -#define SPI_FIFOST_TFE_EMPTY (1U << SPI_FIFOST_TFE_SHIFT) +#define SPI_FIFOST_TFE_SHIFT 3 +#define SPI_FIFOST_TFE_WIDTH 1 +#define SPI_FIFOST_TFE_MASK (((1U << SPI_FIFOST_TFE_WIDTH) - 1U) << SPI_FIFOST_TFE_SHIFT) +#define SPI_FIFOST_TFE_VALUE_NOT_EMPTY 0U +#define SPI_FIFOST_TFE_BITS_NOT_EMPTY (SPI_FIFOST_TFE_VALUE_NOT_EMPTY << SPI_FIFOST_TFE_SHIFT) +#define SPI_FIFOST_TFE_VALUE_EMPTY 1U +#define SPI_FIFOST_TFE_BITS_EMPTY (SPI_FIFOST_TFE_VALUE_EMPTY << SPI_FIFOST_TFE_SHIFT) -#define SPI_FIFOST_TFF_SHIFT 4 -#define SPI_FIFOST_TFF_WIDTH 1 -#define SPI_FIFOST_TFF_MASK (((1U << SPI_FIFOST_TFF_WIDTH) - 1U) << SPI_FIFOST_TFF_SHIFT) -#define SPI_FIFOST_TFF_NOT_FULL (0U << SPI_FIFOST_TFF_SHIFT) -#define SPI_FIFOST_TFF_FULL (1U << SPI_FIFOST_TFF_SHIFT) +#define SPI_FIFOST_TFF_SHIFT 4 +#define SPI_FIFOST_TFF_WIDTH 1 +#define SPI_FIFOST_TFF_MASK (((1U << SPI_FIFOST_TFF_WIDTH) - 1U) << SPI_FIFOST_TFF_SHIFT) +#define SPI_FIFOST_TFF_VALUE_NOT_FULL 0U +#define SPI_FIFOST_TFF_BITS_NOT_FULL (SPI_FIFOST_TFF_VALUE_NOT_FULL << SPI_FIFOST_TFF_SHIFT) +#define SPI_FIFOST_TFF_VALUE_FULL 1U +#define SPI_FIFOST_TFF_BITS_FULL (SPI_FIFOST_TFF_VALUE_FULL << SPI_FIFOST_TFF_SHIFT) -#define SPI_FIFOST_TFHF_SHIFT 5 -#define SPI_FIFOST_TFHF_WIDTH 1 -#define SPI_FIFOST_TFHF_MASK (((1U << SPI_FIFOST_TFHF_WIDTH) - 1U) << SPI_FIFOST_TFHF_SHIFT) -#define SPI_FIFOST_TFHF_NOT_HALF_FULL (0U << SPI_FIFOST_TFHF_SHIFT) -#define SPI_FIFOST_TFHF_HALF_FULL (1U << SPI_FIFOST_TFHF_SHIFT) +#define SPI_FIFOST_TFHF_SHIFT 5 +#define SPI_FIFOST_TFHF_WIDTH 1 +#define SPI_FIFOST_TFHF_MASK (((1U << SPI_FIFOST_TFHF_WIDTH) - 1U) << SPI_FIFOST_TFHF_SHIFT) +#define SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL 0U +#define SPI_FIFOST_TFHF_BITS_NOT_HALF_FULL (SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_TFHF_SHIFT) +#define SPI_FIFOST_TFHF_VALUE_HALF_FULL 1U +#define SPI_FIFOST_TFHF_BITS_HALF_FULL (SPI_FIFOST_TFHF_VALUE_HALF_FULL << SPI_FIFOST_TFHF_SHIFT) -#define SPI_FIFOST_RF_LEVEL_SHIFT 6 -#define SPI_FIFOST_RF_LEVEL_WIDTH 3 -#define SPI_FIFOST_RF_LEVEL_MASK (((1U << SPI_FIFOST_RF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_0_BYTE (0U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_1_BYTE (1U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_2_BYTE (2U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_3_BYTE (3U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_4_BYTE (4U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_5_BYTE (5U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_6_BYTE (6U << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_7_BYTE (7U << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_SHIFT 6 +#define SPI_FIFOST_RF_LEVEL_WIDTH 3 +#define SPI_FIFOST_RF_LEVEL_MASK (((1U << SPI_FIFOST_RF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE 0U +#define SPI_FIFOST_RF_LEVEL_BITS_0_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE 1U +#define SPI_FIFOST_RF_LEVEL_BITS_1_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE 2U +#define SPI_FIFOST_RF_LEVEL_BITS_2_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE 3U +#define SPI_FIFOST_RF_LEVEL_BITS_3_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE 4U +#define SPI_FIFOST_RF_LEVEL_BITS_4_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE 5U +#define SPI_FIFOST_RF_LEVEL_BITS_5_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE 6U +#define SPI_FIFOST_RF_LEVEL_BITS_6_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) +#define SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE 7U +#define SPI_FIFOST_RF_LEVEL_BITS_7_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_SHIFT 9 -#define SPI_FIFOST_TF_LEVEL_WIDTH 3 -#define SPI_FIFOST_TF_LEVEL_MASK (((1U << SPI_FIFOST_TF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_0_BYTE (0U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_1_BYTE (1U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_2_BYTE (2U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_3_BYTE (3U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_4_BYTE (4U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_5_BYTE (5U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_6_BYTE (6U << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_7_BYTE (7U << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_SHIFT 9 +#define SPI_FIFOST_TF_LEVEL_WIDTH 3 +#define SPI_FIFOST_TF_LEVEL_MASK (((1U << SPI_FIFOST_TF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE 0U +#define SPI_FIFOST_TF_LEVEL_BITS_0_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE 1U +#define SPI_FIFOST_TF_LEVEL_BITS_1_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE 2U +#define SPI_FIFOST_TF_LEVEL_BITS_2_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE 3U +#define SPI_FIFOST_TF_LEVEL_BITS_3_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE 4U +#define SPI_FIFOST_TF_LEVEL_BITS_4_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE 5U +#define SPI_FIFOST_TF_LEVEL_BITS_5_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE 6U +#define SPI_FIFOST_TF_LEVEL_BITS_6_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) +#define SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE 7U +#define SPI_FIFOST_TF_LEVEL_BITS_7_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #endif diff --git a/bsp/dp32g030/syscon.h b/bsp/dp32g030/syscon.h index 1e2c8c6..04c04f6 100644 --- a/bsp/dp32g030/syscon.h +++ b/bsp/dp32g030/syscon.h @@ -22,221 +22,286 @@ #endif /* -------- SYSCON -------- */ -#define SYSCON_BASE_ADDR 0x40000000U -#define SYSCON_BASE_SIZE 0x00000800U +#define SYSCON_BASE_ADDR 0x40000000U +#define SYSCON_BASE_SIZE 0x00000800U -#define SYSCON_CLK_SEL_ADDR (SYSCON_BASE_ADDR + 0x0000U) -#define SYSCON_CLK_SEL (*(volatile uint32_t *)SYSCON_CLK_SEL_ADDR) -#define SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT 0 -#define SYSCON_CLK_SEL_SYS_CLK_SEL_WIDTH 1 -#define SYSCON_CLK_SEL_SYS_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_SYS_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SYS_CLK_SEL_RCHF (0U << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SYS_CLK_SEL_DIV_CLK (1U << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_ADDR (SYSCON_BASE_ADDR + 0x0000U) +#define SYSCON_CLK_SEL (*(volatile uint32_t *)SYSCON_CLK_SEL_ADDR) +#define SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT 0 +#define SYSCON_CLK_SEL_SYS_CLK_SEL_WIDTH 1 +#define SYSCON_CLK_SEL_SYS_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_SYS_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SYS_CLK_SEL_VALUE_RCHF 0U +#define SYSCON_CLK_SEL_SYS_CLK_SEL_BITS_RCHF (SYSCON_CLK_SEL_SYS_CLK_SEL_VALUE_RCHF << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SYS_CLK_SEL_VALUE_DIV_CLK 1U +#define SYSCON_CLK_SEL_SYS_CLK_SEL_BITS_DIV_CLK (SYSCON_CLK_SEL_SYS_CLK_SEL_VALUE_DIV_CLK << SYSCON_CLK_SEL_SYS_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT 1 -#define SYSCON_CLK_SEL_DIV_CLK_SEL_WIDTH 3 -#define SYSCON_CLK_SEL_DIV_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_DIV_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_1 (0U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_2 (1U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_4 (2U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_8 (3U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_16 (4U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_DIV_CLK_SEL_32 (5U << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT 1 +#define SYSCON_CLK_SEL_DIV_CLK_SEL_WIDTH 3 +#define SYSCON_CLK_SEL_DIV_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_DIV_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_1 0U +#define SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_1 (SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_1 << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_2 1U +#define SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_2 (SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_2 << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_4 2U +#define SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_4 (SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_4 << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_8 3U +#define SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_8 (SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_8 << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_16 4U +#define SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_16 (SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_16 << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_32 5U +#define SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_32 (SYSCON_CLK_SEL_DIV_CLK_SEL_VALUE_32 << SYSCON_CLK_SEL_DIV_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT 4 -#define SYSCON_CLK_SEL_SRC_CLK_SEL_WIDTH 3 -#define SYSCON_CLK_SEL_SRC_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_SRC_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SRC_CLK_SEL_RCHF (0U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SRC_CLK_SEL_RCLF (1U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SRC_CLK_SEL_XTAH (2U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SRC_CLK_SEL_XTAL (3U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) -#define SYSCON_CLK_SEL_SRC_CLK_SEL_PLL (4U << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT 4 +#define SYSCON_CLK_SEL_SRC_CLK_SEL_WIDTH 3 +#define SYSCON_CLK_SEL_SRC_CLK_SEL_MASK (((1U << SYSCON_CLK_SEL_SRC_CLK_SEL_WIDTH) - 1U) << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_RCHF 0U +#define SYSCON_CLK_SEL_SRC_CLK_SEL_BITS_RCHF (SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_RCHF << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_RCLF 1U +#define SYSCON_CLK_SEL_SRC_CLK_SEL_BITS_RCLF (SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_RCLF << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_XTAH 2U +#define SYSCON_CLK_SEL_SRC_CLK_SEL_BITS_XTAH (SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_XTAH << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_XTAL 3U +#define SYSCON_CLK_SEL_SRC_CLK_SEL_BITS_XTAL (SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_XTAL << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) +#define SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_PLL 4U +#define SYSCON_CLK_SEL_SRC_CLK_SEL_BITS_PLL (SYSCON_CLK_SEL_SRC_CLK_SEL_VALUE_PLL << SYSCON_CLK_SEL_SRC_CLK_SEL_SHIFT) -#define SYSCON_DIV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0004U) -#define SYSCON_DIV_CLK_GATE (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR) -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 1 -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH 1 -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_DISABLE (0U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_ENABLE (1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) +#define SYSCON_DIV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0004U) +#define SYSCON_DIV_CLK_GATE (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR) +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 1 +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH 1 +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE 0U +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE 1U +#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_ENABLE (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) -#define SYSCON_DEV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0008U) -#define SYSCON_DEV_CLK_GATE (*(volatile uint32_t *)SYSCON_DEV_CLK_GATE_ADDR) -#define SYSCON_DEV_CLK_GATE_GPIOA_SHIFT 0 -#define SYSCON_DEV_CLK_GATE_GPIOA_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_GPIOA_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOA_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOA_DISABLE (0U << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOA_ENABLE (1U << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) +#define SYSCON_DEV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0008U) +#define SYSCON_DEV_CLK_GATE (*(volatile uint32_t *)SYSCON_DEV_CLK_GATE_ADDR) +#define SYSCON_DEV_CLK_GATE_GPIOA_SHIFT 0 +#define SYSCON_DEV_CLK_GATE_GPIOA_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_GPIOA_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOA_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_GPIOA_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_GPIOA_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOB_SHIFT 1 -#define SYSCON_DEV_CLK_GATE_GPIOB_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_GPIOB_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOB_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOB_DISABLE (0U << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOB_ENABLE (1U << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOB_SHIFT 1 +#define SYSCON_DEV_CLK_GATE_GPIOB_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_GPIOB_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOB_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_GPIOB_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_GPIOB_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOC_SHIFT 2 -#define SYSCON_DEV_CLK_GATE_GPIOC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_GPIOC_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOC_DISABLE (0U << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOC_ENABLE (1U << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOC_SHIFT 2 +#define SYSCON_DEV_CLK_GATE_GPIOC_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_GPIOC_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_GPIOC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) +#define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_GPIOC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC0_SHIFT 4 -#define SYSCON_DEV_CLK_GATE_IIC0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_IIC0_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC0_DISABLE (0U << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC0_ENABLE (1U << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) +#define SYSCON_DEV_CLK_GATE_IIC0_SHIFT 4 +#define SYSCON_DEV_CLK_GATE_IIC0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_IIC0_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) +#define SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_IIC0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) +#define SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_IIC0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC1_SHIFT 5 -#define SYSCON_DEV_CLK_GATE_IIC1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_IIC1_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC1_DISABLE (0U << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC1_ENABLE (1U << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) +#define SYSCON_DEV_CLK_GATE_IIC1_SHIFT 5 +#define SYSCON_DEV_CLK_GATE_IIC1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_IIC1_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) +#define SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_IIC1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) +#define SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_IIC1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART0_SHIFT 6 -#define SYSCON_DEV_CLK_GATE_UART0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_UART0_MASK (((1U << SYSCON_DEV_CLK_GATE_UART0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART0_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART0_DISABLE (0U << SYSCON_DEV_CLK_GATE_UART0_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART0_ENABLE (1U << SYSCON_DEV_CLK_GATE_UART0_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART0_SHIFT 6 +#define SYSCON_DEV_CLK_GATE_UART0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_UART0_MASK (((1U << SYSCON_DEV_CLK_GATE_UART0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART0_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_UART0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_UART0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART1_SHIFT 7 -#define SYSCON_DEV_CLK_GATE_UART1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_UART1_MASK (((1U << SYSCON_DEV_CLK_GATE_UART1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART1_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART1_DISABLE (0U << SYSCON_DEV_CLK_GATE_UART1_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART1_ENABLE (1U << SYSCON_DEV_CLK_GATE_UART1_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART1_SHIFT 7 +#define SYSCON_DEV_CLK_GATE_UART1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_UART1_MASK (((1U << SYSCON_DEV_CLK_GATE_UART1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART1_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_UART1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_UART1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART2_SHIFT 8 -#define SYSCON_DEV_CLK_GATE_UART2_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_UART2_MASK (((1U << SYSCON_DEV_CLK_GATE_UART2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART2_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART2_DISABLE (0U << SYSCON_DEV_CLK_GATE_UART2_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART2_ENABLE (1U << SYSCON_DEV_CLK_GATE_UART2_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART2_SHIFT 8 +#define SYSCON_DEV_CLK_GATE_UART2_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_UART2_MASK (((1U << SYSCON_DEV_CLK_GATE_UART2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART2_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_UART2_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT) +#define SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_UART2_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI0_SHIFT 10 -#define SYSCON_DEV_CLK_GATE_SPI0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_SPI0_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI0_DISABLE (0U << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI0_ENABLE (1U << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) +#define SYSCON_DEV_CLK_GATE_SPI0_SHIFT 10 +#define SYSCON_DEV_CLK_GATE_SPI0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_SPI0_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) +#define SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_SPI0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) +#define SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI1_SHIFT 11 -#define SYSCON_DEV_CLK_GATE_SPI1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_SPI1_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI1_DISABLE (0U << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI1_ENABLE (1U << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) +#define SYSCON_DEV_CLK_GATE_SPI1_SHIFT 11 +#define SYSCON_DEV_CLK_GATE_SPI1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_SPI1_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) +#define SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_SPI1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) +#define SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT 12 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT 12 +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT 13 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT 13 +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT 14 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT 14 +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT 15 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT 15 +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT 16 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_DISABLE (0U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_ENABLE (1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT 16 +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT 17 -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT 17 +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT 18 -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT 18 +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT 20 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT 20 +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT 21 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_DISABLE (0U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_ENABLE (1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT 21 +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_RTC_SHIFT 22 -#define SYSCON_DEV_CLK_GATE_RTC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_RTC_MASK (((1U << SYSCON_DEV_CLK_GATE_RTC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_RTC_SHIFT) -#define SYSCON_DEV_CLK_GATE_RTC_DISABLE (0U << SYSCON_DEV_CLK_GATE_RTC_SHIFT) -#define SYSCON_DEV_CLK_GATE_RTC_ENABLE (1U << SYSCON_DEV_CLK_GATE_RTC_SHIFT) +#define SYSCON_DEV_CLK_GATE_RTC_SHIFT 22 +#define SYSCON_DEV_CLK_GATE_RTC_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_RTC_MASK (((1U << SYSCON_DEV_CLK_GATE_RTC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_RTC_SHIFT) +#define SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_RTC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT) +#define SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_RTC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT) -#define SYSCON_DEV_CLK_GATE_IWDT_SHIFT 23 -#define SYSCON_DEV_CLK_GATE_IWDT_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_IWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_IWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_IWDT_DISABLE (0U << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_IWDT_ENABLE (1U << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) +#define SYSCON_DEV_CLK_GATE_IWDT_SHIFT 23 +#define SYSCON_DEV_CLK_GATE_IWDT_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_IWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_IWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) +#define SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_IWDT_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) +#define SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_IWDT_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_WWDT_SHIFT 24 -#define SYSCON_DEV_CLK_GATE_WWDT_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_WWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_WWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_WWDT_DISABLE (0U << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_WWDT_ENABLE (1U << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) +#define SYSCON_DEV_CLK_GATE_WWDT_SHIFT 24 +#define SYSCON_DEV_CLK_GATE_WWDT_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_WWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_WWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) +#define SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_WWDT_BITS_DISABLE (SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) +#define SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_WWDT_BITS_ENABLE (SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_SARADC_SHIFT 25 -#define SYSCON_DEV_CLK_GATE_SARADC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_SARADC_MASK (((1U << SYSCON_DEV_CLK_GATE_SARADC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) -#define SYSCON_DEV_CLK_GATE_SARADC_DISABLE (0U << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) -#define SYSCON_DEV_CLK_GATE_SARADC_ENABLE (1U << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) +#define SYSCON_DEV_CLK_GATE_SARADC_SHIFT 25 +#define SYSCON_DEV_CLK_GATE_SARADC_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_SARADC_MASK (((1U << SYSCON_DEV_CLK_GATE_SARADC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) +#define SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_SARADC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) +#define SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) -#define SYSCON_DEV_CLK_GATE_CRC_SHIFT 27 -#define SYSCON_DEV_CLK_GATE_CRC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_CRC_MASK (((1U << SYSCON_DEV_CLK_GATE_CRC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_CRC_SHIFT) -#define SYSCON_DEV_CLK_GATE_CRC_DISABLE (0U << SYSCON_DEV_CLK_GATE_CRC_SHIFT) -#define SYSCON_DEV_CLK_GATE_CRC_ENABLE (1U << SYSCON_DEV_CLK_GATE_CRC_SHIFT) +#define SYSCON_DEV_CLK_GATE_CRC_SHIFT 27 +#define SYSCON_DEV_CLK_GATE_CRC_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_CRC_MASK (((1U << SYSCON_DEV_CLK_GATE_CRC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_CRC_SHIFT) +#define SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_CRC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT) +#define SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_CRC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT) -#define SYSCON_DEV_CLK_GATE_AES_SHIFT 28 -#define SYSCON_DEV_CLK_GATE_AES_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_AES_MASK (((1U << SYSCON_DEV_CLK_GATE_AES_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_AES_SHIFT) -#define SYSCON_DEV_CLK_GATE_AES_DISABLE (0U << SYSCON_DEV_CLK_GATE_AES_SHIFT) -#define SYSCON_DEV_CLK_GATE_AES_ENABLE (1U << SYSCON_DEV_CLK_GATE_AES_SHIFT) +#define SYSCON_DEV_CLK_GATE_AES_SHIFT 28 +#define SYSCON_DEV_CLK_GATE_AES_WIDTH 1 +#define SYSCON_DEV_CLK_GATE_AES_MASK (((1U << SYSCON_DEV_CLK_GATE_AES_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_AES_SHIFT) +#define SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE 0U +#define SYSCON_DEV_CLK_GATE_AES_BITS_DISABLE (SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT) +#define SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE 1U +#define SYSCON_DEV_CLK_GATE_AES_BITS_ENABLE (SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT) -#define SYSCON_RC_FREQ_DELTA_ADDR (SYSCON_BASE_ADDR + 0x0078U) -#define SYSCON_RC_FREQ_DELTA (*(volatile uint32_t *)SYSCON_RC_FREQ_DELTA_ADDR) -#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT 0 -#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH 10 -#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT) -#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT 10 -#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH 1 -#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT) -#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT 11 -#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH 20 -#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT) -#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT 31 -#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH 1 -#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT) +#define SYSCON_RC_FREQ_DELTA_ADDR (SYSCON_BASE_ADDR + 0x0078U) +#define SYSCON_RC_FREQ_DELTA (*(volatile uint32_t *)SYSCON_RC_FREQ_DELTA_ADDR) +#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT 0 +#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH 10 +#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT) +#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT 10 +#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH 1 +#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT) +#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT 11 +#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH 20 +#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT) +#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT 31 +#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH 1 +#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT) -#define SYSCON_VREF_VOLT_DELTA_ADDR (SYSCON_BASE_ADDR + 0x007CU) -#define SYSCON_VREF_VOLT_DELTA (*(volatile uint32_t *)SYSCON_VREF_VOLT_DELTA_ADDR) -#define SYSCON_CHIP_ID0_ADDR (SYSCON_BASE_ADDR + 0x0080U) -#define SYSCON_CHIP_ID0 (*(volatile uint32_t *)SYSCON_CHIP_ID0_ADDR) -#define SYSCON_CHIP_ID1_ADDR (SYSCON_BASE_ADDR + 0x0084U) -#define SYSCON_CHIP_ID1 (*(volatile uint32_t *)SYSCON_CHIP_ID1_ADDR) -#define SYSCON_CHIP_ID2_ADDR (SYSCON_BASE_ADDR + 0x0088U) -#define SYSCON_CHIP_ID2 (*(volatile uint32_t *)SYSCON_CHIP_ID2_ADDR) -#define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU) -#define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR) +#define SYSCON_VREF_VOLT_DELTA_ADDR (SYSCON_BASE_ADDR + 0x007CU) +#define SYSCON_VREF_VOLT_DELTA (*(volatile uint32_t *)SYSCON_VREF_VOLT_DELTA_ADDR) +#define SYSCON_CHIP_ID0_ADDR (SYSCON_BASE_ADDR + 0x0080U) +#define SYSCON_CHIP_ID0 (*(volatile uint32_t *)SYSCON_CHIP_ID0_ADDR) +#define SYSCON_CHIP_ID1_ADDR (SYSCON_BASE_ADDR + 0x0084U) +#define SYSCON_CHIP_ID1 (*(volatile uint32_t *)SYSCON_CHIP_ID1_ADDR) +#define SYSCON_CHIP_ID2_ADDR (SYSCON_BASE_ADDR + 0x0088U) +#define SYSCON_CHIP_ID2 (*(volatile uint32_t *)SYSCON_CHIP_ID2_ADDR) +#define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU) +#define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR) #endif diff --git a/bsp/dp32g030/uart.h b/bsp/dp32g030/uart.h index 4ca96ad..f233eea 100644 --- a/bsp/dp32g030/uart.h +++ b/bsp/dp32g030/uart.h @@ -22,19 +22,19 @@ #endif /* -------- UART0 -------- */ -#define UART0_BASE_ADDR 0x4006B000U -#define UART0_BASE_SIZE 0x00000800U -#define UART0 ((volatile UART_Port_t *)UART0_BASE_ADDR) +#define UART0_BASE_ADDR 0x4006B000U +#define UART0_BASE_SIZE 0x00000800U +#define UART0 ((volatile UART_Port_t *)UART0_BASE_ADDR) /* -------- UART1 -------- */ -#define UART1_BASE_ADDR 0x4006B800U -#define UART1_BASE_SIZE 0x00000800U -#define UART1 ((volatile UART_Port_t *)UART1_BASE_ADDR) +#define UART1_BASE_ADDR 0x4006B800U +#define UART1_BASE_SIZE 0x00000800U +#define UART1 ((volatile UART_Port_t *)UART1_BASE_ADDR) /* -------- UART2 -------- */ -#define UART2_BASE_ADDR 0x4006C000U -#define UART2_BASE_SIZE 0x00000800U -#define UART2 ((volatile UART_Port_t *)UART2_BASE_ADDR) +#define UART2_BASE_ADDR 0x4006C000U +#define UART2_BASE_SIZE 0x00000800U +#define UART2 ((volatile UART_Port_t *)UART2_BASE_ADDR) /* -------- UART -------- */ @@ -50,281 +50,389 @@ typedef struct { uint32_t RXTO; } UART_Port_t; -#define UART_CTRL_UARTEN_SHIFT 0 -#define UART_CTRL_UARTEN_WIDTH 1 -#define UART_CTRL_UARTEN_MASK (((1U << UART_CTRL_UARTEN_WIDTH) - 1U) << UART_CTRL_UARTEN_SHIFT) -#define UART_CTRL_UARTEN_DISABLE (0U << UART_CTRL_UARTEN_SHIFT) -#define UART_CTRL_UARTEN_ENABLE (1U << UART_CTRL_UARTEN_SHIFT) +#define UART_CTRL_UARTEN_SHIFT 0 +#define UART_CTRL_UARTEN_WIDTH 1 +#define UART_CTRL_UARTEN_MASK (((1U << UART_CTRL_UARTEN_WIDTH) - 1U) << UART_CTRL_UARTEN_SHIFT) +#define UART_CTRL_UARTEN_VALUE_DISABLE 0U +#define UART_CTRL_UARTEN_BITS_DISABLE (UART_CTRL_UARTEN_VALUE_DISABLE << UART_CTRL_UARTEN_SHIFT) +#define UART_CTRL_UARTEN_VALUE_ENABLE 1U +#define UART_CTRL_UARTEN_BITS_ENABLE (UART_CTRL_UARTEN_VALUE_ENABLE << UART_CTRL_UARTEN_SHIFT) -#define UART_CTRL_RXEN_SHIFT 1 -#define UART_CTRL_RXEN_WIDTH 1 -#define UART_CTRL_RXEN_MASK (((1U << UART_CTRL_RXEN_WIDTH) - 1U) << UART_CTRL_RXEN_SHIFT) -#define UART_CTRL_RXEN_DISABLE (0U << UART_CTRL_RXEN_SHIFT) -#define UART_CTRL_RXEN_ENABLE (1U << UART_CTRL_RXEN_SHIFT) +#define UART_CTRL_RXEN_SHIFT 1 +#define UART_CTRL_RXEN_WIDTH 1 +#define UART_CTRL_RXEN_MASK (((1U << UART_CTRL_RXEN_WIDTH) - 1U) << UART_CTRL_RXEN_SHIFT) +#define UART_CTRL_RXEN_VALUE_DISABLE 0U +#define UART_CTRL_RXEN_BITS_DISABLE (UART_CTRL_RXEN_VALUE_DISABLE << UART_CTRL_RXEN_SHIFT) +#define UART_CTRL_RXEN_VALUE_ENABLE 1U +#define UART_CTRL_RXEN_BITS_ENABLE (UART_CTRL_RXEN_VALUE_ENABLE << UART_CTRL_RXEN_SHIFT) -#define UART_CTRL_TXEN_SHIFT 2 -#define UART_CTRL_TXEN_WIDTH 1 -#define UART_CTRL_TXEN_MASK (((1U << UART_CTRL_TXEN_WIDTH) - 1U) << UART_CTRL_TXEN_SHIFT) -#define UART_CTRL_TXEN_DISABLE (0U << UART_CTRL_TXEN_SHIFT) -#define UART_CTRL_TXEN_ENABLE (1U << UART_CTRL_TXEN_SHIFT) +#define UART_CTRL_TXEN_SHIFT 2 +#define UART_CTRL_TXEN_WIDTH 1 +#define UART_CTRL_TXEN_MASK (((1U << UART_CTRL_TXEN_WIDTH) - 1U) << UART_CTRL_TXEN_SHIFT) +#define UART_CTRL_TXEN_VALUE_DISABLE 0U +#define UART_CTRL_TXEN_BITS_DISABLE (UART_CTRL_TXEN_VALUE_DISABLE << UART_CTRL_TXEN_SHIFT) +#define UART_CTRL_TXEN_VALUE_ENABLE 1U +#define UART_CTRL_TXEN_BITS_ENABLE (UART_CTRL_TXEN_VALUE_ENABLE << UART_CTRL_TXEN_SHIFT) -#define UART_CTRL_RXDMAEN_SHIFT 3 -#define UART_CTRL_RXDMAEN_WIDTH 1 -#define UART_CTRL_RXDMAEN_MASK (((1U << UART_CTRL_RXDMAEN_WIDTH) - 1U) << UART_CTRL_RXDMAEN_SHIFT) -#define UART_CTRL_RXDMAEN_DISABLE (0U << UART_CTRL_RXDMAEN_SHIFT) -#define UART_CTRL_RXDMAEN_ENABLE (1U << UART_CTRL_RXDMAEN_SHIFT) +#define UART_CTRL_RXDMAEN_SHIFT 3 +#define UART_CTRL_RXDMAEN_WIDTH 1 +#define UART_CTRL_RXDMAEN_MASK (((1U << UART_CTRL_RXDMAEN_WIDTH) - 1U) << UART_CTRL_RXDMAEN_SHIFT) +#define UART_CTRL_RXDMAEN_VALUE_DISABLE 0U +#define UART_CTRL_RXDMAEN_BITS_DISABLE (UART_CTRL_RXDMAEN_VALUE_DISABLE << UART_CTRL_RXDMAEN_SHIFT) +#define UART_CTRL_RXDMAEN_VALUE_ENABLE 1U +#define UART_CTRL_RXDMAEN_BITS_ENABLE (UART_CTRL_RXDMAEN_VALUE_ENABLE << UART_CTRL_RXDMAEN_SHIFT) -#define UART_CTRL_TXDMAEN_SHIFT 4 -#define UART_CTRL_TXDMAEN_WIDTH 1 -#define UART_CTRL_TXDMAEN_MASK (((1U << UART_CTRL_TXDMAEN_WIDTH) - 1U) << UART_CTRL_TXDMAEN_SHIFT) -#define UART_CTRL_TXDMAEN_DISABLE (0U << UART_CTRL_TXDMAEN_SHIFT) -#define UART_CTRL_TXDMAEN_ENABLE (1U << UART_CTRL_TXDMAEN_SHIFT) +#define UART_CTRL_TXDMAEN_SHIFT 4 +#define UART_CTRL_TXDMAEN_WIDTH 1 +#define UART_CTRL_TXDMAEN_MASK (((1U << UART_CTRL_TXDMAEN_WIDTH) - 1U) << UART_CTRL_TXDMAEN_SHIFT) +#define UART_CTRL_TXDMAEN_VALUE_DISABLE 0U +#define UART_CTRL_TXDMAEN_BITS_DISABLE (UART_CTRL_TXDMAEN_VALUE_DISABLE << UART_CTRL_TXDMAEN_SHIFT) +#define UART_CTRL_TXDMAEN_VALUE_ENABLE 1U +#define UART_CTRL_TXDMAEN_BITS_ENABLE (UART_CTRL_TXDMAEN_VALUE_ENABLE << UART_CTRL_TXDMAEN_SHIFT) -#define UART_CTRL_NINEBIT_SHIFT 5 -#define UART_CTRL_NINEBIT_WIDTH 1 -#define UART_CTRL_NINEBIT_MASK (((1U << UART_CTRL_NINEBIT_WIDTH) - 1U) << UART_CTRL_NINEBIT_SHIFT) -#define UART_CTRL_NINEBIT_DISABLE (0U << UART_CTRL_NINEBIT_SHIFT) -#define UART_CTRL_NINEBIT_ENABLE (1U << UART_CTRL_NINEBIT_SHIFT) +#define UART_CTRL_NINEBIT_SHIFT 5 +#define UART_CTRL_NINEBIT_WIDTH 1 +#define UART_CTRL_NINEBIT_MASK (((1U << UART_CTRL_NINEBIT_WIDTH) - 1U) << UART_CTRL_NINEBIT_SHIFT) +#define UART_CTRL_NINEBIT_VALUE_DISABLE 0U +#define UART_CTRL_NINEBIT_BITS_DISABLE (UART_CTRL_NINEBIT_VALUE_DISABLE << UART_CTRL_NINEBIT_SHIFT) +#define UART_CTRL_NINEBIT_VALUE_ENABLE 1U +#define UART_CTRL_NINEBIT_BITS_ENABLE (UART_CTRL_NINEBIT_VALUE_ENABLE << UART_CTRL_NINEBIT_SHIFT) -#define UART_CTRL_PAREN_SHIFT 6 -#define UART_CTRL_PAREN_WIDTH 1 -#define UART_CTRL_PAREN_MASK (((1U << UART_CTRL_PAREN_WIDTH) - 1U) << UART_CTRL_PAREN_SHIFT) -#define UART_CTRL_PAREN_DISABLE (0U << UART_CTRL_PAREN_SHIFT) -#define UART_CTRL_PAREN_ENABLE (1U << UART_CTRL_PAREN_SHIFT) +#define UART_CTRL_PAREN_SHIFT 6 +#define UART_CTRL_PAREN_WIDTH 1 +#define UART_CTRL_PAREN_MASK (((1U << UART_CTRL_PAREN_WIDTH) - 1U) << UART_CTRL_PAREN_SHIFT) +#define UART_CTRL_PAREN_VALUE_DISABLE 0U +#define UART_CTRL_PAREN_BITS_DISABLE (UART_CTRL_PAREN_VALUE_DISABLE << UART_CTRL_PAREN_SHIFT) +#define UART_CTRL_PAREN_VALUE_ENABLE 1U +#define UART_CTRL_PAREN_BITS_ENABLE (UART_CTRL_PAREN_VALUE_ENABLE << UART_CTRL_PAREN_SHIFT) -#define UART_IE_TXDONE_SHIFT 2 -#define UART_IE_TXDONE_WIDTH 1 -#define UART_IE_TXDONE_MASK (((1U << UART_IE_TXDONE_WIDTH) - 1U) << UART_IE_TXDONE_SHIFT) -#define UART_IE_TXDONE_DISABLE (0U << UART_IE_TXDONE_SHIFT) -#define UART_IE_TXDONE_ENABLE (1U << UART_IE_TXDONE_SHIFT) +#define UART_IE_TXDONE_SHIFT 2 +#define UART_IE_TXDONE_WIDTH 1 +#define UART_IE_TXDONE_MASK (((1U << UART_IE_TXDONE_WIDTH) - 1U) << UART_IE_TXDONE_SHIFT) +#define UART_IE_TXDONE_VALUE_DISABLE 0U +#define UART_IE_TXDONE_BITS_DISABLE (UART_IE_TXDONE_VALUE_DISABLE << UART_IE_TXDONE_SHIFT) +#define UART_IE_TXDONE_VALUE_ENABLE 1U +#define UART_IE_TXDONE_BITS_ENABLE (UART_IE_TXDONE_VALUE_ENABLE << UART_IE_TXDONE_SHIFT) -#define UART_IE_PARITYE_SHIFT 3 -#define UART_IE_PARITYE_WIDTH 1 -#define UART_IE_PARITYE_MASK (((1U << UART_IE_PARITYE_WIDTH) - 1U) << UART_IE_PARITYE_SHIFT) -#define UART_IE_PARITYE_DISABLE (0U << UART_IE_PARITYE_SHIFT) -#define UART_IE_PARITYE_ENABLE (1U << UART_IE_PARITYE_SHIFT) +#define UART_IE_PARITYE_SHIFT 3 +#define UART_IE_PARITYE_WIDTH 1 +#define UART_IE_PARITYE_MASK (((1U << UART_IE_PARITYE_WIDTH) - 1U) << UART_IE_PARITYE_SHIFT) +#define UART_IE_PARITYE_VALUE_DISABLE 0U +#define UART_IE_PARITYE_BITS_DISABLE (UART_IE_PARITYE_VALUE_DISABLE << UART_IE_PARITYE_SHIFT) +#define UART_IE_PARITYE_VALUE_ENABLE 1U +#define UART_IE_PARITYE_BITS_ENABLE (UART_IE_PARITYE_VALUE_ENABLE << UART_IE_PARITYE_SHIFT) -#define UART_IE_STOPE_SHIFT 4 -#define UART_IE_STOPE_WIDTH 1 -#define UART_IE_STOPE_MASK (((1U << UART_IE_STOPE_WIDTH) - 1U) << UART_IE_STOPE_SHIFT) -#define UART_IE_STOPE_DISABLE (0U << UART_IE_STOPE_SHIFT) -#define UART_IE_STOPE_ENABLE (1U << UART_IE_STOPE_SHIFT) +#define UART_IE_STOPE_SHIFT 4 +#define UART_IE_STOPE_WIDTH 1 +#define UART_IE_STOPE_MASK (((1U << UART_IE_STOPE_WIDTH) - 1U) << UART_IE_STOPE_SHIFT) +#define UART_IE_STOPE_VALUE_DISABLE 0U +#define UART_IE_STOPE_BITS_DISABLE (UART_IE_STOPE_VALUE_DISABLE << UART_IE_STOPE_SHIFT) +#define UART_IE_STOPE_VALUE_ENABLE 1U +#define UART_IE_STOPE_BITS_ENABLE (UART_IE_STOPE_VALUE_ENABLE << UART_IE_STOPE_SHIFT) -#define UART_IE_RXTO_SHIFT 5 -#define UART_IE_RXTO_WIDTH 1 -#define UART_IE_RXTO_MASK (((1U << UART_IE_RXTO_WIDTH) - 1U) << UART_IE_RXTO_SHIFT) -#define UART_IE_RXTO_DISABLE (0U << UART_IE_RXTO_SHIFT) -#define UART_IE_RXTO_ENABLE (1U << UART_IE_RXTO_SHIFT) +#define UART_IE_RXTO_SHIFT 5 +#define UART_IE_RXTO_WIDTH 1 +#define UART_IE_RXTO_MASK (((1U << UART_IE_RXTO_WIDTH) - 1U) << UART_IE_RXTO_SHIFT) +#define UART_IE_RXTO_VALUE_DISABLE 0U +#define UART_IE_RXTO_BITS_DISABLE (UART_IE_RXTO_VALUE_DISABLE << UART_IE_RXTO_SHIFT) +#define UART_IE_RXTO_VALUE_ENABLE 1U +#define UART_IE_RXTO_BITS_ENABLE (UART_IE_RXTO_VALUE_ENABLE << UART_IE_RXTO_SHIFT) -#define UART_IE_RXFIFO_SHIFT 6 -#define UART_IE_RXFIFO_WIDTH 1 -#define UART_IE_RXFIFO_MASK (((1U << UART_IE_RXFIFO_WIDTH) - 1U) << UART_IE_RXFIFO_SHIFT) -#define UART_IE_RXFIFO_DISABLE (0U << UART_IE_RXFIFO_SHIFT) -#define UART_IE_RXFIFO_ENABLE (1U << UART_IE_RXFIFO_SHIFT) +#define UART_IE_RXFIFO_SHIFT 6 +#define UART_IE_RXFIFO_WIDTH 1 +#define UART_IE_RXFIFO_MASK (((1U << UART_IE_RXFIFO_WIDTH) - 1U) << UART_IE_RXFIFO_SHIFT) +#define UART_IE_RXFIFO_VALUE_DISABLE 0U +#define UART_IE_RXFIFO_BITS_DISABLE (UART_IE_RXFIFO_VALUE_DISABLE << UART_IE_RXFIFO_SHIFT) +#define UART_IE_RXFIFO_VALUE_ENABLE 1U +#define UART_IE_RXFIFO_BITS_ENABLE (UART_IE_RXFIFO_VALUE_ENABLE << UART_IE_RXFIFO_SHIFT) -#define UART_IE_TXFIFO_SHIFT 7 -#define UART_IE_TXFIFO_WIDTH 1 -#define UART_IE_TXFIFO_MASK (((1U << UART_IE_TXFIFO_WIDTH) - 1U) << UART_IE_TXFIFO_SHIFT) -#define UART_IE_TXFIFO_DISABLE (0U << UART_IE_TXFIFO_SHIFT) -#define UART_IE_TXFIFO_ENABLE (1U << UART_IE_TXFIFO_SHIFT) +#define UART_IE_TXFIFO_SHIFT 7 +#define UART_IE_TXFIFO_WIDTH 1 +#define UART_IE_TXFIFO_MASK (((1U << UART_IE_TXFIFO_WIDTH) - 1U) << UART_IE_TXFIFO_SHIFT) +#define UART_IE_TXFIFO_VALUE_DISABLE 0U +#define UART_IE_TXFIFO_BITS_DISABLE (UART_IE_TXFIFO_VALUE_DISABLE << UART_IE_TXFIFO_SHIFT) +#define UART_IE_TXFIFO_VALUE_ENABLE 1U +#define UART_IE_TXFIFO_BITS_ENABLE (UART_IE_TXFIFO_VALUE_ENABLE << UART_IE_TXFIFO_SHIFT) -#define UART_IE_RXFIFO_OVF_SHIFT 8 -#define UART_IE_RXFIFO_OVF_WIDTH 1 -#define UART_IE_RXFIFO_OVF_MASK (((1U << UART_IE_RXFIFO_OVF_WIDTH) - 1U) << UART_IE_RXFIFO_OVF_SHIFT) -#define UART_IE_RXFIFO_OVF_DISABLE (0U << UART_IE_RXFIFO_OVF_SHIFT) -#define UART_IE_RXFIFO_OVF_ENABLE (1U << UART_IE_RXFIFO_OVF_SHIFT) +#define UART_IE_RXFIFO_OVF_SHIFT 8 +#define UART_IE_RXFIFO_OVF_WIDTH 1 +#define UART_IE_RXFIFO_OVF_MASK (((1U << UART_IE_RXFIFO_OVF_WIDTH) - 1U) << UART_IE_RXFIFO_OVF_SHIFT) +#define UART_IE_RXFIFO_OVF_VALUE_DISABLE 0U +#define UART_IE_RXFIFO_OVF_BITS_DISABLE (UART_IE_RXFIFO_OVF_VALUE_DISABLE << UART_IE_RXFIFO_OVF_SHIFT) +#define UART_IE_RXFIFO_OVF_VALUE_ENABLE 1U +#define UART_IE_RXFIFO_OVF_BITS_ENABLE (UART_IE_RXFIFO_OVF_VALUE_ENABLE << UART_IE_RXFIFO_OVF_SHIFT) -#define UART_IE_ABRD_OVF_SHIFT 9 -#define UART_IE_ABRD_OVF_WIDTH 1 -#define UART_IE_ABRD_OVF_MASK (((1U << UART_IE_ABRD_OVF_WIDTH) - 1U) << UART_IE_ABRD_OVF_SHIFT) -#define UART_IE_ABRD_OVF_DISABLE (0U << UART_IE_ABRD_OVF_SHIFT) -#define UART_IE_ABRD_OVF_ENABLE (1U << UART_IE_ABRD_OVF_SHIFT) +#define UART_IE_ABRD_OVF_SHIFT 9 +#define UART_IE_ABRD_OVF_WIDTH 1 +#define UART_IE_ABRD_OVF_MASK (((1U << UART_IE_ABRD_OVF_WIDTH) - 1U) << UART_IE_ABRD_OVF_SHIFT) +#define UART_IE_ABRD_OVF_VALUE_DISABLE 0U +#define UART_IE_ABRD_OVF_BITS_DISABLE (UART_IE_ABRD_OVF_VALUE_DISABLE << UART_IE_ABRD_OVF_SHIFT) +#define UART_IE_ABRD_OVF_VALUE_ENABLE 1U +#define UART_IE_ABRD_OVF_BITS_ENABLE (UART_IE_ABRD_OVF_VALUE_ENABLE << UART_IE_ABRD_OVF_SHIFT) -#define UART_IF_TXDONE_SHIFT 2 -#define UART_IF_TXDONE_WIDTH 1 -#define UART_IF_TXDONE_MASK (((1U << UART_IF_TXDONE_WIDTH) - 1U) << UART_IF_TXDONE_SHIFT) -#define UART_IF_TXDONE_NOT_SET (0U << UART_IF_TXDONE_SHIFT) -#define UART_IF_TXDONE_SET (1U << UART_IF_TXDONE_SHIFT) +#define UART_IF_TXDONE_SHIFT 2 +#define UART_IF_TXDONE_WIDTH 1 +#define UART_IF_TXDONE_MASK (((1U << UART_IF_TXDONE_WIDTH) - 1U) << UART_IF_TXDONE_SHIFT) +#define UART_IF_TXDONE_VALUE_NOT_SET 0U +#define UART_IF_TXDONE_BITS_NOT_SET (UART_IF_TXDONE_VALUE_NOT_SET << UART_IF_TXDONE_SHIFT) +#define UART_IF_TXDONE_VALUE_SET 1U +#define UART_IF_TXDONE_BITS_SET (UART_IF_TXDONE_VALUE_SET << UART_IF_TXDONE_SHIFT) -#define UART_IF_PARITYE_SHIFT 3 -#define UART_IF_PARITYE_WIDTH 1 -#define UART_IF_PARITYE_MASK (((1U << UART_IF_PARITYE_WIDTH) - 1U) << UART_IF_PARITYE_SHIFT) -#define UART_IF_PARITYE_NOT_SET (0U << UART_IF_PARITYE_SHIFT) -#define UART_IF_PARITYE_SET (1U << UART_IF_PARITYE_SHIFT) +#define UART_IF_PARITYE_SHIFT 3 +#define UART_IF_PARITYE_WIDTH 1 +#define UART_IF_PARITYE_MASK (((1U << UART_IF_PARITYE_WIDTH) - 1U) << UART_IF_PARITYE_SHIFT) +#define UART_IF_PARITYE_VALUE_NOT_SET 0U +#define UART_IF_PARITYE_BITS_NOT_SET (UART_IF_PARITYE_VALUE_NOT_SET << UART_IF_PARITYE_SHIFT) +#define UART_IF_PARITYE_VALUE_SET 1U +#define UART_IF_PARITYE_BITS_SET (UART_IF_PARITYE_VALUE_SET << UART_IF_PARITYE_SHIFT) -#define UART_IF_STOPE_SHIFT 4 -#define UART_IF_STOPE_WIDTH 1 -#define UART_IF_STOPE_MASK (((1U << UART_IF_STOPE_WIDTH) - 1U) << UART_IF_STOPE_SHIFT) -#define UART_IF_STOPE_NOT_SET (0U << UART_IF_STOPE_SHIFT) -#define UART_IF_STOPE_SET (1U << UART_IF_STOPE_SHIFT) +#define UART_IF_STOPE_SHIFT 4 +#define UART_IF_STOPE_WIDTH 1 +#define UART_IF_STOPE_MASK (((1U << UART_IF_STOPE_WIDTH) - 1U) << UART_IF_STOPE_SHIFT) +#define UART_IF_STOPE_VALUE_NOT_SET 0U +#define UART_IF_STOPE_BITS_NOT_SET (UART_IF_STOPE_VALUE_NOT_SET << UART_IF_STOPE_SHIFT) +#define UART_IF_STOPE_VALUE_SET 1U +#define UART_IF_STOPE_BITS_SET (UART_IF_STOPE_VALUE_SET << UART_IF_STOPE_SHIFT) -#define UART_IF_RXTO_SHIFT 5 -#define UART_IF_RXTO_WIDTH 1 -#define UART_IF_RXTO_MASK (((1U << UART_IF_RXTO_WIDTH) - 1U) << UART_IF_RXTO_SHIFT) -#define UART_IF_RXTO_NOT_SET (0U << UART_IF_RXTO_SHIFT) -#define UART_IF_RXTO_SET (1U << UART_IF_RXTO_SHIFT) +#define UART_IF_RXTO_SHIFT 5 +#define UART_IF_RXTO_WIDTH 1 +#define UART_IF_RXTO_MASK (((1U << UART_IF_RXTO_WIDTH) - 1U) << UART_IF_RXTO_SHIFT) +#define UART_IF_RXTO_VALUE_NOT_SET 0U +#define UART_IF_RXTO_BITS_NOT_SET (UART_IF_RXTO_VALUE_NOT_SET << UART_IF_RXTO_SHIFT) +#define UART_IF_RXTO_VALUE_SET 1U +#define UART_IF_RXTO_BITS_SET (UART_IF_RXTO_VALUE_SET << UART_IF_RXTO_SHIFT) -#define UART_IF_RXFIFO_SHIFT 6 -#define UART_IF_RXFIFO_WIDTH 1 -#define UART_IF_RXFIFO_MASK (((1U << UART_IF_RXFIFO_WIDTH) - 1U) << UART_IF_RXFIFO_SHIFT) -#define UART_IF_RXFIFO_NOT_SET (0U << UART_IF_RXFIFO_SHIFT) -#define UART_IF_RXFIFO_SET (1U << UART_IF_RXFIFO_SHIFT) +#define UART_IF_RXFIFO_SHIFT 6 +#define UART_IF_RXFIFO_WIDTH 1 +#define UART_IF_RXFIFO_MASK (((1U << UART_IF_RXFIFO_WIDTH) - 1U) << UART_IF_RXFIFO_SHIFT) +#define UART_IF_RXFIFO_VALUE_NOT_SET 0U +#define UART_IF_RXFIFO_BITS_NOT_SET (UART_IF_RXFIFO_VALUE_NOT_SET << UART_IF_RXFIFO_SHIFT) +#define UART_IF_RXFIFO_VALUE_SET 1U +#define UART_IF_RXFIFO_BITS_SET (UART_IF_RXFIFO_VALUE_SET << UART_IF_RXFIFO_SHIFT) -#define UART_IF_TXFIFO_SHIFT 7 -#define UART_IF_TXFIFO_WIDTH 1 -#define UART_IF_TXFIFO_MASK (((1U << UART_IF_TXFIFO_WIDTH) - 1U) << UART_IF_TXFIFO_SHIFT) -#define UART_IF_TXFIFO_NOT_SET (0U << UART_IF_TXFIFO_SHIFT) -#define UART_IF_TXFIFO_SET (1U << UART_IF_TXFIFO_SHIFT) +#define UART_IF_TXFIFO_SHIFT 7 +#define UART_IF_TXFIFO_WIDTH 1 +#define UART_IF_TXFIFO_MASK (((1U << UART_IF_TXFIFO_WIDTH) - 1U) << UART_IF_TXFIFO_SHIFT) +#define UART_IF_TXFIFO_VALUE_NOT_SET 0U +#define UART_IF_TXFIFO_BITS_NOT_SET (UART_IF_TXFIFO_VALUE_NOT_SET << UART_IF_TXFIFO_SHIFT) +#define UART_IF_TXFIFO_VALUE_SET 1U +#define UART_IF_TXFIFO_BITS_SET (UART_IF_TXFIFO_VALUE_SET << UART_IF_TXFIFO_SHIFT) -#define UART_IF_RXFIFO_OVF_SHIFT 8 -#define UART_IF_RXFIFO_OVF_WIDTH 1 -#define UART_IF_RXFIFO_OVF_MASK (((1U << UART_IF_RXFIFO_OVF_WIDTH) - 1U) << UART_IF_RXFIFO_OVF_SHIFT) -#define UART_IF_RXFIFO_OVF_NOT_SET (0U << UART_IF_RXFIFO_OVF_SHIFT) -#define UART_IF_RXFIFO_OVF_SET (1U << UART_IF_RXFIFO_OVF_SHIFT) +#define UART_IF_RXFIFO_OVF_SHIFT 8 +#define UART_IF_RXFIFO_OVF_WIDTH 1 +#define UART_IF_RXFIFO_OVF_MASK (((1U << UART_IF_RXFIFO_OVF_WIDTH) - 1U) << UART_IF_RXFIFO_OVF_SHIFT) +#define UART_IF_RXFIFO_OVF_VALUE_NOT_SET 0U +#define UART_IF_RXFIFO_OVF_BITS_NOT_SET (UART_IF_RXFIFO_OVF_VALUE_NOT_SET << UART_IF_RXFIFO_OVF_SHIFT) +#define UART_IF_RXFIFO_OVF_VALUE_SET 1U +#define UART_IF_RXFIFO_OVF_BITS_SET (UART_IF_RXFIFO_OVF_VALUE_SET << UART_IF_RXFIFO_OVF_SHIFT) -#define UART_IF_ABRD_OVF_SHIFT 9 -#define UART_IF_ABRD_OVF_WIDTH 1 -#define UART_IF_ABRD_OVF_MASK (((1U << UART_IF_ABRD_OVF_WIDTH) - 1U) << UART_IF_ABRD_OVF_SHIFT) -#define UART_IF_ABRD_OVF_NOT_SET (0U << UART_IF_ABRD_OVF_SHIFT) -#define UART_IF_ABRD_OVF_SET (1U << UART_IF_ABRD_OVF_SHIFT) +#define UART_IF_ABRD_OVF_SHIFT 9 +#define UART_IF_ABRD_OVF_WIDTH 1 +#define UART_IF_ABRD_OVF_MASK (((1U << UART_IF_ABRD_OVF_WIDTH) - 1U) << UART_IF_ABRD_OVF_SHIFT) +#define UART_IF_ABRD_OVF_VALUE_NOT_SET 0U +#define UART_IF_ABRD_OVF_BITS_NOT_SET (UART_IF_ABRD_OVF_VALUE_NOT_SET << UART_IF_ABRD_OVF_SHIFT) +#define UART_IF_ABRD_OVF_VALUE_SET 1U +#define UART_IF_ABRD_OVF_BITS_SET (UART_IF_ABRD_OVF_VALUE_SET << UART_IF_ABRD_OVF_SHIFT) -#define UART_IF_RXFIFO_EMPTY_SHIFT 10 -#define UART_IF_RXFIFO_EMPTY_WIDTH 1 -#define UART_IF_RXFIFO_EMPTY_MASK (((1U << UART_IF_RXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_RXFIFO_EMPTY_SHIFT) -#define UART_IF_RXFIFO_EMPTY_NOT_SET (0U << UART_IF_RXFIFO_EMPTY_SHIFT) -#define UART_IF_RXFIFO_EMPTY_SET (1U << UART_IF_RXFIFO_EMPTY_SHIFT) +#define UART_IF_RXFIFO_EMPTY_SHIFT 10 +#define UART_IF_RXFIFO_EMPTY_WIDTH 1 +#define UART_IF_RXFIFO_EMPTY_MASK (((1U << UART_IF_RXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_RXFIFO_EMPTY_SHIFT) +#define UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET 0U +#define UART_IF_RXFIFO_EMPTY_BITS_NOT_SET (UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_RXFIFO_EMPTY_SHIFT) +#define UART_IF_RXFIFO_EMPTY_VALUE_SET 1U +#define UART_IF_RXFIFO_EMPTY_BITS_SET (UART_IF_RXFIFO_EMPTY_VALUE_SET << UART_IF_RXFIFO_EMPTY_SHIFT) -#define UART_IF_RXFIFO_FULL_SHIFT 11 -#define UART_IF_RXFIFO_FULL_WIDTH 1 -#define UART_IF_RXFIFO_FULL_MASK (((1U << UART_IF_RXFIFO_FULL_WIDTH) - 1U) << UART_IF_RXFIFO_FULL_SHIFT) -#define UART_IF_RXFIFO_FULL_NOT_SET (0U << UART_IF_RXFIFO_FULL_SHIFT) -#define UART_IF_RXFIFO_FULL_SET (1U << UART_IF_RXFIFO_FULL_SHIFT) +#define UART_IF_RXFIFO_FULL_SHIFT 11 +#define UART_IF_RXFIFO_FULL_WIDTH 1 +#define UART_IF_RXFIFO_FULL_MASK (((1U << UART_IF_RXFIFO_FULL_WIDTH) - 1U) << UART_IF_RXFIFO_FULL_SHIFT) +#define UART_IF_RXFIFO_FULL_VALUE_NOT_SET 0U +#define UART_IF_RXFIFO_FULL_BITS_NOT_SET (UART_IF_RXFIFO_FULL_VALUE_NOT_SET << UART_IF_RXFIFO_FULL_SHIFT) +#define UART_IF_RXFIFO_FULL_VALUE_SET 1U +#define UART_IF_RXFIFO_FULL_BITS_SET (UART_IF_RXFIFO_FULL_VALUE_SET << UART_IF_RXFIFO_FULL_SHIFT) -#define UART_IF_RXFIFO_HFULL_SHIFT 12 -#define UART_IF_RXFIFO_HFULL_WIDTH 1 -#define UART_IF_RXFIFO_HFULL_MASK (((1U << UART_IF_RXFIFO_HFULL_WIDTH) - 1U) << UART_IF_RXFIFO_HFULL_SHIFT) -#define UART_IF_RXFIFO_HFULL_NOT_SET (0U << UART_IF_RXFIFO_HFULL_SHIFT) -#define UART_IF_RXFIFO_HFULL_SET (1U << UART_IF_RXFIFO_HFULL_SHIFT) +#define UART_IF_RXFIFO_HFULL_SHIFT 12 +#define UART_IF_RXFIFO_HFULL_WIDTH 1 +#define UART_IF_RXFIFO_HFULL_MASK (((1U << UART_IF_RXFIFO_HFULL_WIDTH) - 1U) << UART_IF_RXFIFO_HFULL_SHIFT) +#define UART_IF_RXFIFO_HFULL_VALUE_NOT_SET 0U +#define UART_IF_RXFIFO_HFULL_BITS_NOT_SET (UART_IF_RXFIFO_HFULL_VALUE_NOT_SET << UART_IF_RXFIFO_HFULL_SHIFT) +#define UART_IF_RXFIFO_HFULL_VALUE_SET 1U +#define UART_IF_RXFIFO_HFULL_BITS_SET (UART_IF_RXFIFO_HFULL_VALUE_SET << UART_IF_RXFIFO_HFULL_SHIFT) -#define UART_IF_TXFIFO_EMPTY_SHIFT 13 -#define UART_IF_TXFIFO_EMPTY_WIDTH 1 -#define UART_IF_TXFIFO_EMPTY_MASK (((1U << UART_IF_TXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_TXFIFO_EMPTY_SHIFT) -#define UART_IF_TXFIFO_EMPTY_NOT_SET (0U << UART_IF_TXFIFO_EMPTY_SHIFT) -#define UART_IF_TXFIFO_EMPTY_SET (1U << UART_IF_TXFIFO_EMPTY_SHIFT) +#define UART_IF_TXFIFO_EMPTY_SHIFT 13 +#define UART_IF_TXFIFO_EMPTY_WIDTH 1 +#define UART_IF_TXFIFO_EMPTY_MASK (((1U << UART_IF_TXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_TXFIFO_EMPTY_SHIFT) +#define UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET 0U +#define UART_IF_TXFIFO_EMPTY_BITS_NOT_SET (UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_TXFIFO_EMPTY_SHIFT) +#define UART_IF_TXFIFO_EMPTY_VALUE_SET 1U +#define UART_IF_TXFIFO_EMPTY_BITS_SET (UART_IF_TXFIFO_EMPTY_VALUE_SET << UART_IF_TXFIFO_EMPTY_SHIFT) -#define UART_IF_TXFIFO_FULL_SHIFT 14 -#define UART_IF_TXFIFO_FULL_WIDTH 1 -#define UART_IF_TXFIFO_FULL_MASK (((1U << UART_IF_TXFIFO_FULL_WIDTH) - 1U) << UART_IF_TXFIFO_FULL_SHIFT) -#define UART_IF_TXFIFO_FULL_NOT_SET (0U << UART_IF_TXFIFO_FULL_SHIFT) -#define UART_IF_TXFIFO_FULL_SET (1U << UART_IF_TXFIFO_FULL_SHIFT) +#define UART_IF_TXFIFO_FULL_SHIFT 14 +#define UART_IF_TXFIFO_FULL_WIDTH 1 +#define UART_IF_TXFIFO_FULL_MASK (((1U << UART_IF_TXFIFO_FULL_WIDTH) - 1U) << UART_IF_TXFIFO_FULL_SHIFT) +#define UART_IF_TXFIFO_FULL_VALUE_NOT_SET 0U +#define UART_IF_TXFIFO_FULL_BITS_NOT_SET (UART_IF_TXFIFO_FULL_VALUE_NOT_SET << UART_IF_TXFIFO_FULL_SHIFT) +#define UART_IF_TXFIFO_FULL_VALUE_SET 1U +#define UART_IF_TXFIFO_FULL_BITS_SET (UART_IF_TXFIFO_FULL_VALUE_SET << UART_IF_TXFIFO_FULL_SHIFT) -#define UART_IF_TXFIFO_HFULL_SHIFT 15 -#define UART_IF_TXFIFO_HFULL_WIDTH 1 -#define UART_IF_TXFIFO_HFULL_MASK (((1U << UART_IF_TXFIFO_HFULL_WIDTH) - 1U) << UART_IF_TXFIFO_HFULL_SHIFT) -#define UART_IF_TXFIFO_HFULL_NOT_SET (0U << UART_IF_TXFIFO_HFULL_SHIFT) -#define UART_IF_TXFIFO_HFULL_SET (1U << UART_IF_TXFIFO_HFULL_SHIFT) +#define UART_IF_TXFIFO_HFULL_SHIFT 15 +#define UART_IF_TXFIFO_HFULL_WIDTH 1 +#define UART_IF_TXFIFO_HFULL_MASK (((1U << UART_IF_TXFIFO_HFULL_WIDTH) - 1U) << UART_IF_TXFIFO_HFULL_SHIFT) +#define UART_IF_TXFIFO_HFULL_VALUE_NOT_SET 0U +#define UART_IF_TXFIFO_HFULL_BITS_NOT_SET (UART_IF_TXFIFO_HFULL_VALUE_NOT_SET << UART_IF_TXFIFO_HFULL_SHIFT) +#define UART_IF_TXFIFO_HFULL_VALUE_SET 1U +#define UART_IF_TXFIFO_HFULL_BITS_SET (UART_IF_TXFIFO_HFULL_VALUE_SET << UART_IF_TXFIFO_HFULL_SHIFT) -#define UART_IF_TXBUSY_SHIFT 16 -#define UART_IF_TXBUSY_WIDTH 1 -#define UART_IF_TXBUSY_MASK (((1U << UART_IF_TXBUSY_WIDTH) - 1U) << UART_IF_TXBUSY_SHIFT) -#define UART_IF_TXBUSY_NOT_SET (0U << UART_IF_TXBUSY_SHIFT) -#define UART_IF_TXBUSY_SET (1U << UART_IF_TXBUSY_SHIFT) +#define UART_IF_TXBUSY_SHIFT 16 +#define UART_IF_TXBUSY_WIDTH 1 +#define UART_IF_TXBUSY_MASK (((1U << UART_IF_TXBUSY_WIDTH) - 1U) << UART_IF_TXBUSY_SHIFT) +#define UART_IF_TXBUSY_VALUE_NOT_SET 0U +#define UART_IF_TXBUSY_BITS_NOT_SET (UART_IF_TXBUSY_VALUE_NOT_SET << UART_IF_TXBUSY_SHIFT) +#define UART_IF_TXBUSY_VALUE_SET 1U +#define UART_IF_TXBUSY_BITS_SET (UART_IF_TXBUSY_VALUE_SET << UART_IF_TXBUSY_SHIFT) -#define UART_IF_RF_LEVEL_SHIFT 17 -#define UART_IF_RF_LEVEL_WIDTH 3 -#define UART_IF_RF_LEVEL_MASK (((1U << UART_IF_RF_LEVEL_WIDTH) - 1U) << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_0_8_BYTE (0U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_1_BYTE (1U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_2_BYTE (2U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_3_BYTE (3U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_4_BYTE (4U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_5_BYTE (5U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_6_BYTE (6U << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_7_BYTE (7U << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_SHIFT 17 +#define UART_IF_RF_LEVEL_WIDTH 3 +#define UART_IF_RF_LEVEL_MASK (((1U << UART_IF_RF_LEVEL_WIDTH) - 1U) << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_0_8_BYTE 0U +#define UART_IF_RF_LEVEL_BITS_0_8_BYTE (UART_IF_RF_LEVEL_VALUE_0_8_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_1_BYTE 1U +#define UART_IF_RF_LEVEL_BITS_1_BYTE (UART_IF_RF_LEVEL_VALUE_1_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_2_BYTE 2U +#define UART_IF_RF_LEVEL_BITS_2_BYTE (UART_IF_RF_LEVEL_VALUE_2_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_3_BYTE 3U +#define UART_IF_RF_LEVEL_BITS_3_BYTE (UART_IF_RF_LEVEL_VALUE_3_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_4_BYTE 4U +#define UART_IF_RF_LEVEL_BITS_4_BYTE (UART_IF_RF_LEVEL_VALUE_4_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_5_BYTE 5U +#define UART_IF_RF_LEVEL_BITS_5_BYTE (UART_IF_RF_LEVEL_VALUE_5_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_6_BYTE 6U +#define UART_IF_RF_LEVEL_BITS_6_BYTE (UART_IF_RF_LEVEL_VALUE_6_BYTE << UART_IF_RF_LEVEL_SHIFT) +#define UART_IF_RF_LEVEL_VALUE_7_BYTE 7U +#define UART_IF_RF_LEVEL_BITS_7_BYTE (UART_IF_RF_LEVEL_VALUE_7_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_SHIFT 20 -#define UART_IF_TF_LEVEL_WIDTH 3 -#define UART_IF_TF_LEVEL_MASK (((1U << UART_IF_TF_LEVEL_WIDTH) - 1U) << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_0_8_BYTE (0U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_1_BYTE (1U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_2_BYTE (2U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_3_BYTE (3U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_4_BYTE (4U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_5_BYTE (5U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_6_BYTE (6U << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_7_BYTE (7U << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_SHIFT 20 +#define UART_IF_TF_LEVEL_WIDTH 3 +#define UART_IF_TF_LEVEL_MASK (((1U << UART_IF_TF_LEVEL_WIDTH) - 1U) << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_0_8_BYTE 0U +#define UART_IF_TF_LEVEL_BITS_0_8_BYTE (UART_IF_TF_LEVEL_VALUE_0_8_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_1_BYTE 1U +#define UART_IF_TF_LEVEL_BITS_1_BYTE (UART_IF_TF_LEVEL_VALUE_1_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_2_BYTE 2U +#define UART_IF_TF_LEVEL_BITS_2_BYTE (UART_IF_TF_LEVEL_VALUE_2_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_3_BYTE 3U +#define UART_IF_TF_LEVEL_BITS_3_BYTE (UART_IF_TF_LEVEL_VALUE_3_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_4_BYTE 4U +#define UART_IF_TF_LEVEL_BITS_4_BYTE (UART_IF_TF_LEVEL_VALUE_4_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_5_BYTE 5U +#define UART_IF_TF_LEVEL_BITS_5_BYTE (UART_IF_TF_LEVEL_VALUE_5_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_6_BYTE 6U +#define UART_IF_TF_LEVEL_BITS_6_BYTE (UART_IF_TF_LEVEL_VALUE_6_BYTE << UART_IF_TF_LEVEL_SHIFT) +#define UART_IF_TF_LEVEL_VALUE_7_BYTE 7U +#define UART_IF_TF_LEVEL_BITS_7_BYTE (UART_IF_TF_LEVEL_VALUE_7_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_SHIFT 0 -#define UART_FIFO_RF_LEVEL_WIDTH 3 -#define UART_FIFO_RF_LEVEL_MASK (((1U << UART_FIFO_RF_LEVEL_WIDTH) - 1U) << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_1_BYTE (0U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_2_BYTE (1U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_3_BYTE (2U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_4_BYTE (3U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_5_BYTE (4U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_6_BYTE (5U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_7_BYTE (6U << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_8_BYTE (7U << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_SHIFT 0 +#define UART_FIFO_RF_LEVEL_WIDTH 3 +#define UART_FIFO_RF_LEVEL_MASK (((1U << UART_FIFO_RF_LEVEL_WIDTH) - 1U) << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_1_BYTE 0U +#define UART_FIFO_RF_LEVEL_BITS_1_BYTE (UART_FIFO_RF_LEVEL_VALUE_1_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_2_BYTE 1U +#define UART_FIFO_RF_LEVEL_BITS_2_BYTE (UART_FIFO_RF_LEVEL_VALUE_2_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_3_BYTE 2U +#define UART_FIFO_RF_LEVEL_BITS_3_BYTE (UART_FIFO_RF_LEVEL_VALUE_3_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_4_BYTE 3U +#define UART_FIFO_RF_LEVEL_BITS_4_BYTE (UART_FIFO_RF_LEVEL_VALUE_4_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_5_BYTE 4U +#define UART_FIFO_RF_LEVEL_BITS_5_BYTE (UART_FIFO_RF_LEVEL_VALUE_5_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_6_BYTE 5U +#define UART_FIFO_RF_LEVEL_BITS_6_BYTE (UART_FIFO_RF_LEVEL_VALUE_6_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_7_BYTE 6U +#define UART_FIFO_RF_LEVEL_BITS_7_BYTE (UART_FIFO_RF_LEVEL_VALUE_7_BYTE << UART_FIFO_RF_LEVEL_SHIFT) +#define UART_FIFO_RF_LEVEL_VALUE_8_BYTE 7U +#define UART_FIFO_RF_LEVEL_BITS_8_BYTE (UART_FIFO_RF_LEVEL_VALUE_8_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_SHIFT 3 -#define UART_FIFO_TF_LEVEL_WIDTH 3 -#define UART_FIFO_TF_LEVEL_MASK (((1U << UART_FIFO_TF_LEVEL_WIDTH) - 1U) << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_0_BYTE (0U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_1_BYTE (1U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_2_BYTE (2U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_3_BYTE (3U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_4_BYTE (4U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_5_BYTE (5U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_6_BYTE (6U << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_7_BYTE (7U << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_SHIFT 3 +#define UART_FIFO_TF_LEVEL_WIDTH 3 +#define UART_FIFO_TF_LEVEL_MASK (((1U << UART_FIFO_TF_LEVEL_WIDTH) - 1U) << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_0_BYTE 0U +#define UART_FIFO_TF_LEVEL_BITS_0_BYTE (UART_FIFO_TF_LEVEL_VALUE_0_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_1_BYTE 1U +#define UART_FIFO_TF_LEVEL_BITS_1_BYTE (UART_FIFO_TF_LEVEL_VALUE_1_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_2_BYTE 2U +#define UART_FIFO_TF_LEVEL_BITS_2_BYTE (UART_FIFO_TF_LEVEL_VALUE_2_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_3_BYTE 3U +#define UART_FIFO_TF_LEVEL_BITS_3_BYTE (UART_FIFO_TF_LEVEL_VALUE_3_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_4_BYTE 4U +#define UART_FIFO_TF_LEVEL_BITS_4_BYTE (UART_FIFO_TF_LEVEL_VALUE_4_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_5_BYTE 5U +#define UART_FIFO_TF_LEVEL_BITS_5_BYTE (UART_FIFO_TF_LEVEL_VALUE_5_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_6_BYTE 6U +#define UART_FIFO_TF_LEVEL_BITS_6_BYTE (UART_FIFO_TF_LEVEL_VALUE_6_BYTE << UART_FIFO_TF_LEVEL_SHIFT) +#define UART_FIFO_TF_LEVEL_VALUE_7_BYTE 7U +#define UART_FIFO_TF_LEVEL_BITS_7_BYTE (UART_FIFO_TF_LEVEL_VALUE_7_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_RF_CLR_SHIFT 6 -#define UART_FIFO_RF_CLR_WIDTH 1 -#define UART_FIFO_RF_CLR_MASK (((1U << UART_FIFO_RF_CLR_WIDTH) - 1U) << UART_FIFO_RF_CLR_SHIFT) -#define UART_FIFO_RF_CLR_DISABLE (0U << UART_FIFO_RF_CLR_SHIFT) -#define UART_FIFO_RF_CLR_ENABLE (1U << UART_FIFO_RF_CLR_SHIFT) +#define UART_FIFO_RF_CLR_SHIFT 6 +#define UART_FIFO_RF_CLR_WIDTH 1 +#define UART_FIFO_RF_CLR_MASK (((1U << UART_FIFO_RF_CLR_WIDTH) - 1U) << UART_FIFO_RF_CLR_SHIFT) +#define UART_FIFO_RF_CLR_VALUE_DISABLE 0U +#define UART_FIFO_RF_CLR_BITS_DISABLE (UART_FIFO_RF_CLR_VALUE_DISABLE << UART_FIFO_RF_CLR_SHIFT) +#define UART_FIFO_RF_CLR_VALUE_ENABLE 1U +#define UART_FIFO_RF_CLR_BITS_ENABLE (UART_FIFO_RF_CLR_VALUE_ENABLE << UART_FIFO_RF_CLR_SHIFT) -#define UART_FIFO_TF_CLR_SHIFT 7 -#define UART_FIFO_TF_CLR_WIDTH 1 -#define UART_FIFO_TF_CLR_MASK (((1U << UART_FIFO_TF_CLR_WIDTH) - 1U) << UART_FIFO_TF_CLR_SHIFT) -#define UART_FIFO_TF_CLR_DISABLE (0U << UART_FIFO_TF_CLR_SHIFT) -#define UART_FIFO_TF_CLR_ENABLE (1U << UART_FIFO_TF_CLR_SHIFT) +#define UART_FIFO_TF_CLR_SHIFT 7 +#define UART_FIFO_TF_CLR_WIDTH 1 +#define UART_FIFO_TF_CLR_MASK (((1U << UART_FIFO_TF_CLR_WIDTH) - 1U) << UART_FIFO_TF_CLR_SHIFT) +#define UART_FIFO_TF_CLR_VALUE_DISABLE 0U +#define UART_FIFO_TF_CLR_BITS_DISABLE (UART_FIFO_TF_CLR_VALUE_DISABLE << UART_FIFO_TF_CLR_SHIFT) +#define UART_FIFO_TF_CLR_VALUE_ENABLE 1U +#define UART_FIFO_TF_CLR_BITS_ENABLE (UART_FIFO_TF_CLR_VALUE_ENABLE << UART_FIFO_TF_CLR_SHIFT) -#define UART_FC_CTSEN_SHIFT 0 -#define UART_FC_CTSEN_WIDTH 1 -#define UART_FC_CTSEN_MASK (((1U << UART_FC_CTSEN_WIDTH) - 1U) << UART_FC_CTSEN_SHIFT) -#define UART_FC_CTSEN_DISABLE (0U << UART_FC_CTSEN_SHIFT) -#define UART_FC_CTSEN_ENABLE (1U << UART_FC_CTSEN_SHIFT) +#define UART_FC_CTSEN_SHIFT 0 +#define UART_FC_CTSEN_WIDTH 1 +#define UART_FC_CTSEN_MASK (((1U << UART_FC_CTSEN_WIDTH) - 1U) << UART_FC_CTSEN_SHIFT) +#define UART_FC_CTSEN_VALUE_DISABLE 0U +#define UART_FC_CTSEN_BITS_DISABLE (UART_FC_CTSEN_VALUE_DISABLE << UART_FC_CTSEN_SHIFT) +#define UART_FC_CTSEN_VALUE_ENABLE 1U +#define UART_FC_CTSEN_BITS_ENABLE (UART_FC_CTSEN_VALUE_ENABLE << UART_FC_CTSEN_SHIFT) -#define UART_FC_RTSEN_SHIFT 1 -#define UART_FC_RTSEN_WIDTH 1 -#define UART_FC_RTSEN_MASK (((1U << UART_FC_RTSEN_WIDTH) - 1U) << UART_FC_RTSEN_SHIFT) -#define UART_FC_RTSEN_DISABLE (0U << UART_FC_RTSEN_SHIFT) -#define UART_FC_RTSEN_ENABLE (1U << UART_FC_RTSEN_SHIFT) +#define UART_FC_RTSEN_SHIFT 1 +#define UART_FC_RTSEN_WIDTH 1 +#define UART_FC_RTSEN_MASK (((1U << UART_FC_RTSEN_WIDTH) - 1U) << UART_FC_RTSEN_SHIFT) +#define UART_FC_RTSEN_VALUE_DISABLE 0U +#define UART_FC_RTSEN_BITS_DISABLE (UART_FC_RTSEN_VALUE_DISABLE << UART_FC_RTSEN_SHIFT) +#define UART_FC_RTSEN_VALUE_ENABLE 1U +#define UART_FC_RTSEN_BITS_ENABLE (UART_FC_RTSEN_VALUE_ENABLE << UART_FC_RTSEN_SHIFT) -#define UART_FC_CTSPOL_SHIFT 2 -#define UART_FC_CTSPOL_WIDTH 1 -#define UART_FC_CTSPOL_MASK (((1U << UART_FC_CTSPOL_WIDTH) - 1U) << UART_FC_CTSPOL_SHIFT) -#define UART_FC_CTSPOL_LOW (0U << UART_FC_CTSPOL_SHIFT) -#define UART_FC_CTSPOL_HIGH (1U << UART_FC_CTSPOL_SHIFT) +#define UART_FC_CTSPOL_SHIFT 2 +#define UART_FC_CTSPOL_WIDTH 1 +#define UART_FC_CTSPOL_MASK (((1U << UART_FC_CTSPOL_WIDTH) - 1U) << UART_FC_CTSPOL_SHIFT) +#define UART_FC_CTSPOL_VALUE_LOW 0U +#define UART_FC_CTSPOL_BITS_LOW (UART_FC_CTSPOL_VALUE_LOW << UART_FC_CTSPOL_SHIFT) +#define UART_FC_CTSPOL_VALUE_HIGH 1U +#define UART_FC_CTSPOL_BITS_HIGH (UART_FC_CTSPOL_VALUE_HIGH << UART_FC_CTSPOL_SHIFT) -#define UART_FC_RTSPOL_SHIFT 3 -#define UART_FC_RTSPOL_WIDTH 1 -#define UART_FC_RTSPOL_MASK (((1U << UART_FC_RTSPOL_WIDTH) - 1U) << UART_FC_RTSPOL_SHIFT) -#define UART_FC_RTSPOL_LOW (0U << UART_FC_RTSPOL_SHIFT) -#define UART_FC_RTSPOL_HIGH (1U << UART_FC_RTSPOL_SHIFT) +#define UART_FC_RTSPOL_SHIFT 3 +#define UART_FC_RTSPOL_WIDTH 1 +#define UART_FC_RTSPOL_MASK (((1U << UART_FC_RTSPOL_WIDTH) - 1U) << UART_FC_RTSPOL_SHIFT) +#define UART_FC_RTSPOL_VALUE_LOW 0U +#define UART_FC_RTSPOL_BITS_LOW (UART_FC_RTSPOL_VALUE_LOW << UART_FC_RTSPOL_SHIFT) +#define UART_FC_RTSPOL_VALUE_HIGH 1U +#define UART_FC_RTSPOL_BITS_HIGH (UART_FC_RTSPOL_VALUE_HIGH << UART_FC_RTSPOL_SHIFT) -#define UART_FC_CTS_SIGNAL_SHIFT 4 -#define UART_FC_CTS_SIGNAL_WIDTH 1 -#define UART_FC_CTS_SIGNAL_MASK (((1U << UART_FC_CTS_SIGNAL_WIDTH) - 1U) << UART_FC_CTS_SIGNAL_SHIFT) -#define UART_FC_CTS_SIGNAL_LOW (0U << UART_FC_CTS_SIGNAL_SHIFT) -#define UART_FC_CTS_SIGNAL_HIGH (1U << UART_FC_CTS_SIGNAL_SHIFT) +#define UART_FC_CTS_SIGNAL_SHIFT 4 +#define UART_FC_CTS_SIGNAL_WIDTH 1 +#define UART_FC_CTS_SIGNAL_MASK (((1U << UART_FC_CTS_SIGNAL_WIDTH) - 1U) << UART_FC_CTS_SIGNAL_SHIFT) +#define UART_FC_CTS_SIGNAL_VALUE_LOW 0U +#define UART_FC_CTS_SIGNAL_BITS_LOW (UART_FC_CTS_SIGNAL_VALUE_LOW << UART_FC_CTS_SIGNAL_SHIFT) +#define UART_FC_CTS_SIGNAL_VALUE_HIGH 1U +#define UART_FC_CTS_SIGNAL_BITS_HIGH (UART_FC_CTS_SIGNAL_VALUE_HIGH << UART_FC_CTS_SIGNAL_SHIFT) -#define UART_FC_RTS_SIGNAL_SHIFT 5 -#define UART_FC_RTS_SIGNAL_WIDTH 1 -#define UART_FC_RTS_SIGNAL_MASK (((1U << UART_FC_RTS_SIGNAL_WIDTH) - 1U) << UART_FC_RTS_SIGNAL_SHIFT) -#define UART_FC_RTS_SIGNAL_LOW (0U << UART_FC_RTS_SIGNAL_SHIFT) -#define UART_FC_RTS_SIGNAL_HIGH (1U << UART_FC_RTS_SIGNAL_SHIFT) +#define UART_FC_RTS_SIGNAL_SHIFT 5 +#define UART_FC_RTS_SIGNAL_WIDTH 1 +#define UART_FC_RTS_SIGNAL_MASK (((1U << UART_FC_RTS_SIGNAL_WIDTH) - 1U) << UART_FC_RTS_SIGNAL_SHIFT) +#define UART_FC_RTS_SIGNAL_VALUE_LOW 0U +#define UART_FC_RTS_SIGNAL_BITS_LOW (UART_FC_RTS_SIGNAL_VALUE_LOW << UART_FC_RTS_SIGNAL_SHIFT) +#define UART_FC_RTS_SIGNAL_VALUE_HIGH 1U +#define UART_FC_RTS_SIGNAL_BITS_HIGH (UART_FC_RTS_SIGNAL_VALUE_HIGH << UART_FC_RTS_SIGNAL_SHIFT) #endif diff --git a/driver/crc.c b/driver/crc.c index d5b0430..f0d01b1 100644 --- a/driver/crc.c +++ b/driver/crc.c @@ -20,13 +20,13 @@ void CRC_Init(void) { CRC_CR = 0 - | CRC_CR_CRC_EN_DISABLE - | CRC_CR_INPUT_REV_NORMAL - | CRC_CR_INPUT_INV_NORMAL - | CRC_CR_OUTPUT_REV_NORMAL - | CRC_CR_OUTPUT_INV_NORMAL - | CRC_CR_DATA_WIDTH_8 - | CRC_CR_CRC_SEL_CRC_16_CCITT + | CRC_CR_CRC_EN_BITS_DISABLE + | CRC_CR_INPUT_REV_BITS_NORMAL + | CRC_CR_INPUT_INV_BITS_NORMAL + | CRC_CR_OUTPUT_REV_BITS_NORMAL + | CRC_CR_OUTPUT_INV_BITS_NORMAL + | CRC_CR_DATA_WIDTH_BITS_8 + | CRC_CR_CRC_SEL_BITS_CRC_16_CCITT ; CRC_IV = 0; } @@ -36,14 +36,14 @@ uint16_t CRC_Calculate(const void *pBuffer, uint16_t Size) const uint8_t *pData = (const uint8_t *)pBuffer; uint16_t i, Crc; - CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_ENABLE; + CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_ENABLE; for (i = 0; i < Size; i++) { CRC_DATAIN = pData[i]; } Crc = CRC_DATAOUT; - CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_DISABLE; + CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_DISABLE; return Crc; } diff --git a/driver/flash.h b/driver/flash.h index 6c4ad82..713681b 100644 --- a/driver/flash.h +++ b/driver/flash.h @@ -20,33 +20,33 @@ #include "bsp/dp32g030/flash.h" enum FLASH_READ_MODE { - FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_1_CYCLE, - FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_2_CYCLE, + FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_BITS_1_CYCLE, + FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_BITS_2_CYCLE, }; typedef enum FLASH_READ_MODE FLASH_READ_MODE; enum FLASH_MASK_SELECTION { - FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_NONE, - FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_2KB, - FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_4KB, - FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_8KB, + FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_BITS_NONE, + FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_BITS_2KB, + FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_BITS_4KB, + FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_BITS_8KB, }; typedef enum FLASH_MASK_SELECTION FLASH_MASK_SELECTION; enum FLASH_MODE { - FLASH_MODE_READ_AHB = FLASH_CFG_MODE_READ_AHB, - FLASH_MODE_PROGRAM = FLASH_CFG_MODE_PROGRAM, - FLASH_MODE_ERASE = FLASH_CFG_MODE_ERASE, - FLASH_MODE_READ_APB = FLASH_CFG_MODE_READ_APB, + FLASH_MODE_READ_AHB = FLASH_CFG_MODE_BITS_READ_AHB, + FLASH_MODE_PROGRAM = FLASH_CFG_MODE_BITS_PROGRAM, + FLASH_MODE_ERASE = FLASH_CFG_MODE_BITS_ERASE, + FLASH_MODE_READ_APB = FLASH_CFG_MODE_BITS_READ_APB, }; typedef enum FLASH_MODE FLASH_MODE; enum FLASH_AREA { - FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_MAIN, - FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_NVR, + FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_BITS_MAIN, + FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_BITS_NVR, }; typedef enum FLASH_AREA FLASH_AREA; diff --git a/driver/i2c.c b/driver/i2c.c index 63ee3d0..aa28b05 100644 --- a/driver/i2c.c +++ b/driver/i2c.c @@ -48,7 +48,7 @@ uint8_t I2C_Read(bool bFinal) { uint8_t i, Data; - PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_ENABLE; + PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE; PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK; GPIOA->DIR &= ~GPIO_DIR_11_MASK; @@ -68,8 +68,8 @@ uint8_t I2C_Read(bool bFinal) } PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK; - PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_ENABLE; - GPIOA->DIR |= GPIO_DIR_11_OUTPUT; + PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE; + GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT; GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_Delay(1); if (bFinal) { @@ -107,7 +107,7 @@ int I2C_Write(uint8_t Data) SYSTICK_Delay(1); } - PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_ENABLE; + PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE; PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK; GPIOA->DIR &= ~GPIO_DIR_11_MASK; GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); @@ -125,8 +125,8 @@ int I2C_Write(uint8_t Data) GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_Delay(1); PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK; - PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_ENABLE; - GPIOA->DIR |= GPIO_DIR_11_OUTPUT; + PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE; + GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT; GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); return ret; diff --git a/driver/spi.c b/driver/spi.c index 42e8a2a..9fb5e02 100644 --- a/driver/spi.c +++ b/driver/spi.c @@ -59,15 +59,15 @@ void SPI_WaitForUndocumentedTxFifoStatusBit(void) void SPI_Disable(volatile uint32_t *pCR) { - *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_DISABLE; + *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_DISABLE; } void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig) { if (pPort == SPI0) { - SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_ENABLE; + SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE; } else if (pPort == SPI1) { - SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_ENABLE; + SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE; } SPI_Disable(&pPort->CR); @@ -103,14 +103,14 @@ void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig) void SPI_ToggleMasterMode(volatile uint32_t *pCR, bool bIsMaster) { if (bIsMaster) { - *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_ENABLE; + *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_ENABLE; } else { - *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_DISABLE; + *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_DISABLE; } } void SPI_Enable(volatile uint32_t *pCR) { - *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_ENABLE; + *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_ENABLE; } diff --git a/driver/st7565.c b/driver/st7565.c index 375c39a..3e363b3 100644 --- a/driver/st7565.c +++ b/driver/st7565.c @@ -35,13 +35,13 @@ void ST7565_DrawLine(uint8_t Column, uint8_t Line, uint16_t Size, const uint8_t if (bIsClearMode == false) { for (i = 0; i < Size; i++) { - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = pBitmap[i]; } } else { for (i = 0; i < Size; i++) { - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = 0; } @@ -63,7 +63,7 @@ void ST7565_BlitFullScreen(void) ST7565_SelectColumnAndLine(4U, Line + 1U); GPIO_SetBit(&GPIOB->DATA, 9U); for (Column = 0; Column < 128; Column++) { - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = gFrameBuffer[Line][Column]; } @@ -84,7 +84,7 @@ void ST7565_BlitStatusLine(void) GPIO_SetBit(&GPIOB->DATA, 9); for (i = 0; i < 0x80; i++) { - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = gStatusLine[i]; } @@ -101,7 +101,7 @@ void ST7565_FillScreen(uint8_t Value) ST7565_SelectColumnAndLine(0, i); GPIO_SetBit(&GPIOB->DATA, 9); for (j = 0; j < 132; j++) { - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = Value; } @@ -154,13 +154,13 @@ void ST7565_Configure_GPIO_B11(void) void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line) { GPIO_ClearBit(&GPIOB->DATA, 9); - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = Line + 0xB0; - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = ((Column >> 4) & 0x0F) | 0x10; - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = ((Column >> 0) & 0x0F); SPI_WaitForUndocumentedTxFifoStatusBit(); @@ -169,7 +169,7 @@ void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line) void ST7565_WriteByte(uint8_t Value) { GPIO_ClearBit(&GPIOB->DATA, 9); - while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_NOT_FULL) { + while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) { } SPI0->WDR = Value; } diff --git a/driver/system.c b/driver/system.c index 7ae2cd2..eebb59b 100644 --- a/driver/system.c +++ b/driver/system.c @@ -27,12 +27,12 @@ void SYSTEM_DelayUs(uint32_t Delay) void SYSTEM_ConfigureClocks(void) { // Set source clock from external crystal - PMU_SRC_CFG = (PMU_SRC_CFG & ~PMU_SRC_CFG_RTC_CLK_SEL_MASK) | PMU_SRC_CFG_RTC_CLK_SEL_XTAL; + PMU_SRC_CFG = (PMU_SRC_CFG & ~PMU_SRC_CFG_RTC_CLK_SEL_MASK) | PMU_SRC_CFG_RTC_CLK_SEL_BITS_XTAL; // Divide by 2 - SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_CLK_SEL_2; + SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_CLK_SEL_BITS_2; // Disable division clock gate - SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_DISABLE; + SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE; } diff --git a/driver/uart.c b/driver/uart.c index adb48f3..3c8533a 100644 --- a/driver/uart.c +++ b/driver/uart.c @@ -27,7 +27,7 @@ void UART_Init(void) uint32_t Positive; uint32_t Frequency; - UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_DISABLE; + UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE; Delta = SYSCON_RC_FREQ_DELTA; Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT; Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT; @@ -38,48 +38,48 @@ void UART_Init(void) } UART1->BAUD = Frequency / 39053U; - UART1->CTRL = UART_CTRL_RXEN_ENABLE | UART_CTRL_TXEN_ENABLE | UART_CTRL_RXDMAEN_ENABLE; + UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE; UART1->RXTO = 4; UART1->FC = 0; - UART1->FIFO = UART_FIFO_RF_LEVEL_8_BYTE | UART_FIFO_RF_CLR_ENABLE | UART_FIFO_TF_CLR_ENABLE; + UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE; UART1->IE = 0; - DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_DISABLE; + DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE; DMA_CH0->MSADDR = (uint32_t)(uintptr_t)&UART1->RDR; DMA_CH0->MDADDR = (uint32_t)(uintptr_t)UART_DMA_Buffer; DMA_CH0->MOD = 0 // Source - | DMA_CH_MOD_MS_ADDMOD_NONE - | DMA_CH_MOD_MS_SIZE_8BIT - | DMA_CH_MOD_MS_SEL_HSREQ_MS1 + | DMA_CH_MOD_MS_ADDMOD_BITS_NONE + | DMA_CH_MOD_MS_SIZE_BITS_8BIT + | DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1 // Destination - | DMA_CH_MOD_MD_ADDMOD_INCREMENT - | DMA_CH_MOD_MD_SIZE_8BIT - | DMA_CH_MOD_MD_SEL_SRAM + | DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT + | DMA_CH_MOD_MD_SIZE_BITS_8BIT + | DMA_CH_MOD_MD_SEL_BITS_SRAM ; DMA_INTEN = 0; DMA_INTST = 0 - | DMA_INTST_CH0_TC_INTST_SET - | DMA_INTST_CH1_TC_INTST_SET - | DMA_INTST_CH2_TC_INTST_SET - | DMA_INTST_CH3_TC_INTST_SET - | DMA_INTST_CH0_THC_INTST_SET - | DMA_INTST_CH1_THC_INTST_SET - | DMA_INTST_CH2_THC_INTST_SET - | DMA_INTST_CH3_THC_INTST_SET + | DMA_INTST_CH0_TC_INTST_BITS_SET + | DMA_INTST_CH1_TC_INTST_BITS_SET + | DMA_INTST_CH2_TC_INTST_BITS_SET + | DMA_INTST_CH3_TC_INTST_BITS_SET + | DMA_INTST_CH0_THC_INTST_BITS_SET + | DMA_INTST_CH1_THC_INTST_BITS_SET + | DMA_INTST_CH2_THC_INTST_BITS_SET + | DMA_INTST_CH3_THC_INTST_BITS_SET ; DMA_CH0->CTR = 0 - | DMA_CH_CTR_CH_EN_ENABLE + | DMA_CH_CTR_CH_EN_BITS_ENABLE | ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK) - | DMA_CH_CTR_LOOP_ENABLE - | DMA_CH_CTR_PRI_MEDIUM + | DMA_CH_CTR_LOOP_BITS_ENABLE + | DMA_CH_CTR_PRI_BITS_MEDIUM ; - UART1->IF = UART_IF_RXTO_SET; + UART1->IF = UART_IF_RXTO_BITS_SET; - DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_ENABLE; + DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE; - UART1->CTRL |= UART_CTRL_UARTEN_ENABLE; + UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE; } void UART_Send(const void *pBuffer, uint32_t Size) @@ -89,7 +89,7 @@ void UART_Send(const void *pBuffer, uint32_t Size) for (i = 0; i < Size; i++) { UART1->TDR = pData[i]; - while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_NOT_SET) { + while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) { } } } diff --git a/main.c b/main.c index cd79986..bd2279c 100644 --- a/main.c +++ b/main.c @@ -33,9 +33,9 @@ static const char Version[] = "UV-K5 Firmware, v0.01 Open Edition\r\n"; static void FLASHLIGHT_Init(void) { - PORTCON_PORTC_IE = PORTCON_PORTC_IE_C5_ENABLE; - PORTCON_PORTC_PU = PORTCON_PORTC_PU_C5_ENABLE; - GPIOC->DIR |= GPIO_DIR_3_OUTPUT; + PORTCON_PORTC_IE = PORTCON_PORTC_IE_C5_BITS_ENABLE; + PORTCON_PORTC_PU = PORTCON_PORTC_PU_C5_BITS_ENABLE; + GPIOC->DIR |= GPIO_DIR_3_BITS_OUTPUT; GPIO_SetBit(&GPIOC->DATA, 10); GPIO_SetBit(&GPIOC->DATA, 11); @@ -57,14 +57,14 @@ void Main(void) { // Enable clock gating of blocks we need. SYSCON_DEV_CLK_GATE = 0 - | SYSCON_DEV_CLK_GATE_GPIOA_ENABLE - | SYSCON_DEV_CLK_GATE_GPIOB_ENABLE - | SYSCON_DEV_CLK_GATE_GPIOC_ENABLE - | SYSCON_DEV_CLK_GATE_UART1_ENABLE - | SYSCON_DEV_CLK_GATE_SPI0_ENABLE - | SYSCON_DEV_CLK_GATE_SARADC_ENABLE - | SYSCON_DEV_CLK_GATE_CRC_ENABLE - | SYSCON_DEV_CLK_GATE_AES_ENABLE + | SYSCON_DEV_CLK_GATE_GPIOA_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_GPIOB_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_GPIOC_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_UART1_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_CRC_BITS_ENABLE + | SYSCON_DEV_CLK_GATE_AES_BITS_ENABLE ; SYSTICK_Init(); diff --git a/sram-overlay.c b/sram-overlay.c index f1f4e09..550627a 100644 --- a/sram-overlay.c +++ b/sram-overlay.c @@ -31,23 +31,23 @@ bool overlay_FLASH_RebootToBootloader(void) overlay_FLASH_MaskLock(); overlay_SystemReset(); - return (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_READY; + return (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_BITS_READY; } bool overlay_FLASH_IsBusy(void) { - return (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_READY; + return (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_BITS_READY; } bool overlay_FLASH_IsInitComplete(void) { - return (FLASH_ST & FLASH_ST_INIT_BUSY_MASK) == FLASH_ST_INIT_BUSY_COMPLETE; + return (FLASH_ST & FLASH_ST_INIT_BUSY_MASK) == FLASH_ST_INIT_BUSY_BITS_COMPLETE; } void overlay_FLASH_Start(void) { overlay_FLASH_Unlock(); - FLASH_START |= FLASH_START_START_START; + FLASH_START |= FLASH_START_START_BITS_START; } void overlay_FLASH_Init(FLASH_READ_MODE ReadMode) @@ -62,7 +62,7 @@ void overlay_FLASH_Init(FLASH_READ_MODE ReadMode) void overlay_FLASH_MaskLock(void) { - FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_SET; + FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_BITS_SET; } void overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION Mask) @@ -72,17 +72,17 @@ void overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION Mask) void overlay_FLASH_MaskUnlock(void) { - FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_NOT_SET; + FLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_BITS_NOT_SET; } void overlay_FLASH_Lock(void) { - FLASH_LOCK = FLASH_LOCK_LOCK_LOCK; + FLASH_LOCK = FLASH_LOCK_LOCK_BITS_LOCK; } void overlay_FLASH_Unlock(void) { - FLASH_UNLOCK = FLASH_UNLOCK_UNLOCK_UNLOCK; + FLASH_UNLOCK = FLASH_UNLOCK_UNLOCK_BITS_UNLOCK; } uint32_t overlay_FLASH_ReadByAHB(uint32_t Offset) @@ -121,9 +121,9 @@ void overlay_FLASH_SetArea(FLASH_AREA Area) void overlay_FLASH_SetReadMode(FLASH_READ_MODE Mode) { if (Mode == FLASH_READ_MODE_1_CYCLE) { - FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_1_CYCLE; + FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_BITS_1_CYCLE; } else if (Mode == FLASH_READ_MODE_2_CYCLE) { - FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_2_CYCLE; + FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_BITS_2_CYCLE; } } @@ -134,7 +134,7 @@ void overlay_FLASH_SetEraseTime(void) void overlay_FLASH_WakeFromDeepSleep(void) { - FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_DEEP_PD_MASK) | FLASH_CFG_DEEP_PD_NORMAL; + FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_DEEP_PD_MASK) | FLASH_CFG_DEEP_PD_BITS_NORMAL; while (!overlay_FLASH_IsInitComplete()) { } } @@ -203,7 +203,7 @@ void overlay_FLASH_ConfigureTrimValues(void) overlay_0x20000478 = overlay_FLASH_ReadByAHB(0x07B8); Data = overlay_FLASH_ReadByAHB(0x07BC); - SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_ENABLE; + SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE; SARADC_ADC_CALIB_OFFSET = ((Data & 0xFFFF) << SARADC_ADC_CALIB_OFFSET_OFFSET_SHIFT) & SARADC_ADC_CALIB_OFFSET_OFFSET_MASK; SARADC_ADC_CALIB_KD = (((Data >> 16) & 0xFFFF) << SARADC_ADC_CALIB_KD_KD_SHIFT) & SARADC_ADC_CALIB_KD_KD_MASK; overlay_FLASH_SetArea(FLASH_AREA_MAIN);