uv-k5-firmware/board.c

/* Copyright 2023 Dual Tachyon
 * https://github.com/DualTachyon
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 *     Unless required by applicable law or agreed to in writing, software
 *     distributed under the License is distributed on an "AS IS" BASIS,
 *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *     See the License for the specific language governing permissions and
 *     limitations under the License.
 *
 */

#include "board.h"
#include "bsp/dp32g030/gpio.h"
#include "bsp/dp32g030/portcon.h"
#include "driver/crc.h"
#include "driver/flash.h"
#include "driver/gpio.h"
#include "driver/system.h"
#include "driver/st7565.h"
#include "sram-overlay.h"

void BOARD_FLASH_Init(void)
{
	FLASH_Init(FLASH_READ_MODE_1_CYCLE);
	FLASH_ConfigureTrimValues();
	SYSTEM_ConfigureClocks();
	overlay_FLASH_MainClock = 48000000;
	overlay_FLASH_ClockMultiplier = 48;
	FLASH_Init(FLASH_READ_MODE_2_CYCLE);
}

void BOARD_GPIO_Init(void)
{
	GPIOA->DIR |= 0
		| GPIO_DIR_10_OUTPUT
		| GPIO_DIR_11_OUTPUT
		| GPIO_DIR_12_OUTPUT
		| GPIO_DIR_13_OUTPUT
		;
	GPIOA->DIR &= ~(0
		| GPIO_DIR_3_MASK
		| GPIO_DIR_4_MASK
		| GPIO_DIR_5_MASK
		| GPIO_DIR_6_MASK
		);
	GPIOB->DIR |= 0
		| GPIO_DIR_6_OUTPUT
		| GPIO_DIR_9_OUTPUT
		| GPIO_DIR_11_OUTPUT
		| GPIO_DIR_15_OUTPUT
		;
	GPIOC->DIR |= 0
		| GPIO_DIR_0_OUTPUT
		| GPIO_DIR_1_OUTPUT
		| GPIO_DIR_2_OUTPUT
		| GPIO_DIR_3_OUTPUT
		| GPIO_DIR_4_OUTPUT
		;
	GPIOC->DIR &= ~(0
		| GPIO_DIR_5_MASK
		);

	GPIO_SetBit(&GPIOB->DATA, 15);
}

void BOARD_PORTCON_Init(void)
{
	// TODO: Need to redo these macros to make more sense.

	// PORT A pin selection

	PORTCON_PORTA_SEL0 &= 0
		| PORTCON_PORTA_SEL0_A0_MASK
		| PORTCON_PORTA_SEL0_A1_MASK
		| PORTCON_PORTA_SEL0_A2_MASK
		| PORTCON_PORTA_SEL0_A7_MASK
		;
	PORTCON_PORTA_SEL0 |= 0
		| PORTCON_PORTA_SEL0_A0_GPIOA0
		| PORTCON_PORTA_SEL0_A1_GPIOA1
		| PORTCON_PORTA_SEL0_A2_GPIOA2
		| PORTCON_PORTA_SEL0_A7_UART1_TX
		;

	PORTCON_PORTA_SEL1 &= 0
		| PORTCON_PORTA_SEL1_A8_MASK
		| PORTCON_PORTA_SEL1_A9_MASK
		| PORTCON_PORTA_SEL1_A14_MASK
		| PORTCON_PORTA_SEL1_A15_MASK
		;
	PORTCON_PORTA_SEL1 |= 0
		| PORTCON_PORTA_SEL1_A8_UART1_RX
		| PORTCON_PORTA_SEL1_A9_SARADC_CH4
		| PORTCON_PORTA_SEL1_A14_SARADC_CH9
		| PORTCON_PORTA_SEL1_A15_GPIOA15
		;

	// PORT B pin selection

	PORTCON_PORTB_SEL0 &= 0
		| PORTCON_PORTB_SEL0_B0_MASK
		| PORTCON_PORTB_SEL0_B1_MASK
		| PORTCON_PORTB_SEL0_B2_MASK
		| PORTCON_PORTB_SEL0_B3_MASK
		| PORTCON_PORTB_SEL0_B4_MASK
		| PORTCON_PORTB_SEL0_B5_MASK
		;
	PORTCON_PORTB_SEL0 |= 0
		| PORTCON_PORTB_SEL0_B0_GPIOB0
		| PORTCON_PORTB_SEL0_B1_GPIOB1
		| PORTCON_PORTB_SEL0_B2_GPIOB2
		| PORTCON_PORTB_SEL0_B3_GPIOB3
		| PORTCON_PORTB_SEL0_B4_GPIOB4
		| PORTCON_PORTB_SEL0_B5_GPIOB5
		| PORTCON_PORTB_SEL0_B7_SPI0_SSN
		;

	PORTCON_PORTB_SEL1 &= 0
		| PORTCON_PORTB_SEL1_B8_MASK
		| PORTCON_PORTB_SEL1_B10_MASK
		| PORTCON_PORTB_SEL1_B12_MASK
		| PORTCON_PORTB_SEL1_B13_MASK
		;
	PORTCON_PORTB_SEL1 |= 0
		| PORTCON_PORTB_SEL1_B8_SPI0_CLK
		| PORTCON_PORTB_SEL1_B10_SPI0_MOSI
		| PORTCON_PORTB_SEL1_B11_SWDIO
		| PORTCON_PORTB_SEL1_B12_GPIOB12
		| PORTCON_PORTB_SEL1_B13_GPIOB13
		| PORTCON_PORTB_SEL1_B14_SWCLK
		;

	// PORT C pin selection

	PORTCON_PORTC_SEL0 &= 0
		| PORTCON_PORTC_SEL0_C6_MASK
		| PORTCON_PORTC_SEL0_C7_MASK
		;

	// PORT A pin configuration

	PORTCON_PORTA_IE |= 0
		| PORTCON_PORTA_IE_A3_ENABLE
		| PORTCON_PORTA_IE_A4_ENABLE
		| PORTCON_PORTA_IE_A5_ENABLE
		| PORTCON_PORTA_IE_A6_ENABLE
		| PORTCON_PORTA_IE_A8_ENABLE
		;
	PORTCON_PORTA_IE &= ~(0
		| PORTCON_PORTA_IE_A10_MASK
		| PORTCON_PORTA_IE_A11_MASK
		| PORTCON_PORTA_IE_A12_MASK
		| PORTCON_PORTA_IE_A13_MASK
		);

	PORTCON_PORTA_PU |= 0
		| PORTCON_PORTA_PU_A3_ENABLE
		| PORTCON_PORTA_PU_A4_ENABLE
		| PORTCON_PORTA_PU_A5_ENABLE
		| PORTCON_PORTA_PU_A6_ENABLE
		;
	PORTCON_PORTA_PU &= ~(0
		| PORTCON_PORTA_PU_A10_MASK
		| PORTCON_PORTA_PU_A11_MASK
		| PORTCON_PORTA_PU_A12_MASK
		| PORTCON_PORTA_PU_A13_MASK
		);

	PORTCON_PORTA_PD &= ~(0
		| PORTCON_PORTA_PD_A3_MASK
		| PORTCON_PORTA_PD_A4_MASK
		| PORTCON_PORTA_PD_A5_MASK
		| PORTCON_PORTA_PD_A6_MASK
		| PORTCON_PORTA_PD_A10_MASK
		| PORTCON_PORTA_PD_A11_MASK
		| PORTCON_PORTA_PD_A12_MASK
		| PORTCON_PORTA_PD_A13_MASK
		);

	PORTCON_PORTA_OD |= 0
		| PORTCON_PORTA_OD_A3_ENABLE
		| PORTCON_PORTA_OD_A4_ENABLE
		| PORTCON_PORTA_OD_A5_ENABLE
		| PORTCON_PORTA_OD_A6_ENABLE
		;
	PORTCON_PORTA_OD &= ~(0
		| PORTCON_PORTA_OD_A10_MASK
		| PORTCON_PORTA_OD_A11_MASK
		| PORTCON_PORTA_OD_A12_MASK
		| PORTCON_PORTA_OD_A13_MASK
		);

	// PORT B pin configuration

	PORTCON_PORTB_IE |= 0
		| PORTCON_PORTB_IE_B14_ENABLE
		;
	PORTCON_PORTB_IE &= ~(0
		| PORTCON_PORTB_IE_B6_MASK
		| PORTCON_PORTB_IE_B7_MASK
		| PORTCON_PORTB_IE_B8_MASK
		| PORTCON_PORTB_IE_B9_MASK
		| PORTCON_PORTB_IE_B10_MASK
		| PORTCON_PORTB_IE_B15_MASK
		);

	PORTCON_PORTB_PU &= ~(0
		| PORTCON_PORTB_PU_B6_MASK
		| PORTCON_PORTB_PU_B9_MASK
		| PORTCON_PORTB_PU_B11_MASK
		| PORTCON_PORTB_PU_B14_MASK
		| PORTCON_PORTB_PU_B15_MASK
		);

	PORTCON_PORTB_PD &= ~(0
		| PORTCON_PORTB_PD_B6_MASK
		| PORTCON_PORTB_PD_B9_MASK
		| PORTCON_PORTB_PD_B11_MASK
		| PORTCON_PORTB_PD_B14_MASK
		| PORTCON_PORTB_PD_B15_MASK
		);

	PORTCON_PORTB_OD &= ~(0
		| PORTCON_PORTB_OD_B6_MASK
		| PORTCON_PORTB_OD_B9_MASK
		| PORTCON_PORTB_OD_B11_MASK
		| PORTCON_PORTB_OD_B15_MASK
		);

	PORTCON_PORTB_OD |= 0
		| PORTCON_PORTB_OD_B14_ENABLE
		;

	// PORT C pin configuration

	PORTCON_PORTC_IE |= 0
		| PORTCON_PORTC_IE_C5_ENABLE
		;
	PORTCON_PORTC_IE &= ~(0
		| PORTCON_PORTC_IE_C0_MASK
		| PORTCON_PORTC_IE_C1_MASK
		| PORTCON_PORTC_IE_C2_MASK
		| PORTCON_PORTC_IE_C3_MASK
		| PORTCON_PORTC_IE_C4_MASK
		);

	PORTCON_PORTC_PU |= 0
		| PORTCON_PORTC_PU_C5_ENABLE
		;
	PORTCON_PORTC_PU &= ~(0
		| PORTCON_PORTC_PU_C0_MASK
		| PORTCON_PORTC_PU_C1_MASK
		| PORTCON_PORTC_PU_C2_MASK
		| PORTCON_PORTC_PU_C3_MASK
		| PORTCON_PORTC_PU_C4_MASK
		);

	PORTCON_PORTC_PD &= ~(0
		| PORTCON_PORTC_PD_C0_MASK
		| PORTCON_PORTC_PD_C1_MASK
		| PORTCON_PORTC_PD_C2_MASK
		| PORTCON_PORTC_PD_C3_MASK
		| PORTCON_PORTC_PD_C4_MASK
		| PORTCON_PORTC_PD_C5_MASK
		);

	PORTCON_PORTC_OD &= ~(0
		| PORTCON_PORTC_OD_C0_MASK
		| PORTCON_PORTC_OD_C1_MASK
		| PORTCON_PORTC_OD_C2_MASK
		| PORTCON_PORTC_OD_C3_MASK
		| PORTCON_PORTC_OD_C4_MASK
		);
	PORTCON_PORTC_OD |= 0
		| PORTCON_PORTC_OD_C5_ENABLE
		;
}

void BOARD_Init(void)
{
	BOARD_PORTCON_Init();
	BOARD_GPIO_Init();
	//ADC_Init();
	ST7565_Init();
	//BK1080_Init(0, false);
	CRC_Init();
}