uv-k5-firmware/board.c

/* Copyright 2023 Dual Tachyon
 * https://github.com/DualTachyon
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 *     Unless required by applicable law or agreed to in writing, software
 *     distributed under the License is distributed on an "AS IS" BASIS,
 *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *     See the License for the specific language governing permissions and
 *     limitations under the License.
 *
 */

#include "board.h"
#include "bsp/dp32g030/gpio.h"
#include "bsp/dp32g030/portcon.h"
#include "bsp/dp32g030/saradc.h"
#include "bsp/dp32g030/syscon.h"
#include "driver/adc.h"
#include "driver/bk1080.h"
#include "driver/crc.h"
#include "driver/flash.h"
#include "driver/gpio.h"
#include "driver/system.h"
#include "driver/st7565.h"
#include "sram-overlay.h"

void BOARD_FLASH_Init(void)
{
	FLASH_Init(FLASH_READ_MODE_1_CYCLE);
	FLASH_ConfigureTrimValues();
	SYSTEM_ConfigureClocks();
	overlay_FLASH_MainClock = 48000000;
	overlay_FLASH_ClockMultiplier = 48;
	FLASH_Init(FLASH_READ_MODE_2_CYCLE);
}

void BOARD_GPIO_Init(void)
{
	GPIOA->DIR |= 0
		| GPIO_DIR_10_BITS_OUTPUT
		| GPIO_DIR_11_BITS_OUTPUT
		| GPIO_DIR_12_BITS_OUTPUT
		| GPIO_DIR_13_BITS_OUTPUT
		;
	GPIOA->DIR &= ~(0
		| GPIO_DIR_3_MASK
		| GPIO_DIR_4_MASK
		| GPIO_DIR_5_MASK
		| GPIO_DIR_6_MASK
		);
	GPIOB->DIR |= 0
		| GPIO_DIR_6_BITS_OUTPUT
		| GPIO_DIR_9_BITS_OUTPUT
		| GPIO_DIR_11_BITS_OUTPUT
		| GPIO_DIR_15_BITS_OUTPUT
		;
	GPIOC->DIR |= 0
		| GPIO_DIR_0_BITS_OUTPUT
		| GPIO_DIR_1_BITS_OUTPUT
		| GPIO_DIR_2_BITS_OUTPUT
		| GPIO_DIR_3_BITS_OUTPUT
		| GPIO_DIR_4_BITS_OUTPUT
		;
	GPIOC->DIR &= ~(0
		| GPIO_DIR_5_MASK
		);

	GPIO_SetBit(&GPIOB->DATA, 15);
}

void BOARD_PORTCON_Init(void)
{
	// TODO: Need to redo these macros to make more sense.

	// PORT A pin selection

	PORTCON_PORTA_SEL0 &= 0
		| PORTCON_PORTA_SEL0_A0_MASK
		| PORTCON_PORTA_SEL0_A1_MASK
		| PORTCON_PORTA_SEL0_A2_MASK
		| PORTCON_PORTA_SEL0_A7_MASK
		;
	PORTCON_PORTA_SEL0 |= 0
		| PORTCON_PORTA_SEL0_A0_BITS_GPIOA0
		| PORTCON_PORTA_SEL0_A1_BITS_GPIOA1
		| PORTCON_PORTA_SEL0_A2_BITS_GPIOA2
		| PORTCON_PORTA_SEL0_A7_BITS_UART1_TX
		;

	PORTCON_PORTA_SEL1 &= 0
		| PORTCON_PORTA_SEL1_A8_MASK
		| PORTCON_PORTA_SEL1_A9_MASK
		| PORTCON_PORTA_SEL1_A14_MASK
		| PORTCON_PORTA_SEL1_A15_MASK
		;
	PORTCON_PORTA_SEL1 |= 0
		| PORTCON_PORTA_SEL1_A8_BITS_UART1_RX
		| PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4
		| PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9
		| PORTCON_PORTA_SEL1_A15_BITS_GPIOA15
		;

	// PORT B pin selection

	PORTCON_PORTB_SEL0 &= 0
		| PORTCON_PORTB_SEL0_B0_MASK
		| PORTCON_PORTB_SEL0_B1_MASK
		| PORTCON_PORTB_SEL0_B2_MASK
		| PORTCON_PORTB_SEL0_B3_MASK
		| PORTCON_PORTB_SEL0_B4_MASK
		| PORTCON_PORTB_SEL0_B5_MASK
		;
	PORTCON_PORTB_SEL0 |= 0
		| PORTCON_PORTB_SEL0_B0_BITS_GPIOB0
		| PORTCON_PORTB_SEL0_B1_BITS_GPIOB1
		| PORTCON_PORTB_SEL0_B2_BITS_GPIOB2
		| PORTCON_PORTB_SEL0_B3_BITS_GPIOB3
		| PORTCON_PORTB_SEL0_B4_BITS_GPIOB4
		| PORTCON_PORTB_SEL0_B5_BITS_GPIOB5
		| PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN
		;

	PORTCON_PORTB_SEL1 &= 0
		| PORTCON_PORTB_SEL1_B8_MASK
		| PORTCON_PORTB_SEL1_B10_MASK
		| PORTCON_PORTB_SEL1_B12_MASK
		| PORTCON_PORTB_SEL1_B13_MASK
		;
	PORTCON_PORTB_SEL1 |= 0
		| PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK
		| PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI
		| PORTCON_PORTB_SEL1_B11_BITS_SWDIO
		| PORTCON_PORTB_SEL1_B12_BITS_GPIOB12
		| PORTCON_PORTB_SEL1_B13_BITS_GPIOB13
		| PORTCON_PORTB_SEL1_B14_BITS_SWCLK
		;

	// PORT C pin selection

	PORTCON_PORTC_SEL0 &= 0
		| PORTCON_PORTC_SEL0_C6_MASK
		| PORTCON_PORTC_SEL0_C7_MASK
		;

	// PORT A pin configuration

	PORTCON_PORTA_IE |= 0
		| PORTCON_PORTA_IE_A3_BITS_ENABLE
		| PORTCON_PORTA_IE_A4_BITS_ENABLE
		| PORTCON_PORTA_IE_A5_BITS_ENABLE
		| PORTCON_PORTA_IE_A6_BITS_ENABLE
		| PORTCON_PORTA_IE_A8_BITS_ENABLE
		;
	PORTCON_PORTA_IE &= ~(0
		| PORTCON_PORTA_IE_A10_MASK
		| PORTCON_PORTA_IE_A11_MASK
		| PORTCON_PORTA_IE_A12_MASK
		| PORTCON_PORTA_IE_A13_MASK
		);

	PORTCON_PORTA_PU |= 0
		| PORTCON_PORTA_PU_A3_BITS_ENABLE
		| PORTCON_PORTA_PU_A4_BITS_ENABLE
		| PORTCON_PORTA_PU_A5_BITS_ENABLE
		| PORTCON_PORTA_PU_A6_BITS_ENABLE
		;
	PORTCON_PORTA_PU &= ~(0
		| PORTCON_PORTA_PU_A10_MASK
		| PORTCON_PORTA_PU_A11_MASK
		| PORTCON_PORTA_PU_A12_MASK
		| PORTCON_PORTA_PU_A13_MASK
		);

	PORTCON_PORTA_PD &= ~(0
		| PORTCON_PORTA_PD_A3_MASK
		| PORTCON_PORTA_PD_A4_MASK
		| PORTCON_PORTA_PD_A5_MASK
		| PORTCON_PORTA_PD_A6_MASK
		| PORTCON_PORTA_PD_A10_MASK
		| PORTCON_PORTA_PD_A11_MASK
		| PORTCON_PORTA_PD_A12_MASK
		| PORTCON_PORTA_PD_A13_MASK
		);

	PORTCON_PORTA_OD |= 0
		| PORTCON_PORTA_OD_A3_BITS_ENABLE
		| PORTCON_PORTA_OD_A4_BITS_ENABLE
		| PORTCON_PORTA_OD_A5_BITS_ENABLE
		| PORTCON_PORTA_OD_A6_BITS_ENABLE
		;
	PORTCON_PORTA_OD &= ~(0
		| PORTCON_PORTA_OD_A10_MASK
		| PORTCON_PORTA_OD_A11_MASK
		| PORTCON_PORTA_OD_A12_MASK
		| PORTCON_PORTA_OD_A13_MASK
		);

	// PORT B pin configuration

	PORTCON_PORTB_IE |= 0
		| PORTCON_PORTB_IE_B14_BITS_ENABLE
		;
	PORTCON_PORTB_IE &= ~(0
		| PORTCON_PORTB_IE_B6_MASK
		| PORTCON_PORTB_IE_B7_MASK
		| PORTCON_PORTB_IE_B8_MASK
		| PORTCON_PORTB_IE_B9_MASK
		| PORTCON_PORTB_IE_B10_MASK
		| PORTCON_PORTB_IE_B15_MASK
		);

	PORTCON_PORTB_PU &= ~(0
		| PORTCON_PORTB_PU_B6_MASK
		| PORTCON_PORTB_PU_B9_MASK
		| PORTCON_PORTB_PU_B11_MASK
		| PORTCON_PORTB_PU_B14_MASK
		| PORTCON_PORTB_PU_B15_MASK
		);

	PORTCON_PORTB_PD &= ~(0
		| PORTCON_PORTB_PD_B6_MASK
		| PORTCON_PORTB_PD_B9_MASK
		| PORTCON_PORTB_PD_B11_MASK
		| PORTCON_PORTB_PD_B14_MASK
		| PORTCON_PORTB_PD_B15_MASK
		);

	PORTCON_PORTB_OD &= ~(0
		| PORTCON_PORTB_OD_B6_MASK
		| PORTCON_PORTB_OD_B9_MASK
		| PORTCON_PORTB_OD_B11_MASK
		| PORTCON_PORTB_OD_B15_MASK
		);

	PORTCON_PORTB_OD |= 0
		| PORTCON_PORTB_OD_B14_BITS_ENABLE
		;

	// PORT C pin configuration

	PORTCON_PORTC_IE |= 0
		| PORTCON_PORTC_IE_C5_BITS_ENABLE
		;
	PORTCON_PORTC_IE &= ~(0
		| PORTCON_PORTC_IE_C0_MASK
		| PORTCON_PORTC_IE_C1_MASK
		| PORTCON_PORTC_IE_C2_MASK
		| PORTCON_PORTC_IE_C3_MASK
		| PORTCON_PORTC_IE_C4_MASK
		);

	PORTCON_PORTC_PU |= 0
		| PORTCON_PORTC_PU_C5_BITS_ENABLE
		;
	PORTCON_PORTC_PU &= ~(0
		| PORTCON_PORTC_PU_C0_MASK
		| PORTCON_PORTC_PU_C1_MASK
		| PORTCON_PORTC_PU_C2_MASK
		| PORTCON_PORTC_PU_C3_MASK
		| PORTCON_PORTC_PU_C4_MASK
		);

	PORTCON_PORTC_PD &= ~(0
		| PORTCON_PORTC_PD_C0_MASK
		| PORTCON_PORTC_PD_C1_MASK
		| PORTCON_PORTC_PD_C2_MASK
		| PORTCON_PORTC_PD_C3_MASK
		| PORTCON_PORTC_PD_C4_MASK
		| PORTCON_PORTC_PD_C5_MASK
		);

	PORTCON_PORTC_OD &= ~(0
		| PORTCON_PORTC_OD_C0_MASK
		| PORTCON_PORTC_OD_C1_MASK
		| PORTCON_PORTC_OD_C2_MASK
		| PORTCON_PORTC_OD_C3_MASK
		| PORTCON_PORTC_OD_C4_MASK
		);
	PORTCON_PORTC_OD |= 0
		| PORTCON_PORTC_OD_C5_BITS_ENABLE
		;
}

void BOARD_ADC_Init(void)
{
	ADC_Config_t Config;

	Config.CLK_SEL = SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2;
	Config.CH_SEL = ADC_CH4 | ADC_CH9;
	Config.AVG = SARADC_CFG_AVG_VALUE_8_SAMPLE;
	Config.CONT = SARADC_CFG_CONT_VALUE_SINGLE;
	Config.MEM_MODE = SARADC_CFG_MEM_MODE_VALUE_CHANNEL;
	Config.SMPL_CLK = SARADC_CFG_SMPL_CLK_VALUE_INTERNAL;
	Config.SMPL_WIN = SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE;
	Config.SMPL_SETUP = SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE;
	Config.ADC_TRIG = SARADC_CFG_ADC_TRIG_VALUE_CPU;
	Config.CALIB_KD_VALID = SARADC_CALIB_KD_VALID_VALUE_YES;
	Config.CALIB_OFFSET_VALID = SARADC_CALIB_OFFSET_VALID_VALUE_YES;
	Config.DMA_EN = SARADC_CFG_DMA_EN_VALUE_DISABLE;
	Config.IE_CHx_EOC = SARADC_IE_CHx_EOC_VALUE_NONE;
	Config.IE_FIFO_FULL = SARADC_IE_FIFO_FULL_VALUE_DISABLE;
	Config.IE_FIFO_HFULL = SARADC_IE_FIFO_HFULL_VALUE_DISABLE;
	ADC_Configure(&Config);
	ADC_Enable();
	ADC_SoftReset();
}

void BOARD_ADC_GetBatteryInfo(uint16_t *pCh4, uint16_t *pCh9)
{
	ADC_Start();

	while (!ADC_CheckEndOfConversion(ADC_CH9));
	*pCh4 = ADC_GetValue(ADC_CH4);
	*pCh9 = ADC_GetValue(ADC_CH9);
}

void BOARD_Init(void)
{
	BOARD_PORTCON_Init();
	BOARD_GPIO_Init();
	BOARD_ADC_Init();
	ST7565_Init();
	BK1080_Init(0, false);
	CRC_Init();
}