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For all ppc compilers, implement pg_atomic_fetch_add_ with inline asm.
This is more like how we handle s_lock.h and arch-x86.h. This does not materially affect code generation for gcc 7.2.0 or xlc 13.1.3. Reviewed by Tom Lane. Discussion: https://postgr.es/m/20190831071157.GA3251746@rfd.leadboat.com
This commit is contained in:
Noah Misch
parent
dd50f1a432
commit
e7ff59686e
40
configure
vendored
40
configure
vendored
@ -14593,6 +14593,46 @@ $as_echo "$pgac_cv_have_ppc_mutex_hint" >&6; }
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$as_echo "#define HAVE_PPC_LWARX_MUTEX_HINT 1" >>confdefs.h
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fi
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# Check if compiler accepts "i"(x) when __builtin_constant_p(x).
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether __builtin_constant_p(x) implies \"i\"(x) acceptance" >&5
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$as_echo_n "checking whether __builtin_constant_p(x) implies \"i\"(x) acceptance... " >&6; }
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if ${pgac_cv_have_i_constraint__builtin_constant_p+:} false; then :
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$as_echo_n "(cached) " >&6
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else
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cat confdefs.h - <<_ACEOF >conftest.$ac_ext
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/* end confdefs.h. */
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static inline int
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addi(int ra, int si)
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{
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int res = 0;
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if (__builtin_constant_p(si))
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__asm__ __volatile__(
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" addi %0,%1,%2\n" : "=r"(res) : "r"(ra), "i"(si));
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return res;
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}
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int test_adds(int x) { return addi(3, x) + addi(x, 5); }
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int
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main ()
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{
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;
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return 0;
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}
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_ACEOF
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if ac_fn_c_try_compile "$LINENO"; then :
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pgac_cv_have_i_constraint__builtin_constant_p=yes
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else
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pgac_cv_have_i_constraint__builtin_constant_p=no
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fi
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rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
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fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_have_i_constraint__builtin_constant_p" >&5
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$as_echo "$pgac_cv_have_i_constraint__builtin_constant_p" >&6; }
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if test x"$pgac_cv_have_i_constraint__builtin_constant_p" = xyes ; then
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$as_echo "#define HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P 1" >>confdefs.h
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fi
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;;
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esac
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20
configure.in
20
configure.in
@ -1539,6 +1539,26 @@ case $host_cpu in
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if test x"$pgac_cv_have_ppc_mutex_hint" = xyes ; then
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AC_DEFINE(HAVE_PPC_LWARX_MUTEX_HINT, 1, [Define to 1 if the assembler supports PPC's LWARX mutex hint bit.])
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fi
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# Check if compiler accepts "i"(x) when __builtin_constant_p(x).
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AC_CACHE_CHECK([whether __builtin_constant_p(x) implies "i"(x) acceptance],
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[pgac_cv_have_i_constraint__builtin_constant_p],
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[AC_COMPILE_IFELSE([AC_LANG_PROGRAM(
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[static inline int
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addi(int ra, int si)
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{
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int res = 0;
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if (__builtin_constant_p(si))
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__asm__ __volatile__(
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" addi %0,%1,%2\n" : "=r"(res) : "r"(ra), "i"(si));
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return res;
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}
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int test_adds(int x) { return addi(3, x) + addi(x, 5); }], [])],
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[pgac_cv_have_i_constraint__builtin_constant_p=yes],
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[pgac_cv_have_i_constraint__builtin_constant_p=no])])
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if test x"$pgac_cv_have_i_constraint__builtin_constant_p" = xyes ; then
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AC_DEFINE(HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P, 1,
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[Define to 1 if __builtin_constant_p(x) implies "i"(x) acceptance.])
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fi
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;;
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esac
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@ -329,6 +329,9 @@
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/* Define to 1 if you have isinf(). */
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#undef HAVE_ISINF
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/* Define to 1 if __builtin_constant_p(x) implies "i"(x) acceptance. */
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#undef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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/* Define to 1 if you have the <langinfo.h> header file. */
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#undef HAVE_LANGINFO_H
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@ -25,5 +25,103 @@
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#define pg_write_barrier_impl() __asm__ __volatile__ ("lwsync" : : : "memory")
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#endif
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#define PG_HAVE_ATOMIC_U32_SUPPORT
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typedef struct pg_atomic_uint32
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{
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volatile uint32 value;
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} pg_atomic_uint32;
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/* 64bit atomics are only supported in 64bit mode */
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#ifdef __64BIT__
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#define PG_HAVE_ATOMIC_U64_SUPPORT
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typedef struct pg_atomic_uint64
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{
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volatile uint64 value pg_attribute_aligned(8);
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} pg_atomic_uint64;
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#endif /* __64BIT__ */
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#define PG_HAVE_ATOMIC_FETCH_ADD_U32
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static inline uint32
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pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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{
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uint32 _t;
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uint32 res;
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/*
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* xlc has a no-longer-documented __fetch_and_add() intrinsic. In xlc
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* 12.01.0000.0000, it emits a leading "sync" and trailing "isync". In
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* xlc 13.01.0003.0004, it emits neither. Hence, using the intrinsic
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* would add redundant syncs on xlc 12.
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*/
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#ifdef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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if (__builtin_constant_p(add_) &&
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add_ <= PG_INT16_MAX && add_ >= PG_INT16_MIN)
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__asm__ __volatile__(
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" sync \n"
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" lwarx %1,0,%4 \n"
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" addi %0,%1,%3 \n"
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" stwcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to lwarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "i"(add_), "r"(&ptr->value)
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: "memory", "cc");
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else
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#endif
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__asm__ __volatile__(
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" sync \n"
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" lwarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stwcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to lwarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#ifdef PG_HAVE_ATOMIC_U64_SUPPORT
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#define PG_HAVE_ATOMIC_FETCH_ADD_U64
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static inline uint64
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pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
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{
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uint64 _t;
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uint64 res;
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/* Like u32, but s/lwarx/ldarx/; s/stwcx/stdcx/ */
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#ifdef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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if (__builtin_constant_p(add_) &&
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add_ <= PG_INT16_MAX && add_ >= PG_INT16_MIN)
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__asm__ __volatile__(
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" sync \n"
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" ldarx %1,0,%4 \n"
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" addi %0,%1,%3 \n"
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" stdcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to ldarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "i"(add_), "r"(&ptr->value)
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: "memory", "cc");
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else
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#endif
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__asm__ __volatile__(
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" sync \n"
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" ldarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stdcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to ldarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#endif /* PG_HAVE_ATOMIC_U64_SUPPORT */
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/* per architecture manual doubleword accesses have single copy atomicity */
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#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY
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@ -18,23 +18,6 @@
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#if defined(HAVE_ATOMICS)
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#define PG_HAVE_ATOMIC_U32_SUPPORT
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typedef struct pg_atomic_uint32
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{
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volatile uint32 value;
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} pg_atomic_uint32;
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/* 64bit atomics are only supported in 64bit mode */
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#ifdef __64BIT__
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#define PG_HAVE_ATOMIC_U64_SUPPORT
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typedef struct pg_atomic_uint64
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{
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volatile uint64 value pg_attribute_aligned(8);
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} pg_atomic_uint64;
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#endif /* __64BIT__ */
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#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
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static inline bool
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pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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@ -69,33 +52,6 @@ pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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return ret;
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}
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#define PG_HAVE_ATOMIC_FETCH_ADD_U32
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static inline uint32
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pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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{
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uint32 _t;
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uint32 res;
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/*
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* xlc has a no-longer-documented __fetch_and_add() intrinsic. In xlc
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* 12.01.0000.0000, it emits a leading "sync" and trailing "isync". In
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* xlc 13.01.0003.0004, it emits neither. Hence, using the intrinsic
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* would add redundant syncs on xlc 12.
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*/
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__asm__ __volatile__(
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" sync \n"
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" lwarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stwcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to lwarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#ifdef PG_HAVE_ATOMIC_U64_SUPPORT
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#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64
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@ -115,28 +71,6 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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return ret;
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}
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#define PG_HAVE_ATOMIC_FETCH_ADD_U64
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static inline uint64
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pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
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{
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uint64 _t;
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uint64 res;
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/* Like u32, but s/lwarx/ldarx/; s/stwcx/stdcx/ */
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__asm__ __volatile__(
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" sync \n"
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" ldarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stdcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to ldarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#endif /* PG_HAVE_ATOMIC_U64_SUPPORT */
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#endif /* defined(HAVE_ATOMICS) */
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