Yangyu Chen f6ce48f5b8 chacha-riscv64-v-zbb.pl: better format ... This patch merged the `add` and `xor` part of chacha_sub_round, which are same in RISC-V Vector only and Zvkb implementation. There is no change to the generated ASM code except for the indent. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Reviewed-by: Paul Dale <ppzgs1@gmail.com> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/24069)		2024-05-08 11:10:45 +02:00
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chacha-armv4.pl	Copyright year updates	2023-09-07 09:59:15 +01:00
chacha-armv8-sve.pl	Copyright year updates	2023-09-07 09:59:15 +01:00
chacha-armv8.pl	Update copyright year	2022-05-03 13:34:51 +01:00
chacha-c64xplus.pl	Update copyright year	2020-04-23 13:55:52 +01:00
chacha-ia64.pl	Fix ChaCha assembly code on 32-bit HPUX itanium systems	2023-08-09 12:22:20 +02:00
chacha-loongarch64.pl	Copyright year updates	2024-04-09 13:43:26 +02:00
chacha-ppc.pl	Update copyright year	2020-04-23 13:55:52 +01:00
chacha-riscv64-v-zbb.pl	chacha-riscv64-v-zbb.pl: better format	2024-05-08 11:10:45 +02:00
chacha-s390x.pl	s390x assembly pack: perlasm module update	2019-11-05 10:05:27 +01:00
chacha-x86_64.pl	Unable to run asm code on OpenBSD (amd64)	2024-04-17 09:38:06 +02:00
chacha-x86.pl	Ignore vendor name in Clang version number.	2020-08-27 20:27:26 -07:00
chachap10-ppc.pl	Remove repetitive words	2024-04-16 09:07:05 +02:00