Yangyu Chen f6ce48f5b8 chacha-riscv64-v-zbb.pl: better format ... This patch merged the `add` and `xor` part of chacha_sub_round, which are same in RISC-V Vector only and Zvkb implementation. There is no change to the generated ASM code except for the indent. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Reviewed-by: Paul Dale <ppzgs1@gmail.com> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/24069)		2024-05-08 11:10:45 +02:00
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asm	chacha-riscv64-v-zbb.pl: better format	2024-05-08 11:10:45 +02:00
build.info	riscv: Provide a vector only implementation of Chacha20 cipher	2024-05-08 11:10:45 +02:00
chacha_enc.c	riscv: Provide a vector implementation of CHACHA20 cipher.	2023-10-26 15:55:50 +01:00
chacha_ppc.c
chacha_riscv.c	riscv: Provide a vector only implementation of Chacha20 cipher	2024-05-08 11:10:45 +02:00