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openssl/crypto/chacha/asm
Xi Ruoyao b46de72c26 LoongArch64 assembly pack: Fix ChaCha20 ABI breakage
The [LP64D ABI][1] requires the floating-point registers f24-f31
(aka fs0-fs7) callee-saved.  The low 64 bits of a LSX/LASX vector
register aliases with the corresponding FPR, so we must save and restore
the callee-saved FPR when we writes into the corresponding vector
register.

This ABI breakage can be easily demonstrated by injecting the use of a
saved FPR into the test in bio_enc_test.c:

    static int test_bio_enc_chacha20(int idx)
    {
        register double fs7 asm("f31") = 114.514;
        asm("#optimize barrier":"+f"(fs7));
        return do_test_bio_cipher(EVP_chacha20(), idx) && fs7 == 114.514;
    }

So fix it.  To make the logic simpler, jump into the scalar
implementation earlier when LSX and LASX are not enumerated in AT_HWCAP,
or the input is too short.

[1]: https://github.com/loongson/la-abi-specs/blob/v2.20/lapcs.adoc#floating-point-registers

Reviewed-by: Neil Horman <nhorman@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/22817)
2023-12-19 14:12:24 +01:00
..
chacha-armv4.pl Copyright year updates 2023-09-07 09:59:15 +01:00
chacha-armv8-sve.pl Copyright year updates 2023-09-07 09:59:15 +01:00
chacha-armv8.pl Update copyright year 2022-05-03 13:34:51 +01:00
chacha-c64xplus.pl
chacha-ia64.pl Fix ChaCha assembly code on 32-bit HPUX itanium systems 2023-08-09 12:22:20 +02:00
chacha-loongarch64.pl LoongArch64 assembly pack: Fix ChaCha20 ABI breakage 2023-12-19 14:12:24 +01:00
chacha-ppc.pl
chacha-riscv64-zvkb.pl riscv: Provide a vector implementation of CHACHA20 cipher. 2023-10-26 15:55:50 +01:00
chacha-s390x.pl
chacha-x86_64.pl
chacha-x86.pl
chachap10-ppc.pl Update copyright year 2022-05-03 13:34:51 +01:00