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f20ee1f490
The upcoming RISC-V vector crypto extensions feature a Zvksh extension, that provides SM3-specific istructions. This patch provides an implementation that utilizes this extension if available. Tested on QEMU and no regressions observed. Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
28 lines
735 B
Plaintext
28 lines
735 B
Plaintext
LIBS=../../libcrypto
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IF[{- !$disabled{sm3} -}]
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IF[{- !$disabled{asm} -}]
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$SM3ASM_aarch64=sm3-armv8.S
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$SM3DEF_aarch64=OPENSSL_SM3_ASM
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$SM3ASM_riscv64=sm3_riscv.c sm3-riscv64-zvksh.S
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$SM3DEF_riscv64=OPENSSL_SM3_ASM
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# Now that we have defined all the arch specific variables, use the
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# appropriate ones, and define the appropriate macros
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IF[$SM3ASM_{- $target{asm_arch} -}]
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$SM3ASM=$SM3ASM_{- $target{asm_arch} -}
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$SM3DEF=$SM3DEF_{- $target{asm_arch} -}
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ENDIF
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ENDIF
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SOURCE[../../libcrypto]=sm3.c legacy_sm3.c $SM3ASM
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DEFINE[../../libcrypto]=$SM3DEF
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GENERATE[sm3-armv8.S]=asm/sm3-armv8.pl
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INCLUDE[sm3-armv8.o]=..
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GENERATE[sm3-riscv64-zvksh.S]=asm/sm3-riscv64-zvksh.pl
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ENDIF
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