Christoph Müllner cdea67193d riscv: Add basic vector extension support ... The RISC-V vector extension comes with an implementation-defined number of bits per vector register (VLEN), which can be read out at run-time using the CSR 'vlenb' (which returns VLEN/8) followed by a multiplication by 8 (to convert bytes to bits). This patch introduces a RISC-V capability 'V' to specify the availability of the vector extension. If this extension is found at run-time, then we read out VLEN as described above and cache it. Caching ensures that we only read the CSR once at startup. This is necessary because reading out CSR can be expensive (e.g. if CSR readout is implemented using trap-and-emulate). Follow-up patches can make use of VLEN and chose the best strategy based on the available length of the vector registers. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)		2023-10-26 15:55:49 +01:00
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crypto	riscv: Add basic vector extension support	2023-10-26 15:55:49 +01:00
internal	Round up nano secs when converting OSSL_TIME to struct timeval	2023-10-20 16:33:40 +01:00
openssl	Avoid using gets as an argument name in a prototype	2023-10-25 09:53:46 +01:00