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26217510d2
ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are affected by silicon errata #1742098 [0] and #1655431 [1], respectively, where the second instruction of a AES instruction pair may execute twice if an interrupt is taken right after the first instruction consumes an input register of which a single 32-bit lane has been updated the last time it was modified. This is not such a rare occurrence as it may seem: in counter mode, only the least significant 32-bit word is incremented in the absence of a carry, which makes our counter mode implementation susceptible to these errata. So let's shuffle the counter assignments around a bit so that the most recent updates when the AES instruction pair executes are 128-bit wide. [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice [1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Paul Dale <paul.dale@oracle.com> Reviewed-by: Tomas Mraz <tmraz@fedoraproject.org> (Merged from https://github.com/openssl/openssl/pull/13504) |
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| .. | ||
| aes-586.pl | ||
| aes-armv4.pl | ||
| aes-c64xplus.pl | ||
| aes-ia64.S | ||
| aes-mips.pl | ||
| aes-parisc.pl | ||
| aes-ppc.pl | ||
| aes-s390x.pl | ||
| aes-sparcv9.pl | ||
| aes-x86_64.pl | ||
| aesfx-sparcv9.pl | ||
| aesni-mb-x86_64.pl | ||
| aesni-sha1-x86_64.pl | ||
| aesni-sha256-x86_64.pl | ||
| aesni-x86_64.pl | ||
| aesni-x86.pl | ||
| aesp8-ppc.pl | ||
| aest4-sparcv9.pl | ||
| aesv8-armx.pl | ||
| bsaes-armv7.pl | ||
| bsaes-x86_64.pl | ||
| vpaes-armv8.pl | ||
| vpaes-ppc.pl | ||
| vpaes-x86_64.pl | ||
| vpaes-x86.pl | ||