mirror of
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a5d250e57e
We received analytics that devices of the device family Oppo A37x are crashing with SIGILL when trying to load libcrypto.so. These crashes were fixed by using the system-supplied getauxval function. Reviewed-by: Kurt Roeckx <kurt@roeckx.be> Reviewed-by: Tim Hudson <tjh@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/11257)
272 lines
7.1 KiB
C
272 lines
7.1 KiB
C
/*
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* Copyright 2011-2021 The OpenSSL Project Authors. All Rights Reserved.
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*
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* Licensed under the Apache License 2.0 (the "License"). You may not use
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* this file except in compliance with the License. You can obtain a copy
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* in the file LICENSE in the source distribution or at
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* https://www.openssl.org/source/license.html
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <setjmp.h>
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#include <signal.h>
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#include <openssl/crypto.h>
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#ifdef __APPLE__
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#include <sys/sysctl.h>
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#endif
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#include "internal/cryptlib.h"
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#include "arm_arch.h"
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unsigned int OPENSSL_armcap_P = 0;
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unsigned int OPENSSL_arm_midr = 0;
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unsigned int OPENSSL_armv8_rsa_neonized = 0;
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#if __ARM_MAX_ARCH__<7
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void OPENSSL_cpuid_setup(void)
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{
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}
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uint32_t OPENSSL_rdtsc(void)
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{
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return 0;
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}
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#else
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static sigset_t all_masked;
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static sigjmp_buf ill_jmp;
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static void ill_handler(int sig)
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{
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siglongjmp(ill_jmp, sig);
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}
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/*
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* Following subroutines could have been inlined, but it's not all
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* ARM compilers support inline assembler...
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*/
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void _armv7_neon_probe(void);
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void _armv8_aes_probe(void);
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void _armv8_sha1_probe(void);
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void _armv8_sha256_probe(void);
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void _armv8_pmull_probe(void);
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# ifdef __aarch64__
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void _armv8_sha512_probe(void);
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unsigned int _armv8_cpuid_probe(void);
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# endif
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uint32_t _armv7_tick(void);
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uint32_t OPENSSL_rdtsc(void)
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{
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if (OPENSSL_armcap_P & ARMV7_TICK)
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return _armv7_tick();
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else
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return 0;
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}
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# if defined(__GNUC__) && __GNUC__>=2
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void OPENSSL_cpuid_setup(void) __attribute__ ((constructor));
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# endif
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# if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
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# if __GLIBC_PREREQ(2, 16)
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# include <sys/auxv.h>
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# define OSSL_IMPLEMENT_GETAUXVAL
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# endif
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# endif
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# if defined(__FreeBSD__)
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# include <sys/param.h>
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# if __FreeBSD_version >= 1200000
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# include <sys/auxv.h>
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# define OSSL_IMPLEMENT_GETAUXVAL
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static unsigned long getauxval(unsigned long key)
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{
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unsigned long val = 0ul;
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if (elf_aux_info((int)key, &val, sizeof(val)) != 0)
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return 0ul;
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return val;
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}
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# endif
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# endif
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/*
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* Android: according to https://developer.android.com/ndk/guides/cpu-features,
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* getauxval is supported starting with API level 18
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*/
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# if defined(__ANDROID__) && defined(__ANDROID_API__) && __ANDROID_API__ >= 18
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# include <sys/auxv.h>
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# define OSSL_IMPLEMENT_GETAUXVAL
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# endif
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/*
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* ARM puts the feature bits for Crypto Extensions in AT_HWCAP2, whereas
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* AArch64 used AT_HWCAP.
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*/
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# if defined(__arm__) || defined (__arm)
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# define HWCAP 16
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/* AT_HWCAP */
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# define HWCAP_NEON (1 << 12)
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# define HWCAP_CE 26
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/* AT_HWCAP2 */
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# define HWCAP_CE_AES (1 << 0)
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# define HWCAP_CE_PMULL (1 << 1)
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# define HWCAP_CE_SHA1 (1 << 2)
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# define HWCAP_CE_SHA256 (1 << 3)
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# elif defined(__aarch64__)
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# define HWCAP 16
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/* AT_HWCAP */
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# define HWCAP_NEON (1 << 1)
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# define HWCAP_CE HWCAP
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# define HWCAP_CE_AES (1 << 3)
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# define HWCAP_CE_PMULL (1 << 4)
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# define HWCAP_CE_SHA1 (1 << 5)
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# define HWCAP_CE_SHA256 (1 << 6)
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# define HWCAP_CPUID (1 << 11)
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# define HWCAP_CE_SHA512 (1 << 21)
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# endif
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void OPENSSL_cpuid_setup(void)
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{
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const char *e;
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struct sigaction ill_oact, ill_act;
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sigset_t oset;
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static int trigger = 0;
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if (trigger)
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return;
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trigger = 1;
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OPENSSL_armcap_P = 0;
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if ((e = getenv("OPENSSL_armcap"))) {
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OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
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return;
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}
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# if defined(__APPLE__)
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# if !defined(__aarch64__)
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/*
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* Capability probing by catching SIGILL appears to be problematic
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* on iOS. But since Apple universe is "monocultural", it's actually
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* possible to simply set pre-defined processor capability mask.
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*/
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if (1) {
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OPENSSL_armcap_P = ARMV7_NEON;
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return;
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}
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/*
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* One could do same even for __aarch64__ iOS builds. It's not done
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* exclusively for reasons of keeping code unified across platforms.
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* Unified code works because it never triggers SIGILL on Apple
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* devices...
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*/
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# else
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{
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unsigned int sha512;
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size_t len = sizeof(sha512);
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if (sysctlbyname("hw.optional.armv8_2_sha512", &sha512, &len, NULL, 0) == 0 && sha512 == 1)
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OPENSSL_armcap_P |= ARMV8_SHA512;
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}
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# endif
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# endif
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# ifdef OSSL_IMPLEMENT_GETAUXVAL
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if (getauxval(HWCAP) & HWCAP_NEON) {
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unsigned long hwcap = getauxval(HWCAP_CE);
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OPENSSL_armcap_P |= ARMV7_NEON;
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if (hwcap & HWCAP_CE_AES)
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OPENSSL_armcap_P |= ARMV8_AES;
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if (hwcap & HWCAP_CE_PMULL)
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OPENSSL_armcap_P |= ARMV8_PMULL;
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if (hwcap & HWCAP_CE_SHA1)
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OPENSSL_armcap_P |= ARMV8_SHA1;
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if (hwcap & HWCAP_CE_SHA256)
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OPENSSL_armcap_P |= ARMV8_SHA256;
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# ifdef __aarch64__
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if (hwcap & HWCAP_CE_SHA512)
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OPENSSL_armcap_P |= ARMV8_SHA512;
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if (hwcap & HWCAP_CPUID)
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OPENSSL_armcap_P |= ARMV8_CPUID;
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# endif
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}
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# endif
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sigfillset(&all_masked);
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sigdelset(&all_masked, SIGILL);
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sigdelset(&all_masked, SIGTRAP);
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sigdelset(&all_masked, SIGFPE);
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sigdelset(&all_masked, SIGBUS);
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sigdelset(&all_masked, SIGSEGV);
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memset(&ill_act, 0, sizeof(ill_act));
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ill_act.sa_handler = ill_handler;
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ill_act.sa_mask = all_masked;
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sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
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sigaction(SIGILL, &ill_act, &ill_oact);
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/* If we used getauxval, we already have all the values */
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# ifndef OSSL_IMPLEMENT_GETAUXVAL
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if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv7_neon_probe();
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OPENSSL_armcap_P |= ARMV7_NEON;
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if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv8_pmull_probe();
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OPENSSL_armcap_P |= ARMV8_PMULL | ARMV8_AES;
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} else if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv8_aes_probe();
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OPENSSL_armcap_P |= ARMV8_AES;
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}
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if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv8_sha1_probe();
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OPENSSL_armcap_P |= ARMV8_SHA1;
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}
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if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv8_sha256_probe();
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OPENSSL_armcap_P |= ARMV8_SHA256;
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}
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# if defined(__aarch64__) && !defined(__APPLE__)
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if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv8_sha512_probe();
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OPENSSL_armcap_P |= ARMV8_SHA512;
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}
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# endif
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}
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# endif
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/* Things that getauxval didn't tell us */
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if (sigsetjmp(ill_jmp, 1) == 0) {
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_armv7_tick();
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OPENSSL_armcap_P |= ARMV7_TICK;
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}
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sigaction(SIGILL, &ill_oact, NULL);
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sigprocmask(SIG_SETMASK, &oset, NULL);
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# ifdef __aarch64__
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if (OPENSSL_armcap_P & ARMV8_CPUID)
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OPENSSL_arm_midr = _armv8_cpuid_probe();
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if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) ||
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MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)) &&
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(OPENSSL_armcap_P & ARMV7_NEON)) {
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OPENSSL_armv8_rsa_neonized = 1;
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}
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# endif
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}
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#endif
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