Jerry Shih 3e56c0efe7 riscv: Provide vector crypto implementation of AES-128/256-XTS mode. ... To accelerate the performance of the AES-XTS mode, in this patch, we have the specialized multi-block implementation for AES-128-XTS and AES-256-XTS. Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)		2023-10-26 15:55:50 +01:00
..
asm	riscv: Provide vector crypto implementation of AES-128/256-XTS mode.	2023-10-26 15:55:50 +01:00
aes_cbc.c
aes_cfb.c
aes_core.c	Update copyright year	2022-05-03 13:34:51 +01:00
aes_ecb.c
aes_ige.c
aes_local.h	Update copyright year	2021-06-17 13:24:59 +01:00
aes_misc.c
aes_ofb.c
aes_wrap.c
aes_x86core.c	fix some code with obvious wrong coding style	2021-10-28 13:10:46 +10:00
build.info	riscv: Provide vector crypto implementation of AES-128/256-XTS mode.	2023-10-26 15:55:50 +01:00