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3645eb0be2
c8ddeb7e64/doc/vector/riscv-crypto-vector-zvkb.adoc
Create `RISCV_HAS_ZVKB()` macro.
Use zvkb for SM4 instead of zvbb.
Use zvkb for ghash instead of zvbb.
We could just use the zvbb's subset `zvkb` for flexibility.
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Hugo Landau <hlandau@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/21923)
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*
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* Copyright 2022-2023 The OpenSSL Project Authors. All Rights Reserved.
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*
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* Licensed under the Apache License 2.0 (the "License"). You may not use
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* this file except in compliance with the License. You can obtain a copy
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* in the file LICENSE in the source distribution or at
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* https://www.openssl.org/source/license.html
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*/
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#ifndef OSSL_CRYPTO_RISCV_ARCH_H
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# define OSSL_CRYPTO_RISCV_ARCH_H
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# include <ctype.h>
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# include <stdint.h>
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# define RISCV_DEFINE_CAP(NAME, INDEX, BIT_INDEX) +1
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extern uint32_t OPENSSL_riscvcap_P[ ((
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# include "riscv_arch.def"
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) + sizeof(uint32_t) - 1) / sizeof(uint32_t) ];
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# ifdef OPENSSL_RISCVCAP_IMPL
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# define RISCV_DEFINE_CAP(NAME, INDEX, BIT_INDEX) +1
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uint32_t OPENSSL_riscvcap_P[ ((
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# include "riscv_arch.def"
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) + sizeof(uint32_t) - 1) / sizeof(uint32_t) ];
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# endif
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# define RISCV_DEFINE_CAP(NAME, INDEX, BIT_INDEX) \
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static inline int RISCV_HAS_##NAME(void) \
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{ \
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return (OPENSSL_riscvcap_P[INDEX] & (1 << BIT_INDEX)) != 0; \
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}
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# include "riscv_arch.def"
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struct RISCV_capability_s {
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const char *name;
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size_t index;
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size_t bit_offset;
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};
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# define RISCV_DEFINE_CAP(NAME, INDEX, BIT_INDEX) +1
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extern const struct RISCV_capability_s RISCV_capabilities[
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# include "riscv_arch.def"
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];
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# ifdef OPENSSL_RISCVCAP_IMPL
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# define RISCV_DEFINE_CAP(NAME, INDEX, BIT_INDEX) \
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{ #NAME, INDEX, BIT_INDEX },
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const struct RISCV_capability_s RISCV_capabilities[] = {
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# include "riscv_arch.def"
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};
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# endif
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# define RISCV_DEFINE_CAP(NAME, INDEX, BIT_INDEX) +1
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static const size_t kRISCVNumCaps =
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# include "riscv_arch.def"
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;
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/* Extension combination tests. */
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#define RISCV_HAS_ZBB_AND_ZBC() (RISCV_HAS_ZBB() && RISCV_HAS_ZBC())
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#define RISCV_HAS_ZBKB_AND_ZKND_AND_ZKNE() (RISCV_HAS_ZBKB() && RISCV_HAS_ZKND() && RISCV_HAS_ZKNE())
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#define RISCV_HAS_ZKND_AND_ZKNE() (RISCV_HAS_ZKND() && RISCV_HAS_ZKNE())
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/*
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* The ZVBB is the superset of ZVKB extension. We use macro here to replace the
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* `RISCV_HAS_ZVKB()` with `RISCV_HAS_ZVBB() || RISCV_HAS_ZVKB()`.
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*/
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#define RISCV_HAS_ZVKB() (RISCV_HAS_ZVBB() || RISCV_HAS_ZVKB())
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#define RISCV_HAS_ZVKB_AND_ZVKNHA() (RISCV_HAS_ZVKB() && RISCV_HAS_ZVKNHA())
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#define RISCV_HAS_ZVKB_AND_ZVKNHB() (RISCV_HAS_ZVKB() && RISCV_HAS_ZVKNHB())
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#define RISCV_HAS_ZVKB_AND_ZVKSED() (RISCV_HAS_ZVKB() && RISCV_HAS_ZVKSED())
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#define RISCV_HAS_ZVKB_AND_ZVKSH() (RISCV_HAS_ZVKB() && RISCV_HAS_ZVKSH())
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/*
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* Get the size of a vector register in bits (VLEN).
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* If RISCV_HAS_V() is false, then this returns 0.
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*/
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size_t riscv_vlen(void);
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#endif
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