mirror of
https://github.com/openssl/openssl.git
synced 2024-12-15 06:01:37 +08:00
54b4053130
Reviewed-by: Richard Levitte <levitte@openssl.org> (Merged from https://github.com/openssl/openssl/pull/16176)
437 lines
9.3 KiB
Raku
437 lines
9.3 KiB
Raku
#! /usr/bin/env perl
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# Copyright 2007-2021 The OpenSSL Project Authors. All Rights Reserved.
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#
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# Licensed under the Apache License 2.0 (the "License"). You may not use
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# this file except in compliance with the License. You can obtain a copy
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# in the file LICENSE in the source distribution or at
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# https://www.openssl.org/source/license.html
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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#
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# Hardware SPARC T4 support by David S. Miller
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# ====================================================================
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# Performance improvement is not really impressive on pre-T1 CPU: +8%
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# over Sun C and +25% over gcc [3.3]. While on T1, a.k.a. Niagara, it
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# turned to be 40% faster than 64-bit code generated by Sun C 5.8 and
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# >2x than 64-bit code generated by gcc 3.4. And there is a gimmick.
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# X[16] vector is packed to 8 64-bit registers and as result nothing
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# is spilled on stack. In addition input data is loaded in compact
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# instruction sequence, thus minimizing the window when the code is
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# subject to [inter-thread] cache-thrashing hazard. The goal is to
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# ensure scalability on UltraSPARC T1, or rather to avoid decay when
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# amount of active threads exceeds the number of physical cores.
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# SPARC T4 SHA1 hardware achieves 3.72 cycles per byte, which is 3.1x
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# faster than software. Multi-process benchmark saturates at 11x
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# single-process result on 8-core processor, or ~9GBps per 2.85GHz
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# socket.
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$output=pop and open STDOUT,">$output";
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@X=("%o0","%o1","%o2","%o3","%o4","%o5","%g1","%o7");
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$rot1m="%g2";
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$tmp64="%g3";
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$Xi="%g4";
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$A="%l0";
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$B="%l1";
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$C="%l2";
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$D="%l3";
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$E="%l4";
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@V=($A,$B,$C,$D,$E);
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$K_00_19="%l5";
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$K_20_39="%l6";
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$K_40_59="%l7";
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$K_60_79="%g5";
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@K=($K_00_19,$K_20_39,$K_40_59,$K_60_79);
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$ctx="%i0";
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$inp="%i1";
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$len="%i2";
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$tmp0="%i3";
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$tmp1="%i4";
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$tmp2="%i5";
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sub BODY_00_15 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $xi=($i&1)?@X[($i/2)%8]:$Xi;
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$code.=<<___;
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sll $a,5,$tmp0 !! $i
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add @K[$i/20],$e,$e
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srl $a,27,$tmp1
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add $tmp0,$e,$e
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and $c,$b,$tmp0
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add $tmp1,$e,$e
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sll $b,30,$tmp2
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andn $d,$b,$tmp1
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srl $b,2,$b
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or $tmp1,$tmp0,$tmp1
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or $tmp2,$b,$b
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add $xi,$e,$e
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___
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if ($i&1 && $i<15) {
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$code.=
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" srlx @X[(($i+1)/2)%8],32,$Xi\n";
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}
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$code.=<<___;
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add $tmp1,$e,$e
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___
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}
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sub Xupdate {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i/2;
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if ($i&1) {
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$code.=<<___;
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sll $a,5,$tmp0 !! $i
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add @K[$i/20],$e,$e
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srl $a,27,$tmp1
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___
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} else {
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$code.=<<___;
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sllx @X[($j+6)%8],32,$Xi ! Xupdate($i)
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xor @X[($j+1)%8],@X[$j%8],@X[$j%8]
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srlx @X[($j+7)%8],32,$tmp1
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xor @X[($j+4)%8],@X[$j%8],@X[$j%8]
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sll $a,5,$tmp0 !! $i
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or $tmp1,$Xi,$Xi
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add @K[$i/20],$e,$e !!
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xor $Xi,@X[$j%8],@X[$j%8]
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srlx @X[$j%8],31,$Xi
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add @X[$j%8],@X[$j%8],@X[$j%8]
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and $Xi,$rot1m,$Xi
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andn @X[$j%8],$rot1m,@X[$j%8]
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srl $a,27,$tmp1 !!
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or $Xi,@X[$j%8],@X[$j%8]
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___
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}
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}
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sub BODY_16_19 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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&Xupdate(@_);
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if ($i&1) {
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$xi=@X[($i/2)%8];
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} else {
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$xi=$Xi;
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$code.="\tsrlx @X[($i/2)%8],32,$xi\n";
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}
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$code.=<<___;
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add $tmp0,$e,$e !!
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and $c,$b,$tmp0
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add $tmp1,$e,$e
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sll $b,30,$tmp2
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add $xi,$e,$e
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andn $d,$b,$tmp1
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srl $b,2,$b
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or $tmp1,$tmp0,$tmp1
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or $tmp2,$b,$b
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add $tmp1,$e,$e
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___
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}
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sub BODY_20_39 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $xi;
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&Xupdate(@_);
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if ($i&1) {
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$xi=@X[($i/2)%8];
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} else {
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$xi=$Xi;
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$code.="\tsrlx @X[($i/2)%8],32,$xi\n";
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}
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$code.=<<___;
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add $tmp0,$e,$e !!
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xor $c,$b,$tmp0
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add $tmp1,$e,$e
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sll $b,30,$tmp2
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xor $d,$tmp0,$tmp1
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srl $b,2,$b
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add $tmp1,$e,$e
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or $tmp2,$b,$b
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add $xi,$e,$e
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___
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}
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sub BODY_40_59 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $xi;
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&Xupdate(@_);
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if ($i&1) {
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$xi=@X[($i/2)%8];
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} else {
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$xi=$Xi;
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$code.="\tsrlx @X[($i/2)%8],32,$xi\n";
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}
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$code.=<<___;
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add $tmp0,$e,$e !!
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and $c,$b,$tmp0
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add $tmp1,$e,$e
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sll $b,30,$tmp2
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or $c,$b,$tmp1
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srl $b,2,$b
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and $d,$tmp1,$tmp1
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add $xi,$e,$e
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or $tmp1,$tmp0,$tmp1
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or $tmp2,$b,$b
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add $tmp1,$e,$e
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___
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}
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$code.=<<___;
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#ifndef __ASSEMBLER__
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# define __ASSEMBLER__ 1
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#endif
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#include "crypto/sparc_arch.h"
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#ifdef __arch64__
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.register %g2,#scratch
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.register %g3,#scratch
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#endif
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.section ".text",#alloc,#execinstr
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#ifdef __PIC__
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SPARC_PIC_THUNK(%g1)
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#endif
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.align 32
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.globl sha1_block_data_order
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sha1_block_data_order:
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SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)
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ld [%g1+4],%g1 ! OPENSSL_sparcv9cap_P[1]
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andcc %g1, CFR_SHA1, %g0
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be .Lsoftware
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nop
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ld [%o0 + 0x00], %f0 ! load context
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ld [%o0 + 0x04], %f1
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ld [%o0 + 0x08], %f2
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andcc %o1, 0x7, %g0
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ld [%o0 + 0x0c], %f3
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bne,pn %icc, .Lhwunaligned
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ld [%o0 + 0x10], %f4
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.Lhw_loop:
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ldd [%o1 + 0x00], %f8
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ldd [%o1 + 0x08], %f10
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ldd [%o1 + 0x10], %f12
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ldd [%o1 + 0x18], %f14
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ldd [%o1 + 0x20], %f16
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ldd [%o1 + 0x28], %f18
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ldd [%o1 + 0x30], %f20
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subcc %o2, 1, %o2 ! done yet?
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ldd [%o1 + 0x38], %f22
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add %o1, 0x40, %o1
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prefetch [%o1 + 63], 20
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.word 0x81b02820 ! SHA1
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bne,pt SIZE_T_CC, .Lhw_loop
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nop
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.Lhwfinish:
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st %f0, [%o0 + 0x00] ! store context
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st %f1, [%o0 + 0x04]
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st %f2, [%o0 + 0x08]
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st %f3, [%o0 + 0x0c]
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retl
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st %f4, [%o0 + 0x10]
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.align 8
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.Lhwunaligned:
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alignaddr %o1, %g0, %o1
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ldd [%o1 + 0x00], %f10
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.Lhwunaligned_loop:
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ldd [%o1 + 0x08], %f12
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ldd [%o1 + 0x10], %f14
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ldd [%o1 + 0x18], %f16
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ldd [%o1 + 0x20], %f18
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ldd [%o1 + 0x28], %f20
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ldd [%o1 + 0x30], %f22
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ldd [%o1 + 0x38], %f24
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subcc %o2, 1, %o2 ! done yet?
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ldd [%o1 + 0x40], %f26
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add %o1, 0x40, %o1
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prefetch [%o1 + 63], 20
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faligndata %f10, %f12, %f8
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faligndata %f12, %f14, %f10
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faligndata %f14, %f16, %f12
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faligndata %f16, %f18, %f14
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faligndata %f18, %f20, %f16
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faligndata %f20, %f22, %f18
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faligndata %f22, %f24, %f20
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faligndata %f24, %f26, %f22
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.word 0x81b02820 ! SHA1
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bne,pt SIZE_T_CC, .Lhwunaligned_loop
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for %f26, %f26, %f10 ! %f10=%f26
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ba .Lhwfinish
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nop
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.align 16
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.Lsoftware:
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save %sp,-STACK_FRAME,%sp
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sllx $len,6,$len
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add $inp,$len,$len
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or %g0,1,$rot1m
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sllx $rot1m,32,$rot1m
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or $rot1m,1,$rot1m
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ld [$ctx+0],$A
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ld [$ctx+4],$B
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ld [$ctx+8],$C
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ld [$ctx+12],$D
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ld [$ctx+16],$E
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andn $inp,7,$tmp0
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sethi %hi(0x5a827999),$K_00_19
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or $K_00_19,%lo(0x5a827999),$K_00_19
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sethi %hi(0x6ed9eba1),$K_20_39
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or $K_20_39,%lo(0x6ed9eba1),$K_20_39
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sethi %hi(0x8f1bbcdc),$K_40_59
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or $K_40_59,%lo(0x8f1bbcdc),$K_40_59
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sethi %hi(0xca62c1d6),$K_60_79
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or $K_60_79,%lo(0xca62c1d6),$K_60_79
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.Lloop:
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ldx [$tmp0+0],@X[0]
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ldx [$tmp0+16],@X[2]
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ldx [$tmp0+32],@X[4]
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ldx [$tmp0+48],@X[6]
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and $inp,7,$tmp1
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ldx [$tmp0+8],@X[1]
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sll $tmp1,3,$tmp1
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ldx [$tmp0+24],@X[3]
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subcc %g0,$tmp1,$tmp2 ! should be 64-$tmp1, but -$tmp1 works too
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ldx [$tmp0+40],@X[5]
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bz,pt %icc,.Laligned
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ldx [$tmp0+56],@X[7]
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sllx @X[0],$tmp1,@X[0]
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ldx [$tmp0+64],$tmp64
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___
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for($i=0;$i<7;$i++)
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{ $code.=<<___;
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srlx @X[$i+1],$tmp2,$Xi
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sllx @X[$i+1],$tmp1,@X[$i+1]
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or $Xi,@X[$i],@X[$i]
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___
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}
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$code.=<<___;
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srlx $tmp64,$tmp2,$tmp64
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or $tmp64,@X[7],@X[7]
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.Laligned:
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srlx @X[0],32,$Xi
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___
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for ($i=0;$i<16;$i++) { &BODY_00_15($i,@V); unshift(@V,pop(@V)); }
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for (;$i<20;$i++) { &BODY_16_19($i,@V); unshift(@V,pop(@V)); }
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for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
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for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
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for (;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
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$code.=<<___;
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ld [$ctx+0],@X[0]
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ld [$ctx+4],@X[1]
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ld [$ctx+8],@X[2]
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ld [$ctx+12],@X[3]
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add $inp,64,$inp
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ld [$ctx+16],@X[4]
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cmp $inp,$len
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add $A,@X[0],$A
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st $A,[$ctx+0]
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add $B,@X[1],$B
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st $B,[$ctx+4]
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add $C,@X[2],$C
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st $C,[$ctx+8]
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add $D,@X[3],$D
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st $D,[$ctx+12]
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add $E,@X[4],$E
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st $E,[$ctx+16]
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bne SIZE_T_CC,.Lloop
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andn $inp,7,$tmp0
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ret
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restore
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.type sha1_block_data_order,#function
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.size sha1_block_data_order,(.-sha1_block_data_order)
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.asciz "SHA1 block transform for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>"
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.align 4
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___
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# Purpose of these subroutines is to explicitly encode VIS instructions,
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# so that one can compile the module without having to specify VIS
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# extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
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# Idea is to reserve for option to produce "universal" binary and let
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# programmer detect if current CPU is VIS capable at run-time.
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sub unvis {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my $ref,$opf;
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my %visopf = ( "faligndata" => 0x048,
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"for" => 0x07c );
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$ref = "$mnemonic\t$rs1,$rs2,$rd";
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if ($opf=$visopf{$mnemonic}) {
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foreach ($rs1,$rs2,$rd) {
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return $ref if (!/%f([0-9]{1,2})/);
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$_=$1;
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if ($1>=32) {
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return $ref if ($1&1);
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# re-encode for upper double register addressing
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$_=($1|$1>>5)&31;
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}
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
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$ref;
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} else {
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return $ref;
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}
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}
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sub unalignaddr {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
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my $ref="$mnemonic\t$rs1,$rs2,$rd";
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foreach ($rs1,$rs2,$rd) {
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if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
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else { return $ref; }
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00300|$rd<<25|$rs1<<14|$rs2,
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$ref;
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}
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foreach (split("\n",$code)) {
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s/\`([^\`]*)\`/eval $1/ge;
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s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
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&unvis($1,$2,$3,$4)
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/ge;
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s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
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&unalignaddr($1,$2,$3,$4)
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/ge;
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print $_,"\n";
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}
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close STDOUT or die "error closing STDOUT: $!";
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