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4746f25ac6
[skip ci] Reviewed-by: Matt Caswell <matt@openssl.org> (Merged from https://github.com/openssl/openssl/pull/7829)
168 lines
5.8 KiB
Plaintext
168 lines
5.8 KiB
Plaintext
=pod
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=head1 NAME
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OPENSSL_ia32cap - the x86[_64] processor capabilities vector
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=head1 SYNOPSIS
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env OPENSSL_ia32cap=... <application>
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=head1 DESCRIPTION
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OpenSSL supports a range of x86[_64] instruction set extensions. These
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extensions are denoted by individual bits in capability vector returned
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by processor in EDX:ECX register pair after executing CPUID instruction
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with EAX=1 input value (see Intel Application Note #241618). This vector
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is copied to memory upon toolkit initialization and used to choose
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between different code paths to provide optimal performance across wide
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range of processors. For the moment of this writing following bits are
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significant:
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=over 4
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=item bit #4 denoting presence of Time-Stamp Counter.
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=item bit #19 denoting availability of CLFLUSH instruction;
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=item bit #20, reserved by Intel, is used to choose among RC4 code paths;
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=item bit #23 denoting MMX support;
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=item bit #24, FXSR bit, denoting availability of XMM registers;
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=item bit #25 denoting SSE support;
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=item bit #26 denoting SSE2 support;
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=item bit #28 denoting Hyperthreading, which is used to distinguish
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cores with shared cache;
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=item bit #30, reserved by Intel, denotes specifically Intel CPUs;
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=item bit #33 denoting availability of PCLMULQDQ instruction;
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=item bit #41 denoting SSSE3, Supplemental SSE3, support;
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=item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
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=item bit #54 denoting availability of MOVBE instruction;
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=item bit #57 denoting AES-NI instruction set extension;
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=item bit #58, XSAVE bit, lack of which in combination with MOVBE is used
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to identify Atom Silvermont core;
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=item bit #59, OSXSAVE bit, denoting availability of YMM registers;
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=item bit #60 denoting AVX extension;
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=item bit #62 denoting availability of RDRAND instruction;
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=back
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For example, in 32-bit application context clearing bit #26 at run-time
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disables high-performance SSE2 code present in the crypto library, while
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clearing bit #24 disables SSE2 code operating on 128-bit XMM register
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bank. You might have to do the latter if target OpenSSL application is
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executed on SSE2 capable CPU, but under control of OS that does not
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enable XMM registers. Historically address of the capability vector copy
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was exposed to application through OPENSSL_ia32cap_loc(), but not
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anymore. Now the only way to affect the capability detection is to set
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OPENSSL_ia32cap environment variable prior target application start. To
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give a specific example, on Intel P4 processor 'env
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OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet 'env
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OPENSSL_ia32cap=~0x1000000 apps/openssl' would achieve the desired
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effect. Alternatively you can reconfigure the toolkit with no-sse2
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option and recompile.
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Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
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variable" terms. The truth is that it's not copied from CPUID output
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verbatim, but is adjusted to reflect whether or not the data cache is
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actually shared between logical cores. This in turn affects the decision
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on whether or not expensive countermeasures against cache-timing attacks
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are applied, most notably in AES assembler module.
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The capability vector is further extended with EBX value returned by
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CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
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=over 4
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=item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
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=item bit #64+5 denoting availability of AVX2 instructions;
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=item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
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and RORX;
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=item bit #64+16 denoting availability of AVX512F extension;
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=item bit #64+18 denoting availability of RDSEED instruction;
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=item bit #64+19 denoting availability of ADCX and ADOX instructions;
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=item bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
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a.k.a. AVX512IFMA extension;
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=item bit #64+29 denoting availability of SHA extension;
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=item bit #64+30 denoting availability of AVX512BW extension;
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=item bit #64+31 denoting availability of AVX512VL extension;
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=item bit #64+41 denoting availability of VAES extension;
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=item bit #64+42 denoting availability of VPCLMULQDQ extension;
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=back
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To control this extended capability word use ':' as delimiter when
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setting up OPENSSL_ia32cap environment variable. For example assigning
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':~0x20' would disable AVX2 code paths, and ':0' - all post-AVX
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extensions.
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It should be noted that whether or not some of the most "fancy"
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extension code paths are actually assembled depends on current assembler
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version. Base minimum of AES-NI/PCLMULQDQ, SSSE3 and SHA extension code
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paths are always assembled. Apart from that, minimum assembler version
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requirements are summarized in below table:
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Extension | GNU as | nasm | llvm
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------------+--------+--------+--------
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AVX | 2.19 | 2.09 | 3.0
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AVX2 | 2.22 | 2.10 | 3.1
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ADCX/ADOX | 2.23 | 2.10 | 3.3
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AVX512 | 2.25 | 2.11.8 | see NOTES
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AVX512IFMA | 2.26 | 2.11.8 | see NOTES
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VAES | 2.30 | 2.13.3 |
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=head1 NOTES
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Even though AVX512 support was implemented in llvm 3.6, compilation of
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assembly modules apparently requires explicit -march flag. But then
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compiler generates processor-specific code, which in turn contradicts
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the mere idea of run-time switch execution facilitated by the variable
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in question. Till the limitation is lifted, it's possible to work around
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the problem by making build procedure use following script:
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#!/bin/sh
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exec clang -no-integrated-as "$@"
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instead of real clang. In which case it doesn't matter which clang
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version is used, as it is GNU assembler version that will be checked.
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=head1 RETURN VALUES
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Not available.
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=head1 COPYRIGHT
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Copyright 2004-2018 The OpenSSL Project Authors. All Rights Reserved.
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Licensed under the Apache License 2.0 (the "License"). You may not use
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this file except in compliance with the License. You can obtain a copy
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in the file LICENSE in the source distribution or at
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L<https://www.openssl.org/source/license.html>.
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=cut
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