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md5-sparcv9.pl: add hardware SPARC T4 support.
Submitted by: David Miller
This commit is contained in:
Andy Polyakov
parent
b460c8f896
commit
e66055b8f7
@ -5,11 +5,18 @@
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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#
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# Hardware SPARC T4 support by David S. Miller <davem@davemloft.net>.
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# ====================================================================
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# MD5 for SPARCv9, 6.9 cycles per byte on UltraSPARC, >40% faster than
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# code generated by Sun C 5.2.
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# SPARC T4 MD5 hardware achieves 3.24 cycles per byte, which is 2.1x
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# faster than software. Multi-process benchmark saturates at 12x
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# single-process result on 8-core processor, or ~11GBps per 2.85GHz
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# socket.
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$bits=32;
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for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
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if ($bits==64) { $bias=2047; $frame=192; }
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@ -196,11 +203,95 @@ $code.=<<___ if ($bits==64);
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.register %g3,#scratch
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___
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$code.=<<___;
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#include "sparc_arch.h"
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.section ".text",#alloc,#execinstr
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#ifdef __PIC__
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SPARC_PIC_THUNK(%g1)
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#endif
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.globl md5_block_asm_data_order
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.align 32
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md5_block_asm_data_order:
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SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)
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ld [%g1+4],%g1 ! OPENSSL_sparcv9cap_P[1]
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andcc %g1, CFR_MD5, %g0
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be .Lsoftware
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nop
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rd %asi, %g5
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wr %g0, 0x88, %asi ! ASI_PRIMARY_LITTLE
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lda [%o0 + 0x00] %asi, %f0 ! load context
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lda [%o0 + 0x04] %asi, %f1
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andcc %o1, 0x7, %g0
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lda [%o0 + 0x08] %asi, %f2
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bne,pn %icc, .Lhwunaligned
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lda [%o0 + 0x0c] %asi, %f3
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.Lhw_loop:
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ldd [%o1 + 0x00], %f8
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ldd [%o1 + 0x08], %f10
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ldd [%o1 + 0x10], %f12
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ldd [%o1 + 0x18], %f14
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ldd [%o1 + 0x20], %f16
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ldd [%o1 + 0x28], %f18
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ldd [%o1 + 0x30], %f20
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subcc %o2, 1, %o2 ! done yet?
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ldd [%o1 + 0x38], %f22
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add %o1, 0x40, %o1
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.word 0x81b02800 ! MD5
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bne,pt `$bits==64?"%xcc":"%icc"`, .Lhw_loop
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nop
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.Lhwfinish:
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sta %f0, [%o0 + 0x00] %asi ! store context
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sta %f1, [%o0 + 0x04] %asi
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sta %f2, [%o0 + 0x08] %asi
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sta %f3, [%o0 + 0x0c] %asi
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retl
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wr %g5, 0x0, %asi ! restore %asi
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.align 8
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.Lhwunaligned:
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alignaddr %o1, %g0, %o1
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ldd [%o1 + 0x00], %f10
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.Lhwunaligned_loop:
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ldd [%o1 + 0x08], %f12
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ldd [%o1 + 0x10], %f14
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ldd [%o1 + 0x18], %f16
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ldd [%o1 + 0x20], %f18
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ldd [%o1 + 0x28], %f20
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ldd [%o1 + 0x30], %f22
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ldd [%o1 + 0x38], %f24
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subcc %o2, 1, %o2 ! done yet?
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ldd [%o1 + 0x40], %f26
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add %o1, 0x40, %o1
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faligndata %f10, %f12, %f8
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faligndata %f12, %f14, %f10
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faligndata %f14, %f16, %f12
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faligndata %f16, %f18, %f14
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faligndata %f18, %f20, %f16
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faligndata %f20, %f22, %f18
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faligndata %f22, %f24, %f20
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faligndata %f24, %f26, %f22
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.word 0x81b02800 ! MD5
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bne,pt `$bits==64?"%xcc":"%icc"`, .Lhwunaligned_loop
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for %f26, %f26, %f10 ! %f10=%f26
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ba .Lhwfinish
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nop
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.align 16
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.Lsoftware:
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save %sp,-$frame,%sp
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rd %asi,$saved_asi
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@ -279,6 +370,62 @@ $code.=<<___;
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.align 4
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___
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$code =~ s/\`([^\`]*)\`/eval $1/gem;
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print $code;
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# Purpose of these subroutines is to explicitly encode VIS instructions,
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# so that one can compile the module without having to specify VIS
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# extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
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# Idea is to reserve for option to produce "universal" binary and let
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# programmer detect if current CPU is VIS capable at run-time.
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sub unvis {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my $ref,$opf;
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my %visopf = ( "faligndata" => 0x048,
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"for" => 0x07c );
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$ref = "$mnemonic\t$rs1,$rs2,$rd";
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if ($opf=$visopf{$mnemonic}) {
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foreach ($rs1,$rs2,$rd) {
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return $ref if (!/%f([0-9]{1,2})/);
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$_=$1;
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if ($1>=32) {
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return $ref if ($1&1);
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# re-encode for upper double register addressing
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$_=($1|$1>>5)&31;
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}
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
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$ref;
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} else {
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return $ref;
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}
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}
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sub unalignaddr {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
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my $ref="$mnemonic\t$rs1,$rs2,$rd";
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foreach ($rs1,$rs2,$rd) {
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if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
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else { return $ref; }
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00300|$rd<<25|$rs1<<14|$rs2,
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$ref;
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}
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foreach (split("\n",$code)) {
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s/\`([^\`]*)\`/eval $1/ge;
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s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
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&unvis($1,$2,$3,$4)
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/ge;
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s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
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&unalignaddr($1,$2,$3,$4)
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/ge;
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print $_,"\n";
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}
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close STDOUT;
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