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Mitigate the hazard of cache-collision timing attack on last round. The
only chance for T[ed]4 to get evicted in this module is when its cache "overlaps" with last 128 bits of key schedule.
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@ -6,7 +6,7 @@
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# forms are granted according to the OpenSSL license.
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# ====================================================================
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#
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# Version 1.0
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# Version 1.1
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#
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# The major reason for undertaken effort was to mitigate the hazard of
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# cache-timing attack. This is [currently and initially!] addressed in
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@ -16,6 +16,9 @@
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# is an initial draft and one should expect more countermeasures to
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# be implemented...
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#
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# Version 1.1 prefetches T[ed]4 in order to mitigate attack on last
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# round.
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#
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# Even though performance was not the primary goal [on the contrary,
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# extra shifts "induced" by compressed S-box and longer loop epilogue
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# "induced" by scheduling for L2 have negative effect on performance],
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@ -78,7 +81,7 @@ ___
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$code.=<<___;
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.section ".text",#alloc,#execinstr
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.align 64
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.align 256
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AES_Te:
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___
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&_data_word(
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@ -364,20 +367,28 @@ _sparcv9_AES_encrypt:
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ld [$key+28],$t3 !
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srlx $acc9,8,$acc9
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xor $acc5,$s1,$s1
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ldx [$tbl+2048+0],%g0 ! prefetch te4
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srlx $acc10,16,$acc10
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xor $acc6,$s1,$s1
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ldx [$tbl+2048+32],%g0 ! prefetch te4
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srlx $acc11,24,$acc11
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xor $acc7,$s1,$s1
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ldx [$tbl+2048+64],%g0 ! prefetch te4
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srlx $acc13,8,$acc13
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xor $acc8,$s2,$s2
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ldx [$tbl+2048+96],%g0 ! prefetch te4
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srlx $acc14,16,$acc14 !
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xor $acc9,$s2,$s2
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ldx [$tbl+2048+128],%g0 ! prefetch te4
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srlx $acc15,24,$acc15
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xor $acc10,$s2,$s2
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ldx [$tbl+2048+160],%g0 ! prefetch te4
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srl $s0,21,$acc0
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xor $acc11,$s2,$s2
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ldx [$tbl+2048+192],%g0 ! prefetch te4
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xor $acc12,$acc14,$acc14
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xor $acc13,$s3,$s3
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ldx [$tbl+2048+224],%g0 ! prefetch te4
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srl $s1,13,$acc1 !
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xor $acc14,$s3,$s3
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xor $acc15,$s3,$s3
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@ -616,7 +627,7 @@ AES_encrypt:
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___
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$code.=<<___;
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.align 64
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.align 256
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AES_Td:
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___
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&_data_word(
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@ -902,20 +913,28 @@ _sparcv9_AES_decrypt:
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ld [$key+28],$t3 !
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srlx $acc9,8,$acc9
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xor $acc5,$s1,$s1
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ldx [$tbl+2048+0],%g0 ! prefetch td4
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srlx $acc10,16,$acc10
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xor $acc6,$s1,$s1
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ldx [$tbl+2048+32],%g0 ! prefetch td4
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srlx $acc11,24,$acc11
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xor $acc7,$s1,$s1
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ldx [$tbl+2048+64],%g0 ! prefetch td4
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srlx $acc13,8,$acc13
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xor $acc8,$s2,$s2
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ldx [$tbl+2048+96],%g0 ! prefetch td4
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srlx $acc14,16,$acc14 !
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xor $acc9,$s2,$s2
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ldx [$tbl+2048+128],%g0 ! prefetch td4
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srlx $acc15,24,$acc15
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xor $acc10,$s2,$s2
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ldx [$tbl+2048+160],%g0 ! prefetch td4
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srl $s0,21,$acc0
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xor $acc11,$s2,$s2
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ldx [$tbl+2048+192],%g0 ! prefetch td4
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xor $acc12,$acc14,$acc14
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xor $acc13,$s3,$s3
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ldx [$tbl+2048+224],%g0 ! prefetch td4
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and $acc0,2040,$acc0 !
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xor $acc14,$s3,$s3
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xor $acc15,$s3,$s3
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