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MIPS assembly pack: adapt it for MIPS[32|64]R6.
MIPS[32|64]R6 is binary and source incompatible with previous MIPS ISA specifications. Fortunately it's still possible to resolve differences in source code with standard pre-processor and switching to trap-free version of addition and subtraction instructions. Reviewed-by: Richard Levitte <levitte@openssl.org>
This commit is contained in:
Andy Polyakov
parent
a43249122b
commit
947716c187
@ -216,7 +216,7 @@
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},
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mips32_asm => {
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template => 1,
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bn_asm_src => "bn-mips.s mips-mont.s",
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bn_asm_src => "bn-mips.S mips-mont.S",
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aes_asm_src => "aes_cbc.c aes-mips.S",
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sha1_asm_src => "sha1-mips.S sha256-mips.S",
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},
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@ -65,8 +65,8 @@ $flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
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if ($flavour =~ /64|n32/i) {
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$PTR_LA="dla";
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$PTR_ADD="dadd"; # incidentally works even on n32
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$PTR_SUB="dsub"; # incidentally works even on n32
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$PTR_ADD="daddu"; # incidentally works even on n32
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$PTR_SUB="dsubu"; # incidentally works even on n32
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$PTR_INS="dins";
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$REG_S="sd";
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$REG_L="ld";
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@ -74,8 +74,8 @@ if ($flavour =~ /64|n32/i) {
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$SZREG=8;
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} else {
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$PTR_LA="la";
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$PTR_ADD="add";
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$PTR_SUB="sub";
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$PTR_ADD="addu";
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$PTR_SUB="subu";
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$PTR_INS="ins";
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$REG_S="sw";
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$REG_L="lw";
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@ -102,15 +102,13 @@ open STDOUT,">$output";
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my ($MSB,$LSB)=(0,3); # automatically converted to little-endian
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$code.=<<___;
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#include "mips_arch.h"
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.text
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#ifdef OPENSSL_FIPSCANISTER
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# include <openssl/fipssyms.h>
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#endif
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#if defined(__mips_smartmips) && !defined(_MIPS_ARCH_MIPS32R2)
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#define _MIPS_ARCH_MIPS32R2
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#endif
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#if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
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.option pic2
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#endif
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@ -146,7 +144,7 @@ _mips_AES_encrypt:
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xor $s2,$t2
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xor $s3,$t3
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sub $cnt,1
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subu $cnt,1
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#if defined(__mips_smartmips)
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ext $i0,$s1,16,8
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.Loop_enc:
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@ -218,7 +216,7 @@ _mips_AES_encrypt:
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xor $t2,$t6
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xor $t3,$t7
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sub $cnt,1
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subu $cnt,1
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$PTR_ADD $key0,16
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xor $s0,$t0
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xor $s1,$t1
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@ -409,7 +407,7 @@ _mips_AES_encrypt:
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xor $t2,$t6
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xor $t3,$t7
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sub $cnt,1
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subu $cnt,1
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$PTR_ADD $key0,16
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xor $s0,$t0
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xor $s1,$t1
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@ -657,6 +655,12 @@ $code.=<<___;
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.set reorder
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$PTR_LA $Tbl,AES_Te # PIC-ified 'load address'
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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lw $s0,0($inp)
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lw $s1,4($inp)
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lw $s2,8($inp)
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lw $s3,12($inp)
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#else
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lwl $s0,0+$MSB($inp)
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lwl $s1,4+$MSB($inp)
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lwl $s2,8+$MSB($inp)
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@ -665,9 +669,16 @@ $code.=<<___;
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lwr $s1,4+$LSB($inp)
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lwr $s2,8+$LSB($inp)
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lwr $s3,12+$LSB($inp)
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#endif
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bal _mips_AES_encrypt
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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sw $s0,0($out)
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sw $s1,4($out)
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sw $s2,8($out)
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sw $s3,12($out)
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#else
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swr $s0,0+$LSB($out)
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swr $s1,4+$LSB($out)
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swr $s2,8+$LSB($out)
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@ -676,6 +687,7 @@ $code.=<<___;
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swl $s1,4+$MSB($out)
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swl $s2,8+$MSB($out)
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swl $s3,12+$MSB($out)
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#endif
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.set noreorder
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$REG_L $ra,$FRAMESIZE-1*$SZREG($sp)
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@ -720,7 +732,7 @@ _mips_AES_decrypt:
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xor $s2,$t2
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xor $s3,$t3
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sub $cnt,1
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subu $cnt,1
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#if defined(__mips_smartmips)
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ext $i0,$s3,16,8
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.Loop_dec:
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@ -792,7 +804,7 @@ _mips_AES_decrypt:
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xor $t2,$t6
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xor $t3,$t7
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sub $cnt,1
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subu $cnt,1
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$PTR_ADD $key0,16
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xor $s0,$t0
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xor $s1,$t1
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@ -985,7 +997,7 @@ _mips_AES_decrypt:
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xor $t2,$t6
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xor $t3,$t7
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sub $cnt,1
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subu $cnt,1
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$PTR_ADD $key0,16
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xor $s0,$t0
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xor $s1,$t1
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@ -1228,6 +1240,12 @@ $code.=<<___;
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.set reorder
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$PTR_LA $Tbl,AES_Td # PIC-ified 'load address'
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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lw $s0,0($inp)
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lw $s1,4($inp)
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lw $s2,8($inp)
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lw $s3,12($inp)
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#else
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lwl $s0,0+$MSB($inp)
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lwl $s1,4+$MSB($inp)
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lwl $s2,8+$MSB($inp)
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@ -1236,9 +1254,16 @@ $code.=<<___;
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lwr $s1,4+$LSB($inp)
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lwr $s2,8+$LSB($inp)
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lwr $s3,12+$LSB($inp)
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#endif
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bal _mips_AES_decrypt
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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sw $s0,0($out)
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sw $s1,4($out)
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sw $s2,8($out)
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sw $s3,12($out)
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#else
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swr $s0,0+$LSB($out)
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swr $s1,4+$LSB($out)
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swr $s2,8+$LSB($out)
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@ -1247,6 +1272,7 @@ $code.=<<___;
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swl $s1,4+$MSB($out)
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swl $s2,8+$MSB($out)
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swl $s3,12+$MSB($out)
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#endif
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.set noreorder
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$REG_L $ra,$FRAMESIZE-1*$SZREG($sp)
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@ -1295,35 +1321,52 @@ _mips_AES_set_encrypt_key:
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$PTR_ADD $rcon,$Tbl,256
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.set reorder
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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lw $rk0,0($inp) # load 128 bits
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lw $rk1,4($inp)
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lw $rk2,8($inp)
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lw $rk3,12($inp)
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#else
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lwl $rk0,0+$MSB($inp) # load 128 bits
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lwl $rk1,4+$MSB($inp)
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lwl $rk2,8+$MSB($inp)
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lwl $rk3,12+$MSB($inp)
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li $at,128
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lwr $rk0,0+$LSB($inp)
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lwr $rk1,4+$LSB($inp)
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lwr $rk2,8+$LSB($inp)
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lwr $rk3,12+$LSB($inp)
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#endif
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li $at,128
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.set noreorder
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beq $bits,$at,.L128bits
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li $cnt,10
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.set reorder
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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lw $rk4,16($inp) # load 192 bits
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lw $rk5,20($inp)
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#else
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lwl $rk4,16+$MSB($inp) # load 192 bits
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lwl $rk5,20+$MSB($inp)
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li $at,192
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lwr $rk4,16+$LSB($inp)
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lwr $rk5,20+$LSB($inp)
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#endif
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li $at,192
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.set noreorder
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beq $bits,$at,.L192bits
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li $cnt,8
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.set reorder
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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lw $rk6,24($inp) # load 256 bits
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lw $rk7,28($inp)
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#else
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lwl $rk6,24+$MSB($inp) # load 256 bits
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lwl $rk7,28+$MSB($inp)
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li $at,256
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lwr $rk6,24+$LSB($inp)
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lwr $rk7,28+$LSB($inp)
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#endif
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li $at,256
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.set noreorder
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beq $bits,$at,.L256bits
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li $cnt,7
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@ -1353,7 +1396,7 @@ _mips_AES_set_encrypt_key:
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sw $rk1,4($key)
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sw $rk2,8($key)
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sw $rk3,12($key)
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sub $cnt,1
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subu $cnt,1
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$PTR_ADD $key,16
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_bias $i0,24
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@ -1410,7 +1453,7 @@ _mips_AES_set_encrypt_key:
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sw $rk3,12($key)
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sw $rk4,16($key)
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sw $rk5,20($key)
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sub $cnt,1
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subu $cnt,1
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$PTR_ADD $key,24
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_bias $i0,24
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@ -1471,7 +1514,7 @@ _mips_AES_set_encrypt_key:
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sw $rk5,20($key)
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sw $rk6,24($key)
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sw $rk7,28($key)
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sub $cnt,1
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subu $cnt,1
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_bias $i0,24
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_bias $i1,16
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@ -1653,7 +1696,7 @@ $code.=<<___;
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lw $tp1,16($key) # modulo-scheduled
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lui $x80808080,0x8080
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sub $cnt,1
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subu $cnt,1
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or $x80808080,0x8080
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sll $cnt,2
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$PTR_ADD $key,16
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@ -1716,7 +1759,7 @@ $code.=<<___;
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lw $tp1,4($key) # modulo-scheduled
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xor $tpe,$tp2
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#endif
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sub $cnt,1
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subu $cnt,1
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sw $tpe,0($key)
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$PTR_ADD $key,4
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bnez $cnt,.Lmix
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@ -35,6 +35,7 @@ GENERATE[aesp8-ppc.s]=asm/aesp8-ppc.pl $(PERLASM_SCHEME)
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GENERATE[aes-parisc.s]=asm/aes-parisc.pl $(PERLASM_SCHEME)
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GENERATE[aes-mips.S]=asm/aes-mips.pl $(PERLASM_SCHEME)
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INCLUDE[aes-mips.o]=..
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GENERATE[aesv8-armx.S]=asm/aesv8-armx.pl $(PERLASM_SCHEME)
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INCLUDE[aesv8-armx.o]=..
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@ -56,14 +56,14 @@
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$flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
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if ($flavour =~ /64|n32/i) {
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$PTR_ADD="dadd"; # incidentally works even on n32
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$PTR_SUB="dsub"; # incidentally works even on n32
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$PTR_ADD="daddu"; # incidentally works even on n32
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$PTR_SUB="dsubu"; # incidentally works even on n32
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$REG_S="sd";
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$REG_L="ld";
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$SZREG=8;
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} else {
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$PTR_ADD="add";
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$PTR_SUB="sub";
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$PTR_ADD="addu";
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$PTR_SUB="subu";
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$REG_S="sw";
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$REG_L="lw";
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$SZREG=4;
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@ -121,6 +121,8 @@ $m1=$s11;
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$FRAMESIZE=14;
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$code=<<___;
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#include "mips_arch.h"
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.text
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.set noat
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@ -183,27 +185,27 @@ $code.=<<___;
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$PTR_SUB $sp,$num
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and $sp,$at
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$MULTU $aj,$bi
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$LD $alo,$BNSZ($ap)
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$LD $nlo,$BNSZ($np)
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mflo $lo0
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mfhi $hi0
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$MULTU $lo0,$n0
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mflo $m1
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$MULTU ($aj,$bi)
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$LD $ahi,$BNSZ($ap)
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$LD $nhi,$BNSZ($np)
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mflo ($lo0,$aj,$bi)
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mfhi ($hi0,$aj,$bi)
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$MULTU ($lo0,$n0)
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mflo ($m1,$lo0,$n0)
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$MULTU $alo,$bi
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mflo $alo
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mfhi $ahi
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$MULTU ($ahi,$bi)
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mflo ($alo,$ahi,$bi)
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mfhi ($ahi,$ahi,$bi)
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$MULTU $nj,$m1
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mflo $lo1
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mfhi $hi1
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$MULTU $nlo,$m1
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$MULTU ($nj,$m1)
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mflo ($lo1,$nj,$m1)
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mfhi ($hi1,$nj,$m1)
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$MULTU ($nhi,$m1)
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$ADDU $lo1,$lo0
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sltu $at,$lo1,$lo0
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$ADDU $hi1,$at
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mflo $nlo
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mfhi $nhi
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mflo ($nlo,$nhi,$m1)
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mfhi ($nhi,$nhi,$m1)
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move $tp,$sp
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li $j,2*$BNSZ
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@ -215,25 +217,25 @@ $code.=<<___;
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$LD $aj,($aj)
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$LD $nj,($nj)
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$MULTU $aj,$bi
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$MULTU ($aj,$bi)
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$ADDU $lo0,$alo,$hi0
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$ADDU $lo1,$nlo,$hi1
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sltu $at,$lo0,$hi0
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sltu $t0,$lo1,$hi1
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$ADDU $hi0,$ahi,$at
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$ADDU $hi1,$nhi,$t0
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mflo $alo
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mfhi $ahi
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mflo ($alo,$aj,$bi)
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mfhi ($ahi,$aj,$bi)
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$ADDU $lo1,$lo0
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sltu $at,$lo1,$lo0
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$MULTU $nj,$m1
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$MULTU ($nj,$m1)
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$ADDU $hi1,$at
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addu $j,$BNSZ
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$ST $lo1,($tp)
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sltu $t0,$j,$num
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mflo $nlo
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mfhi $nhi
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mflo ($nlo,$nj,$m1)
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mfhi ($nhi,$nj,$m1)
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bnez $t0,.L1st
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$PTR_ADD $tp,$BNSZ
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@ -263,34 +265,34 @@ $code.=<<___;
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$PTR_ADD $bi,$bp,$i
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$LD $bi,($bi)
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$LD $aj,($ap)
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$LD $alo,$BNSZ($ap)
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$LD $ahi,$BNSZ($ap)
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$LD $tj,($sp)
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$MULTU $aj,$bi
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$MULTU ($aj,$bi)
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$LD $nj,($np)
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$LD $nlo,$BNSZ($np)
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mflo $lo0
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mfhi $hi0
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$LD $nhi,$BNSZ($np)
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mflo ($lo0,$aj,$bi)
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mfhi ($hi0,$aj,$bi)
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$ADDU $lo0,$tj
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$MULTU $lo0,$n0
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$MULTU ($lo0,$n0)
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sltu $at,$lo0,$tj
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$ADDU $hi0,$at
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mflo $m1
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mflo ($m1,$lo0,$n0)
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$MULTU $alo,$bi
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mflo $alo
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mfhi $ahi
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$MULTU ($ahi,$bi)
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mflo ($alo,$ahi,$bi)
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mfhi ($ahi,$ahi,$bi)
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$MULTU $nj,$m1
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mflo $lo1
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mfhi $hi1
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$MULTU ($nj,$m1)
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mflo ($lo1,$nj,$m1)
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mfhi ($hi1,$nj,$m1)
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$MULTU $nlo,$m1
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$MULTU ($nhi,$m1)
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$ADDU $lo1,$lo0
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sltu $at,$lo1,$lo0
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$ADDU $hi1,$at
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mflo $nlo
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mfhi $nhi
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mflo ($nlo,$nhi,$m1)
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mfhi ($nhi,$nhi,$m1)
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move $tp,$sp
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li $j,2*$BNSZ
|
||||
@ -303,19 +305,19 @@ $code.=<<___;
|
||||
$LD $aj,($aj)
|
||||
$LD $nj,($nj)
|
||||
|
||||
$MULTU $aj,$bi
|
||||
$MULTU ($aj,$bi)
|
||||
$ADDU $lo0,$alo,$hi0
|
||||
$ADDU $lo1,$nlo,$hi1
|
||||
sltu $at,$lo0,$hi0
|
||||
sltu $t0,$lo1,$hi1
|
||||
$ADDU $hi0,$ahi,$at
|
||||
$ADDU $hi1,$nhi,$t0
|
||||
mflo $alo
|
||||
mfhi $ahi
|
||||
mflo ($alo,$aj,$bi)
|
||||
mfhi ($ahi,$aj,$bi)
|
||||
|
||||
$ADDU $lo0,$tj
|
||||
addu $j,$BNSZ
|
||||
$MULTU $nj,$m1
|
||||
$MULTU ($nj,$m1)
|
||||
sltu $at,$lo0,$tj
|
||||
$ADDU $lo1,$lo0
|
||||
$ADDU $hi0,$at
|
||||
@ -323,8 +325,8 @@ $code.=<<___;
|
||||
$LD $tj,2*$BNSZ($tp)
|
||||
$ADDU $hi1,$t0
|
||||
sltu $at,$j,$num
|
||||
mflo $nlo
|
||||
mfhi $nhi
|
||||
mflo ($nlo,$nj,$m1)
|
||||
mfhi ($nhi,$nj,$m1)
|
||||
$ST $lo1,($tp)
|
||||
bnez $at,.Linner
|
||||
$PTR_ADD $tp,$BNSZ
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -34,8 +34,10 @@ INCLUDE[sparct4-mont.o]=..
|
||||
GENERATE[sparcv9-gf2m.S]=asm/sparcv9-gf2m.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[sparcv9-gf2m.o]=..
|
||||
|
||||
GENERATE[bn-mips.s]=asm/mips.pl $(PERLASM_SCHEME)
|
||||
GENERATE[mips-mont.s]=asm/mips-mont.pl $(PERLASM_SCHEME)
|
||||
GENERATE[bn-mips.S]=asm/mips.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[bn-mips.o]=..
|
||||
GENERATE[mips-mont.S]=asm/mips-mont.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[mips-mont.o]=..
|
||||
|
||||
GENERATE[s390x-mont.S]=asm/s390x-mont.pl $(PERLASM_SCHEME)
|
||||
GENERATE[s390x-gf2m.s]=asm/s390x-gf2m.pl $(PERLASM_SCHEME)
|
||||
@ -64,16 +66,8 @@ GENERATE[armv4-gf2m.S]=asm/armv4-gf2m.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[armv4-gf2m.o]=..
|
||||
GENERATE[armv8-mont.S]=asm/armv8-mont.pl $(PERLASM_SCHEME)
|
||||
|
||||
OVERRIDES=bn-mips3.o pa-risc2W.o pa-risc2.c
|
||||
OVERRIDES=pa-risc2W.o pa-risc2.c
|
||||
BEGINRAW[Makefile]
|
||||
##### BN assembler implementations
|
||||
|
||||
{- $builddir -}/bn-mips3.o: {- $sourcedir -}/asm/mips3.s
|
||||
@if [ "$(CC)" = "gcc" ]; then \
|
||||
ABI=`expr "$(CFLAGS)" : ".*-mabi=\([n3264]*\)"` && \
|
||||
as -$$ABI -O -o $@ {- $sourcedir -}/asm/mips3.s; \
|
||||
else $(CC) -c $(CFLAGS) $(LIB_CFLAGS) -o $@ {- $sourcedir -}/asm/mips3.s; fi
|
||||
|
||||
# GNU assembler fails to compile PA-RISC2 modules, insist on calling
|
||||
# vendor assembler...
|
||||
{- $builddir -}/pa-risc2W.o: {- $sourcedir -}/asm/pa-risc2W.s
|
||||
|
||||
40
crypto/mips_arch.h
Normal file
40
crypto/mips_arch.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright 2011-2016 The OpenSSL Project Authors. All Rights Reserved.
|
||||
*
|
||||
* Licensed under the OpenSSL license (the "License"). You may not use
|
||||
* this file except in compliance with the License. You can obtain a copy
|
||||
* in the file LICENSE in the source distribution or at
|
||||
* https://www.openssl.org/source/license.html
|
||||
*/
|
||||
|
||||
#ifndef __MIPS_ARCH_H__
|
||||
# define __MIPS_ARCH_H__
|
||||
|
||||
# if (defined(__mips_smartmips) || defined(_MIPS_ARCH_MIPS32R3) || \
|
||||
defined(_MIPS_ARCH_MIPS32R5) || defined(_MIPS_ARCH_MIPS32R6))
|
||||
&& !defined(_MIPS_ARCH_MIPS32R2)
|
||||
# define _MIPS_ARCH_MIPS32R2
|
||||
# endif
|
||||
|
||||
# if (defined(_MIPS_ARCH_MIPS64R3) || defined(_MIPS_ARCH_MIPS64R5) || \
|
||||
defined(_MIPS_ARCH_MIPS64R6)) \
|
||||
&& !defined(_MIPS_ARCH_MIPS64R2)
|
||||
# define _MIPS_ARCH_MIPS64R2
|
||||
# endif
|
||||
|
||||
# if defined(_MIPS_ARCH_MIPS64R6)
|
||||
# define dmultu(rs,rt)
|
||||
# define mflo(rd,rs,rt) dmulu rd,rs,rt
|
||||
# define mfhi(rd,rs,rt) dmuhu rd,rs,rt
|
||||
# elif defined(_MIPS_ARCH_MIPS32R6)
|
||||
# define multu(rs,rt)
|
||||
# define mflo(rd,rs,rt) mulu rd,rs,rt
|
||||
# define mfhi(rd,rs,rt) muhu rd,rs,rt
|
||||
# else
|
||||
# define dmultu(rs,rt) dmultu rs,rt
|
||||
# define multu(rs,rt) multu rs,rt
|
||||
# define mflo(rd,rs,rt) mflo rd
|
||||
# define mfhi(rd,rs,rt) mfhi rd
|
||||
# endif
|
||||
|
||||
#endif
|
||||
@ -67,6 +67,8 @@ $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0x0003f000" : "0x00030000";
|
||||
($in0,$in1,$tmp0,$tmp1,$tmp2,$tmp3,$tmp4) = ($a4,$a5,$a6,$a7,$at,$t0,$t1);
|
||||
|
||||
$code.=<<___;
|
||||
#include "mips_arch.h"
|
||||
|
||||
#ifdef MIPSEB
|
||||
# define MSB 0
|
||||
# define LSB 7
|
||||
@ -92,10 +94,15 @@ poly1305_init:
|
||||
|
||||
beqz $inp,.Lno_key
|
||||
|
||||
#if defined(_MIPS_ARCH_MIPS64R6)
|
||||
ld $in0,0($inp)
|
||||
ld $in1,8($inp)
|
||||
#else
|
||||
ldl $in0,0+MSB($inp)
|
||||
ldl $in1,8+MSB($inp)
|
||||
ldr $in0,0+LSB($inp)
|
||||
ldr $in1,8+LSB($inp)
|
||||
#endif
|
||||
#ifdef MIPSEB
|
||||
# if defined(_MIPS_ARCH_MIPS64R2)
|
||||
dsbh $in0,$in0 # byte swap
|
||||
@ -182,7 +189,7 @@ poly1305_blocks_internal:
|
||||
.frame $sp,6*8,$ra
|
||||
.mask $SAVED_REGS_MASK,-8
|
||||
.set noreorder
|
||||
dsub $sp,6*8
|
||||
dsubu $sp,6*8
|
||||
sd $s5,40($sp)
|
||||
sd $s4,32($sp)
|
||||
___
|
||||
@ -204,11 +211,16 @@ $code.=<<___;
|
||||
ld $s1,40($ctx)
|
||||
|
||||
.Loop:
|
||||
#if defined(_MIPS_ARCH_MIPS64R6)
|
||||
ld $in0,0($inp) # load input
|
||||
ld $in1,8($inp)
|
||||
#else
|
||||
ldl $in0,0+MSB($inp) # load input
|
||||
ldl $in1,8+MSB($inp)
|
||||
ldr $in0,0+LSB($inp)
|
||||
daddiu $len,-1
|
||||
ldr $in1,8+LSB($inp)
|
||||
#endif
|
||||
daddiu $len,-1
|
||||
daddiu $inp,16
|
||||
#ifdef MIPSEB
|
||||
# if defined(_MIPS_ARCH_MIPS64R2)
|
||||
@ -258,42 +270,42 @@ $code.=<<___;
|
||||
sltu $tmp1,$h1,$in1
|
||||
daddu $h1,$tmp0
|
||||
|
||||
dmultu $r0,$h0 # h0*r0
|
||||
dmultu ($r0,$h0) # h0*r0
|
||||
daddu $h2,$padbit
|
||||
sltu $tmp0,$h1,$tmp0
|
||||
mflo $d0
|
||||
mfhi $d1
|
||||
mflo ($d0,$r0,$h0)
|
||||
mfhi ($d1,$r0,$h0)
|
||||
|
||||
dmultu $s1,$h1 # h1*5*r1
|
||||
dmultu ($s1,$h1) # h1*5*r1
|
||||
daddu $tmp0,$tmp1
|
||||
daddu $h2,$tmp0
|
||||
mflo $tmp0
|
||||
mfhi $tmp1
|
||||
mflo ($tmp0,$s1,$h1)
|
||||
mfhi ($tmp1,$s1,$h1)
|
||||
|
||||
dmultu $r1,$h0 # h0*r1
|
||||
dmultu ($r1,$h0) # h0*r1
|
||||
daddu $d0,$tmp0
|
||||
daddu $d1,$tmp1
|
||||
mflo $tmp2
|
||||
mfhi $d2
|
||||
mflo ($tmp2,$r1,$h0)
|
||||
mfhi ($d2,$r1,$h0)
|
||||
sltu $tmp0,$d0,$tmp0
|
||||
daddu $d1,$tmp0
|
||||
|
||||
dmultu $r0,$h1 # h1*r0
|
||||
dmultu ($r0,$h1) # h1*r0
|
||||
daddu $d1,$tmp2
|
||||
sltu $tmp2,$d1,$tmp2
|
||||
mflo $tmp0
|
||||
mfhi $tmp1
|
||||
mflo ($tmp0,$r0,$h1)
|
||||
mfhi ($tmp1,$r0,$h1)
|
||||
daddu $d2,$tmp2
|
||||
|
||||
dmultu $s1,$h2 # h2*5*r1
|
||||
dmultu ($s1,$h2) # h2*5*r1
|
||||
daddu $d1,$tmp0
|
||||
daddu $d2,$tmp1
|
||||
mflo $tmp2
|
||||
mflo ($tmp2,$s1,$h2)
|
||||
|
||||
dmultu $r0,$h2 # h2*r0
|
||||
dmultu ($r0,$h2) # h2*r0
|
||||
sltu $tmp0,$d1,$tmp0
|
||||
daddu $d2,$tmp0
|
||||
mflo $tmp3
|
||||
mflo ($tmp3,$r0,$h2)
|
||||
|
||||
daddu $d1,$tmp2
|
||||
daddu $d2,$tmp3
|
||||
@ -329,7 +341,7 @@ $code.=<<___ if ($flavour =~ /nubi/i); # optimize non-nubi epilogue
|
||||
___
|
||||
$code.=<<___;
|
||||
jr $ra
|
||||
dadd $sp,6*8
|
||||
daddu $sp,6*8
|
||||
.end poly1305_blocks_internal
|
||||
___
|
||||
}
|
||||
|
||||
@ -13,6 +13,7 @@ INCLUDE[poly1305-armv4.o]=..
|
||||
GENERATE[poly1305-armv8.S]=asm/poly1305-armv8.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[poly1305-armv8.o]=..
|
||||
GENERATE[poly1305-mips.S]=asm/poly1305-mips.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[poly1305-mips.o]=..
|
||||
|
||||
BEGINRAW[Makefile(unix)]
|
||||
{- $builddir -}/poly1305-%.S: {- $sourcedir -}/asm/poly1305-%.pl
|
||||
|
||||
@ -56,15 +56,15 @@
|
||||
$flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
|
||||
|
||||
if ($flavour =~ /64|n32/i) {
|
||||
$PTR_ADD="dadd"; # incidentally works even on n32
|
||||
$PTR_SUB="dsub"; # incidentally works even on n32
|
||||
$PTR_ADD="daddu"; # incidentally works even on n32
|
||||
$PTR_SUB="dsubu"; # incidentally works even on n32
|
||||
$REG_S="sd";
|
||||
$REG_L="ld";
|
||||
$PTR_SLL="dsll"; # incidentally works even on n32
|
||||
$SZREG=8;
|
||||
} else {
|
||||
$PTR_ADD="add";
|
||||
$PTR_SUB="sub";
|
||||
$PTR_ADD="addu";
|
||||
$PTR_SUB="subu";
|
||||
$REG_S="sw";
|
||||
$REG_L="lw";
|
||||
$PTR_SLL="sll";
|
||||
@ -126,10 +126,14 @@ $code.=<<___;
|
||||
addu $e,$K # $i
|
||||
xor $t0,$c,$d
|
||||
rotr $t1,$a,27
|
||||
lwl @X[$j],$j*4+$MSB($inp)
|
||||
and $t0,$b
|
||||
addu $e,$t1
|
||||
#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
|
||||
lw @X[$j],$j*4($inp)
|
||||
#else
|
||||
lwl @X[$j],$j*4+$MSB($inp)
|
||||
lwr @X[$j],$j*4+$LSB($inp)
|
||||
#endif
|
||||
xor $t0,$d
|
||||
addu $e,@X[$i]
|
||||
rotr $b,$b,2
|
||||
@ -336,14 +340,12 @@ $FRAMESIZE=16; # large enough to accommodate NUBI saved registers
|
||||
$SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";
|
||||
|
||||
$code=<<___;
|
||||
#include "mips_arch.h"
|
||||
|
||||
#ifdef OPENSSL_FIPSCANISTER
|
||||
# include <openssl/fipssyms.h>
|
||||
#endif
|
||||
|
||||
#if defined(__mips_smartmips) && !defined(_MIPS_ARCH_MIPS32R2)
|
||||
#define _MIPS_ARCH_MIPS32R2
|
||||
#endif
|
||||
|
||||
.text
|
||||
|
||||
.set noat
|
||||
@ -387,10 +389,16 @@ $code.=<<___;
|
||||
.align 4
|
||||
.Loop:
|
||||
.set reorder
|
||||
#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
|
||||
lui $K,0x5a82
|
||||
lw @X[0],($inp)
|
||||
ori $K,0x7999 # K_00_19
|
||||
#else
|
||||
lwl @X[0],$MSB($inp)
|
||||
lui $K,0x5a82
|
||||
lwr @X[0],$LSB($inp)
|
||||
ori $K,0x7999 # K_00_19
|
||||
#endif
|
||||
___
|
||||
for ($i=0;$i<15;$i++) { &BODY_00_14($i,@V); unshift(@V,pop(@V)); }
|
||||
for (;$i<20;$i++) { &BODY_15_19($i,@V); unshift(@V,pop(@V)); }
|
||||
|
||||
@ -60,16 +60,16 @@ $flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
|
||||
|
||||
if ($flavour =~ /64|n32/i) {
|
||||
$PTR_LA="dla";
|
||||
$PTR_ADD="dadd"; # incidentally works even on n32
|
||||
$PTR_SUB="dsub"; # incidentally works even on n32
|
||||
$PTR_ADD="daddu"; # incidentally works even on n32
|
||||
$PTR_SUB="dsubu"; # incidentally works even on n32
|
||||
$REG_S="sd";
|
||||
$REG_L="ld";
|
||||
$PTR_SLL="dsll"; # incidentally works even on n32
|
||||
$SZREG=8;
|
||||
} else {
|
||||
$PTR_LA="la";
|
||||
$PTR_ADD="add";
|
||||
$PTR_SUB="sub";
|
||||
$PTR_ADD="addu";
|
||||
$PTR_SUB="subu";
|
||||
$REG_S="sw";
|
||||
$REG_L="lw";
|
||||
$PTR_SLL="sll";
|
||||
@ -135,8 +135,12 @@ my ($i,$a,$b,$c,$d,$e,$f,$g,$h)=@_;
|
||||
my ($T1,$tmp0,$tmp1,$tmp2)=(@X[4],@X[5],@X[6],@X[7]);
|
||||
|
||||
$code.=<<___ if ($i<15);
|
||||
#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
|
||||
${LD} @X[1],`($i+1)*$SZ`($inp)
|
||||
#else
|
||||
${LD}l @X[1],`($i+1)*$SZ+$MSB`($inp)
|
||||
${LD}r @X[1],`($i+1)*$SZ+$LSB`($inp)
|
||||
#endif
|
||||
___
|
||||
$code.=<<___ if (!$big_endian && $i<16 && $SZ==4);
|
||||
#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
|
||||
@ -298,14 +302,12 @@ $FRAMESIZE=16*$SZ+16*$SZREG;
|
||||
$SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";
|
||||
|
||||
$code.=<<___;
|
||||
#include "mips_arch.h"
|
||||
|
||||
#ifdef OPENSSL_FIPSCANISTER
|
||||
# include <openssl/fipssyms.h>
|
||||
#endif
|
||||
|
||||
#if defined(__mips_smartmips) && !defined(_MIPS_ARCH_MIPS32R2)
|
||||
#define _MIPS_ARCH_MIPS32R2
|
||||
#endif
|
||||
|
||||
.text
|
||||
.set noat
|
||||
#if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
|
||||
@ -369,8 +371,12 @@ $code.=<<___;
|
||||
|
||||
.align 5
|
||||
.Loop:
|
||||
#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
|
||||
${LD} @X[0],($inp)
|
||||
#else
|
||||
${LD}l @X[0],$MSB($inp)
|
||||
${LD}r @X[0],$LSB($inp)
|
||||
#endif
|
||||
___
|
||||
for ($i=0;$i<16;$i++)
|
||||
{ &BODY_00_15($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
|
||||
|
||||
@ -39,8 +39,11 @@ GENERATE[sha256-parisc.s]=asm/sha512-parisc.pl $(PERLASM_SCHEME)
|
||||
GENERATE[sha512-parisc.s]=asm/sha512-parisc.pl $(PERLASM_SCHEME)
|
||||
|
||||
GENERATE[sha1-mips.S]=asm/sha1-mips.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[sha1-mips.o]=..
|
||||
GENERATE[sha256-mips.S]=asm/sha512-mips.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[sha256-mips.o]=..
|
||||
GENERATE[sha512-mips.S]=asm/sha512-mips.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[sha512-mips.o]=..
|
||||
|
||||
GENERATE[sha1-armv4-large.S]=asm/sha1-armv4-large.pl $(PERLASM_SCHEME)
|
||||
INCLUDE[sha1-armv4-large.o]=..
|
||||
|
||||
Loading…
Reference in New Issue
Block a user