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aarch64: fix BTI in bsaes assembly code

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Change-Id: I63f0fb2af5eb9cea515dec96485325f8efd50511

Reviewed-by: Shane Lontis <shane.lontis@oracle.com>
Reviewed-by: Kurt Roeckx <kurt@roeckx.be>
(Merged from https://github.com/openssl/openssl/pull/23982)
This commit is contained in:
Tom Cosgrove 2024-03-26 13:18:00 +00:00 committed by Tomas Mraz
parent f5b5a35c84
commit 88c74fe05b
1 changed files with 4 additions and 1 deletions
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5
crypto/aes/asm/bsaes-armv8.pl
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@ -1018,6 +1018,7 @@ _bsaes_key_convert:
// Initialisation vector overwritten with last quadword of ciphertext
// No output registers, usual AAPCS64 register preservation
ossl_bsaes_cbc_encrypt:
AARCH64_VALID_CALL_TARGET
cmp x2, #128
bhs .Lcbc_do_bsaes
b AES_cbc_encrypt
@ -1270,7 +1271,7 @@ ossl_bsaes_cbc_encrypt:
// Output text filled in
// No output registers, usual AAPCS64 register preservation
ossl_bsaes_ctr32_encrypt_blocks:
AARCH64_VALID_CALL_TARGET
cmp x2, #8 // use plain AES for
blo .Lctr_enc_short // small sizes
@ -1476,6 +1477,7 @@ ossl_bsaes_ctr32_encrypt_blocks:
// Output ciphertext filled in
// No output registers, usual AAPCS64 register preservation
ossl_bsaes_xts_encrypt:
AARCH64_VALID_CALL_TARGET
// Stack layout:
// sp ->
// nrounds*128-96 bytes: key schedule
@ -1921,6 +1923,7 @@ ossl_bsaes_xts_encrypt:
// Output plaintext filled in
// No output registers, usual AAPCS64 register preservation
ossl_bsaes_xts_decrypt:
AARCH64_VALID_CALL_TARGET
// Stack layout:
// sp ->
// nrounds*128-96 bytes: key schedule