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riscv: Provide vector crypto implementation of AES-ECB mode.

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This patch provides stream and multi-block implementations for
AES-128-ECB, AES-192-ECB, and AES-256-ECB to accelerate AES-ECB.
Also, refactor functions to share the same variable
declaration in aes-riscv64-zvkned.pl.

Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>

Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Hugo Landau <hlandau@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/21923)
This commit is contained in:
Phoebe Chen 2023-09-24 20:07:48 -07:00 committed by Hugo Landau
parent 1c25bc2e3f
commit 751a22194e
2 changed files with 676 additions and 460 deletions
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1130
crypto/aes/asm/aes-riscv64-zvkned.pl
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6
providers/implementations/ciphers/cipher_aes_hw_rv64i.inc
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@ -93,6 +93,12 @@ static int cipher_hw_rv64i_zvkned_initkey(PROV_CIPHER_CTX *dat,
if (RISCV_HAS_ZVKB()) {
dat->stream.ctr = (ctr128_f) rv64i_zvkb_zvkned_ctr32_encrypt_blocks;
}
} else if (dat->mode == EVP_CIPH_ECB_MODE) {
if (dat->enc) {
dat->stream.ecb = (ecb128_f) rv64i_zvkned_ecb_encrypt;
} else {
dat->stream.ecb = (ecb128_f) rv64i_zvkned_ecb_decrypt;
}
}
/* Zvkned supports aes-128/192/256 encryption and decryption. */