mirror/openssl
2
0
Fork 0
mirror of https://github.com/openssl/openssl.git synced 2025-02-17 14:32:04 +08:00
Code Issues Packages Projects Releases Wiki Activity

riscv: Fix remaining asm checks

Browse Source 
There are additional asm checks which don't check for OPENSSL_CPUID_OBJ
causing the build to still fail on riscv [1], so fix them in the same
manner as ff27959769

[1] https://bugs.gentoo.org/923956
Fixes: https://github.com/openssl/openssl/issues/22871

Reviewed-by: Shane Lontis <shane.lontis@oracle.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/23752)

(cherry picked from commit daf1f8d64f)
This commit is contained in:
Jakov Smolić 2024-03-05 16:43:11 +01:00 committed by Tomas Mraz
parent 53ef123f48
commit 347f05e893
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
providers/implementations/ciphers/cipher_aes_gcm_hw.c
View File

@ -142,9 +142,9 @@ static const PROV_GCM_HW aes_gcm = {
# include "cipher_aes_gcm_hw_armv8.inc"
#elif defined(PPC_AES_GCM_CAPABLE) && defined(_ARCH_PPC64)
# include "cipher_aes_gcm_hw_ppc.inc"
#elif defined(__riscv) && __riscv_xlen == 64
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
# include "cipher_aes_gcm_hw_rv64i.inc"
#elif defined(__riscv) && __riscv_xlen == 32
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 32
# include "cipher_aes_gcm_hw_rv32i.inc"
#else
const PROV_GCM_HW *ossl_prov_aes_hw_gcm(size_t keybits)

4
providers/implementations/ciphers/cipher_aes_hw.c
View File

@ -142,9 +142,9 @@ const PROV_CIPHER_HW *ossl_prov_cipher_hw_aes_##mode(size_t keybits) \
# include "cipher_aes_hw_t4.inc"
#elif defined(S390X_aes_128_CAPABLE)
# include "cipher_aes_hw_s390x.inc"
#elif defined(__riscv) && __riscv_xlen == 64
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
# include "cipher_aes_hw_rv64i.inc"
#elif defined(__riscv) && __riscv_xlen == 32
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 32
# include "cipher_aes_hw_rv32i.inc"
#elif defined (ARMv8_HWAES_CAPABLE)
# include "cipher_aes_hw_armv8.inc"

4
providers/implementations/ciphers/cipher_aes_ocb_hw.c
View File

@ -104,7 +104,7 @@ static const PROV_CIPHER_HW aes_t4_ocb = { \
if (SPARC_AES_CAPABLE) \
return &aes_t4_ocb;
#elif defined(__riscv) && __riscv_xlen == 64
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
static int cipher_hw_aes_ocb_rv64i_zknd_zkne_initkey(PROV_CIPHER_CTX *vctx,
const unsigned char *key,
@ -152,7 +152,7 @@ static const PROV_CIPHER_HW aes_rv64i_zvkned_ocb = { \
else if (RISCV_HAS_ZKND_AND_ZKNE()) \
return &aes_rv64i_zknd_zkne_ocb;
#elif defined(__riscv) && __riscv_xlen == 32
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 32
static int cipher_hw_aes_ocb_rv32i_zknd_zkne_initkey(PROV_CIPHER_CTX *vctx,
const unsigned char *key,

4
providers/implementations/ciphers/cipher_aes_xts_hw.c
View File

@ -159,7 +159,7 @@ static const PROV_CIPHER_HW aes_xts_t4 = { \
if (SPARC_AES_CAPABLE) \
return &aes_xts_t4;
#elif defined(__riscv) && __riscv_xlen == 64
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
static int cipher_hw_aes_xts_rv64i_zknd_zkne_initkey(PROV_CIPHER_CTX *ctx,
const unsigned char *key,
@ -245,7 +245,7 @@ if (RISCV_HAS_ZVKNED() && riscv_vlen() >= 128) \
else if (RISCV_HAS_ZKND_AND_ZKNE()) \
return &aes_xts_rv64i_zknd_zkne;
#elif defined(__riscv) && __riscv_xlen == 32
#elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 32
static int cipher_hw_aes_xts_rv32i_zknd_zkne_initkey(PROV_CIPHER_CTX *ctx,
const unsigned char *key,