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openssl/crypto/sm3/build.info

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SM3: Add SM3 hash function SM3 is a secure hash function which is part of the Chinese "Commercial Cryptography" suite of algorithms which use is required for certain commercial applications in China. Reviewed-by: Paul Dale <paul.dale@oracle.com> Reviewed-by: Richard Levitte <levitte@openssl.org> (Merged from https://github.com/openssl/openssl/pull/4616)
2017-10-26 01:19:02 +08:00
LIBS=../../libcrypto
Cleanup legacy digest methods. Macros have been added to generate the simple legacy methods. Engines and EVP_MD_METH_get methods still require access to the old legacy methods, so they needed to be added back in. They may only be removed after engines are deprecated and removed. Removed some unnecessary #includes and #ifndef guards (which are done in build.info instead). Reviewed-by: Richard Levitte <levitte@openssl.org> (Merged from https://github.com/openssl/openssl/pull/10602)
2019-12-18 12:46:01 +08:00
IF[{- !$disabled{sm3} -}]
SM3 acceleration with SM3 hardware instruction on aarch64 SM3 hardware instruction is optional feature of crypto extension for aarch64. This implementation accelerates SM3 via SM3 instructions. For the platform not supporting SM3 instruction, the original C implementation still works. Thanks to AliBaba for testing and reporting the following perf numbers for Yitian710: Benchmark on T-Head Yitian-710 2.75GHz: Before: type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes sm3 49297.82k 121062.63k 223106.05k 283371.52k 307574.10k 309400.92k After (33% - 74% faster): type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes sm3 65640.01k 179121.79k 359854.59k 481448.96k 534055.59k 538274.47k Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/17454)
2021-12-24 16:29:04 +08:00
IF[{- !$disabled{asm} -}]
$SM3ASM_aarch64=sm3-armv8.S
$SM3DEF_aarch64=OPENSSL_SM3_ASM
riscv: SM3: Provide a Zvksh-based implementation The upcoming RISC-V vector crypto extensions feature a Zvksh extension, that provides SM3-specific istructions. This patch provides an implementation that utilizes this extension if available. Tested on QEMU and no regressions observed. Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
2023-01-27 23:47:41 +08:00
$SM3ASM_riscv64=sm3_riscv.c sm3-riscv64-zvksh.S
$SM3DEF_riscv64=OPENSSL_SM3_ASM
SM3 acceleration with SM3 hardware instruction on aarch64 SM3 hardware instruction is optional feature of crypto extension for aarch64. This implementation accelerates SM3 via SM3 instructions. For the platform not supporting SM3 instruction, the original C implementation still works. Thanks to AliBaba for testing and reporting the following perf numbers for Yitian710: Benchmark on T-Head Yitian-710 2.75GHz: Before: type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes sm3 49297.82k 121062.63k 223106.05k 283371.52k 307574.10k 309400.92k After (33% - 74% faster): type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes sm3 65640.01k 179121.79k 359854.59k 481448.96k 534055.59k 538274.47k Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/17454)
2021-12-24 16:29:04 +08:00
# Now that we have defined all the arch specific variables, use the
# appropriate ones, and define the appropriate macros
IF[$SM3ASM_{- $target{asm_arch} -}]
$SM3ASM=$SM3ASM_{- $target{asm_arch} -}
$SM3DEF=$SM3DEF_{- $target{asm_arch} -}
ENDIF
ENDIF
SOURCE[../../libcrypto]=sm3.c legacy_sm3.c $SM3ASM
DEFINE[../../libcrypto]=$SM3DEF
GENERATE[sm3-armv8.S]=asm/sm3-armv8.pl
INCLUDE[sm3-armv8.o]=..
riscv: SM3: Provide a Zvksh-based implementation The upcoming RISC-V vector crypto extensions feature a Zvksh extension, that provides SM3-specific istructions. This patch provides an implementation that utilizes this extension if available. Tested on QEMU and no regressions observed. Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
2023-01-27 23:47:41 +08:00
GENERATE[sm3-riscv64-zvksh.S]=asm/sm3-riscv64-zvksh.pl
SM3 acceleration with SM3 hardware instruction on aarch64 SM3 hardware instruction is optional feature of crypto extension for aarch64. This implementation accelerates SM3 via SM3 instructions. For the platform not supporting SM3 instruction, the original C implementation still works. Thanks to AliBaba for testing and reporting the following perf numbers for Yitian710: Benchmark on T-Head Yitian-710 2.75GHz: Before: type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes sm3 49297.82k 121062.63k 223106.05k 283371.52k 307574.10k 309400.92k After (33% - 74% faster): type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 16384 bytes sm3 65640.01k 179121.79k 359854.59k 481448.96k 534055.59k 538274.47k Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/17454)
2021-12-24 16:29:04 +08:00
ENDIF
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