2016-05-18 02:51:26 +08:00
|
|
|
/*
|
2022-05-03 18:52:38 +08:00
|
|
|
* Copyright 2011-2022 The OpenSSL Project Authors. All Rights Reserved.
|
2016-05-18 02:51:26 +08:00
|
|
|
*
|
2018-12-06 21:03:01 +08:00
|
|
|
* Licensed under the Apache License 2.0 (the "License"). You may not use
|
2016-05-18 02:51:26 +08:00
|
|
|
* this file except in compliance with the License. You can obtain a copy
|
|
|
|
* in the file LICENSE in the source distribution or at
|
|
|
|
* https://www.openssl.org/source/license.html
|
|
|
|
*/
|
|
|
|
|
2011-07-18 01:40:29 +08:00
|
|
|
#include <stdio.h>
|
|
|
|
#include <stdlib.h>
|
|
|
|
#include <string.h>
|
|
|
|
#include <setjmp.h>
|
|
|
|
#include <signal.h>
|
2015-04-02 16:17:42 +08:00
|
|
|
#include <openssl/crypto.h>
|
2021-04-20 04:26:50 +08:00
|
|
|
#ifdef __APPLE__
|
|
|
|
#include <sys/sysctl.h>
|
|
|
|
#endif
|
2017-11-20 00:40:56 +08:00
|
|
|
#include "internal/cryptlib.h"
|
2022-10-28 02:07:48 +08:00
|
|
|
#ifndef _WIN32
|
2021-05-20 02:54:20 +08:00
|
|
|
#include <unistd.h>
|
2022-10-28 02:07:48 +08:00
|
|
|
#else
|
|
|
|
#include <windows.h>
|
|
|
|
#endif
|
2011-07-18 01:40:29 +08:00
|
|
|
#include "arm_arch.h"
|
|
|
|
|
2015-01-22 11:40:55 +08:00
|
|
|
unsigned int OPENSSL_armcap_P = 0;
|
2020-04-28 10:33:50 +08:00
|
|
|
unsigned int OPENSSL_arm_midr = 0;
|
2021-03-19 14:45:57 +08:00
|
|
|
unsigned int OPENSSL_armv8_rsa_neonized = 0;
|
2011-07-18 01:40:29 +08:00
|
|
|
|
2022-10-28 02:07:48 +08:00
|
|
|
#ifdef _WIN32
|
|
|
|
void OPENSSL_cpuid_setup(void)
|
|
|
|
{
|
|
|
|
OPENSSL_armcap_P |= ARMV7_NEON;
|
|
|
|
OPENSSL_armv8_rsa_neonized = 1;
|
|
|
|
if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) {
|
|
|
|
// These are all covered by one call in Windows
|
|
|
|
OPENSSL_armcap_P |= ARMV8_AES;
|
|
|
|
OPENSSL_armcap_P |= ARMV8_PMULL;
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA1;
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA256;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t OPENSSL_rdtsc(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#elif __ARM_MAX_ARCH__<7
|
2015-01-22 11:40:55 +08:00
|
|
|
void OPENSSL_cpuid_setup(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2017-11-20 00:40:56 +08:00
|
|
|
uint32_t OPENSSL_rdtsc(void)
|
2015-01-22 11:40:55 +08:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2014-11-08 05:48:22 +08:00
|
|
|
#else
|
2011-07-18 01:40:29 +08:00
|
|
|
static sigset_t all_masked;
|
|
|
|
|
|
|
|
static sigjmp_buf ill_jmp;
|
2015-01-22 11:40:55 +08:00
|
|
|
static void ill_handler(int sig)
|
|
|
|
{
|
|
|
|
siglongjmp(ill_jmp, sig);
|
|
|
|
}
|
2011-07-18 01:40:29 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Following subroutines could have been inlined, but it's not all
|
|
|
|
* ARM compilers support inline assembler...
|
|
|
|
*/
|
|
|
|
void _armv7_neon_probe(void);
|
2014-05-04 16:55:49 +08:00
|
|
|
void _armv8_aes_probe(void);
|
|
|
|
void _armv8_sha1_probe(void);
|
|
|
|
void _armv8_sha256_probe(void);
|
|
|
|
void _armv8_pmull_probe(void);
|
2018-02-11 19:29:06 +08:00
|
|
|
# ifdef __aarch64__
|
2021-12-24 16:29:04 +08:00
|
|
|
void _armv8_sm3_probe(void);
|
2021-10-20 05:49:05 +08:00
|
|
|
void _armv8_sm4_probe(void);
|
2022-12-03 20:58:43 +08:00
|
|
|
void _armv8_eor3_probe(void);
|
2018-02-11 19:29:06 +08:00
|
|
|
void _armv8_sha512_probe(void);
|
2020-04-28 10:33:50 +08:00
|
|
|
unsigned int _armv8_cpuid_probe(void);
|
2022-02-07 18:17:06 +08:00
|
|
|
void _armv8_sve_probe(void);
|
|
|
|
void _armv8_sve2_probe(void);
|
2021-05-20 02:54:20 +08:00
|
|
|
void _armv8_rng_probe(void);
|
|
|
|
|
|
|
|
size_t OPENSSL_rndr_asm(unsigned char *buf, size_t len);
|
|
|
|
size_t OPENSSL_rndrrs_asm(unsigned char *buf, size_t len);
|
|
|
|
|
|
|
|
size_t OPENSSL_rndr_bytes(unsigned char *buf, size_t len);
|
|
|
|
size_t OPENSSL_rndrrs_bytes(unsigned char *buf, size_t len);
|
|
|
|
|
|
|
|
static size_t OPENSSL_rndr_wrapper(size_t (*func)(unsigned char *, size_t), unsigned char *buf, size_t len)
|
|
|
|
{
|
2021-12-28 12:13:21 +08:00
|
|
|
size_t buffer_size = 0;
|
2021-05-20 02:54:20 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
buffer_size = func(buf, len);
|
|
|
|
if (buffer_size == len)
|
|
|
|
break;
|
|
|
|
usleep(5000); /* 5000 microseconds (5 milliseconds) */
|
|
|
|
}
|
|
|
|
return buffer_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
size_t OPENSSL_rndr_bytes(unsigned char *buf, size_t len)
|
|
|
|
{
|
|
|
|
return OPENSSL_rndr_wrapper(OPENSSL_rndr_asm, buf, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
size_t OPENSSL_rndrrs_bytes(unsigned char *buf, size_t len)
|
|
|
|
{
|
|
|
|
return OPENSSL_rndr_wrapper(OPENSSL_rndrrs_asm, buf, len);
|
|
|
|
}
|
2018-02-11 19:29:06 +08:00
|
|
|
# endif
|
2017-11-20 00:40:56 +08:00
|
|
|
uint32_t _armv7_tick(void);
|
2011-07-18 01:40:29 +08:00
|
|
|
|
2017-11-20 00:40:56 +08:00
|
|
|
uint32_t OPENSSL_rdtsc(void)
|
2015-01-22 11:40:55 +08:00
|
|
|
{
|
|
|
|
if (OPENSSL_armcap_P & ARMV7_TICK)
|
|
|
|
return _armv7_tick();
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
2011-07-18 01:40:29 +08:00
|
|
|
|
2015-01-05 18:25:10 +08:00
|
|
|
# if defined(__GNUC__) && __GNUC__>=2
|
|
|
|
void OPENSSL_cpuid_setup(void) __attribute__ ((constructor));
|
|
|
|
# endif
|
2019-01-16 13:31:15 +08:00
|
|
|
|
|
|
|
# if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
|
|
|
|
# if __GLIBC_PREREQ(2, 16)
|
|
|
|
# include <sys/auxv.h>
|
|
|
|
# define OSSL_IMPLEMENT_GETAUXVAL
|
|
|
|
# endif
|
2021-06-23 09:46:42 +08:00
|
|
|
# elif defined(__ANDROID_API__)
|
|
|
|
/* see https://developer.android.google.cn/ndk/guides/cpu-features */
|
|
|
|
# if __ANDROID_API__ >= 18
|
|
|
|
# include <sys/auxv.h>
|
|
|
|
# define OSSL_IMPLEMENT_GETAUXVAL
|
|
|
|
# endif
|
2015-01-22 11:40:55 +08:00
|
|
|
# endif
|
2020-12-10 04:23:32 +08:00
|
|
|
# if defined(__FreeBSD__)
|
|
|
|
# include <sys/param.h>
|
|
|
|
# if __FreeBSD_version >= 1200000
|
|
|
|
# include <sys/auxv.h>
|
|
|
|
# define OSSL_IMPLEMENT_GETAUXVAL
|
|
|
|
|
|
|
|
static unsigned long getauxval(unsigned long key)
|
|
|
|
{
|
|
|
|
unsigned long val = 0ul;
|
|
|
|
|
|
|
|
if (elf_aux_info((int)key, &val, sizeof(val)) != 0)
|
|
|
|
return 0ul;
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
# endif
|
|
|
|
# endif
|
2014-06-01 23:21:06 +08:00
|
|
|
|
2020-03-05 18:26:06 +08:00
|
|
|
/*
|
|
|
|
* Android: according to https://developer.android.com/ndk/guides/cpu-features,
|
|
|
|
* getauxval is supported starting with API level 18
|
|
|
|
*/
|
|
|
|
# if defined(__ANDROID__) && defined(__ANDROID_API__) && __ANDROID_API__ >= 18
|
|
|
|
# include <sys/auxv.h>
|
|
|
|
# define OSSL_IMPLEMENT_GETAUXVAL
|
|
|
|
# endif
|
|
|
|
|
2014-06-01 23:21:06 +08:00
|
|
|
/*
|
2017-08-04 13:10:41 +08:00
|
|
|
* ARM puts the feature bits for Crypto Extensions in AT_HWCAP2, whereas
|
2014-06-01 23:21:06 +08:00
|
|
|
* AArch64 used AT_HWCAP.
|
|
|
|
*/
|
2021-11-19 23:14:30 +08:00
|
|
|
# ifndef AT_HWCAP
|
|
|
|
# define AT_HWCAP 16
|
|
|
|
# endif
|
|
|
|
# ifndef AT_HWCAP2
|
|
|
|
# define AT_HWCAP2 26
|
|
|
|
# endif
|
2015-01-22 11:40:55 +08:00
|
|
|
# if defined(__arm__) || defined (__arm)
|
2021-11-19 23:14:30 +08:00
|
|
|
# define HWCAP AT_HWCAP
|
2015-01-22 11:40:55 +08:00
|
|
|
# define HWCAP_NEON (1 << 12)
|
|
|
|
|
2021-11-19 23:14:30 +08:00
|
|
|
# define HWCAP_CE AT_HWCAP2
|
2015-01-22 11:40:55 +08:00
|
|
|
# define HWCAP_CE_AES (1 << 0)
|
|
|
|
# define HWCAP_CE_PMULL (1 << 1)
|
|
|
|
# define HWCAP_CE_SHA1 (1 << 2)
|
|
|
|
# define HWCAP_CE_SHA256 (1 << 3)
|
|
|
|
# elif defined(__aarch64__)
|
2021-11-19 23:14:30 +08:00
|
|
|
# define HWCAP AT_HWCAP
|
2015-01-22 11:40:55 +08:00
|
|
|
# define HWCAP_NEON (1 << 1)
|
|
|
|
|
|
|
|
# define HWCAP_CE HWCAP
|
|
|
|
# define HWCAP_CE_AES (1 << 3)
|
|
|
|
# define HWCAP_CE_PMULL (1 << 4)
|
|
|
|
# define HWCAP_CE_SHA1 (1 << 5)
|
|
|
|
# define HWCAP_CE_SHA256 (1 << 6)
|
2020-04-28 10:33:50 +08:00
|
|
|
# define HWCAP_CPUID (1 << 11)
|
2021-06-09 14:35:46 +08:00
|
|
|
# define HWCAP_SHA3 (1 << 17)
|
2021-12-24 16:29:04 +08:00
|
|
|
# define HWCAP_CE_SM3 (1 << 18)
|
2021-10-20 05:49:05 +08:00
|
|
|
# define HWCAP_CE_SM4 (1 << 19)
|
2018-02-11 19:29:06 +08:00
|
|
|
# define HWCAP_CE_SHA512 (1 << 21)
|
2022-02-07 18:17:06 +08:00
|
|
|
# define HWCAP_SVE (1 << 22)
|
2021-05-20 02:54:20 +08:00
|
|
|
/* AT_HWCAP2 */
|
|
|
|
# define HWCAP2 26
|
2022-02-07 18:17:06 +08:00
|
|
|
# define HWCAP2_SVE2 (1 << 1)
|
2021-05-20 02:54:20 +08:00
|
|
|
# define HWCAP2_RNG (1 << 16)
|
2015-01-22 11:40:55 +08:00
|
|
|
# endif
|
2014-06-01 23:21:06 +08:00
|
|
|
|
2011-07-18 01:40:29 +08:00
|
|
|
void OPENSSL_cpuid_setup(void)
|
2015-01-22 11:40:55 +08:00
|
|
|
{
|
2017-06-11 21:38:05 +08:00
|
|
|
const char *e;
|
2015-01-22 11:40:55 +08:00
|
|
|
struct sigaction ill_oact, ill_act;
|
|
|
|
sigset_t oset;
|
|
|
|
static int trigger = 0;
|
|
|
|
|
|
|
|
if (trigger)
|
|
|
|
return;
|
|
|
|
trigger = 1;
|
|
|
|
|
2021-05-26 23:46:00 +08:00
|
|
|
OPENSSL_armcap_P = 0;
|
|
|
|
|
2015-01-22 11:40:55 +08:00
|
|
|
if ((e = getenv("OPENSSL_armcap"))) {
|
|
|
|
OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2021-04-20 04:26:50 +08:00
|
|
|
# if defined(__APPLE__)
|
|
|
|
# if !defined(__aarch64__)
|
2017-02-15 19:01:09 +08:00
|
|
|
/*
|
|
|
|
* Capability probing by catching SIGILL appears to be problematic
|
|
|
|
* on iOS. But since Apple universe is "monocultural", it's actually
|
|
|
|
* possible to simply set pre-defined processor capability mask.
|
|
|
|
*/
|
|
|
|
if (1) {
|
|
|
|
OPENSSL_armcap_P = ARMV7_NEON;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* One could do same even for __aarch64__ iOS builds. It's not done
|
|
|
|
* exclusively for reasons of keeping code unified across platforms.
|
|
|
|
* Unified code works because it never triggers SIGILL on Apple
|
|
|
|
* devices...
|
|
|
|
*/
|
2021-04-20 04:26:50 +08:00
|
|
|
# else
|
|
|
|
{
|
2021-06-09 14:35:46 +08:00
|
|
|
unsigned int feature;
|
|
|
|
size_t len = sizeof(feature);
|
|
|
|
char uarch[64];
|
2021-04-20 04:26:50 +08:00
|
|
|
|
2021-06-09 14:35:46 +08:00
|
|
|
if (sysctlbyname("hw.optional.armv8_2_sha512", &feature, &len, NULL, 0) == 0 && feature == 1)
|
2021-04-20 04:26:50 +08:00
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA512;
|
2021-06-09 14:35:46 +08:00
|
|
|
feature = 0;
|
|
|
|
if (sysctlbyname("hw.optional.armv8_2_sha3", &feature, &len, NULL, 0) == 0 && feature == 1) {
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA3;
|
|
|
|
len = sizeof(uarch);
|
|
|
|
if ((sysctlbyname("machdep.cpu.brand_string", uarch, &len, NULL, 0) == 0) &&
|
|
|
|
(strncmp(uarch, "Apple M1", 8) == 0))
|
|
|
|
OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;
|
|
|
|
}
|
2021-04-20 04:26:50 +08:00
|
|
|
}
|
|
|
|
# endif
|
2017-02-15 19:01:09 +08:00
|
|
|
# endif
|
|
|
|
|
2019-01-16 13:31:15 +08:00
|
|
|
# ifdef OSSL_IMPLEMENT_GETAUXVAL
|
|
|
|
if (getauxval(HWCAP) & HWCAP_NEON) {
|
|
|
|
unsigned long hwcap = getauxval(HWCAP_CE);
|
|
|
|
|
|
|
|
OPENSSL_armcap_P |= ARMV7_NEON;
|
|
|
|
|
|
|
|
if (hwcap & HWCAP_CE_AES)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_AES;
|
|
|
|
|
|
|
|
if (hwcap & HWCAP_CE_PMULL)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_PMULL;
|
|
|
|
|
|
|
|
if (hwcap & HWCAP_CE_SHA1)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA1;
|
|
|
|
|
|
|
|
if (hwcap & HWCAP_CE_SHA256)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA256;
|
|
|
|
|
|
|
|
# ifdef __aarch64__
|
2021-10-20 05:49:05 +08:00
|
|
|
if (hwcap & HWCAP_CE_SM4)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SM4;
|
|
|
|
|
2019-01-16 13:31:15 +08:00
|
|
|
if (hwcap & HWCAP_CE_SHA512)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA512;
|
2020-04-28 10:33:50 +08:00
|
|
|
|
|
|
|
if (hwcap & HWCAP_CPUID)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_CPUID;
|
2021-12-24 16:29:04 +08:00
|
|
|
|
|
|
|
if (hwcap & HWCAP_CE_SM3)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SM3;
|
2021-06-09 14:35:46 +08:00
|
|
|
if (hwcap & HWCAP_SHA3)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA3;
|
2019-01-16 13:31:15 +08:00
|
|
|
# endif
|
|
|
|
}
|
2021-05-20 02:54:20 +08:00
|
|
|
# ifdef __aarch64__
|
2022-02-07 18:17:06 +08:00
|
|
|
if (getauxval(HWCAP) & HWCAP_SVE)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SVE;
|
|
|
|
|
|
|
|
if (getauxval(HWCAP2) & HWCAP2_SVE2)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SVE2;
|
|
|
|
|
2021-05-20 02:54:20 +08:00
|
|
|
if (getauxval(HWCAP2) & HWCAP2_RNG)
|
|
|
|
OPENSSL_armcap_P |= ARMV8_RNG;
|
|
|
|
# endif
|
2019-01-16 13:31:15 +08:00
|
|
|
# endif
|
|
|
|
|
2015-01-22 11:40:55 +08:00
|
|
|
sigfillset(&all_masked);
|
|
|
|
sigdelset(&all_masked, SIGILL);
|
|
|
|
sigdelset(&all_masked, SIGTRAP);
|
|
|
|
sigdelset(&all_masked, SIGFPE);
|
|
|
|
sigdelset(&all_masked, SIGBUS);
|
|
|
|
sigdelset(&all_masked, SIGSEGV);
|
|
|
|
|
|
|
|
memset(&ill_act, 0, sizeof(ill_act));
|
|
|
|
ill_act.sa_handler = ill_handler;
|
|
|
|
ill_act.sa_mask = all_masked;
|
|
|
|
|
|
|
|
sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
|
|
|
|
sigaction(SIGILL, &ill_act, &ill_oact);
|
|
|
|
|
2019-01-16 13:31:15 +08:00
|
|
|
/* If we used getauxval, we already have all the values */
|
|
|
|
# ifndef OSSL_IMPLEMENT_GETAUXVAL
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
2015-01-22 11:40:55 +08:00
|
|
|
_armv7_neon_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV7_NEON;
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_pmull_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_PMULL | ARMV8_AES;
|
|
|
|
} else if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_aes_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_AES;
|
|
|
|
}
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_sha1_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA1;
|
|
|
|
}
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_sha256_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA256;
|
|
|
|
}
|
2019-01-16 13:31:15 +08:00
|
|
|
# if defined(__aarch64__) && !defined(__APPLE__)
|
2018-02-11 19:29:06 +08:00
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
2021-10-20 05:49:05 +08:00
|
|
|
_armv8_sm4_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SM4;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
2018-02-11 19:29:06 +08:00
|
|
|
_armv8_sha512_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA512;
|
|
|
|
}
|
2021-12-24 16:29:04 +08:00
|
|
|
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_sm3_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SM3;
|
2022-12-03 20:58:43 +08:00
|
|
|
}
|
2021-06-09 14:35:46 +08:00
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_eor3_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SHA3;
|
2021-12-24 16:29:04 +08:00
|
|
|
}
|
2019-01-16 13:31:15 +08:00
|
|
|
# endif
|
2015-01-22 11:40:55 +08:00
|
|
|
}
|
2021-05-20 02:54:20 +08:00
|
|
|
# ifdef __aarch64__
|
2022-02-07 18:17:06 +08:00
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_sve_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SVE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_sve2_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_SVE2;
|
|
|
|
}
|
|
|
|
|
2021-05-20 02:54:20 +08:00
|
|
|
if (sigsetjmp(ill_jmp, 1) == 0) {
|
|
|
|
_armv8_rng_probe();
|
|
|
|
OPENSSL_armcap_P |= ARMV8_RNG;
|
|
|
|
}
|
|
|
|
# endif
|
2019-01-16 13:31:15 +08:00
|
|
|
# endif
|
|
|
|
|
2022-07-23 10:04:46 +08:00
|
|
|
/*
|
|
|
|
* Probing for ARMV7_TICK is known to produce unreliable results,
|
|
|
|
* so we will only use the feature when the user explicitly enables
|
|
|
|
* it with OPENSSL_armcap.
|
|
|
|
*/
|
2015-01-22 11:40:55 +08:00
|
|
|
|
|
|
|
sigaction(SIGILL, &ill_oact, NULL);
|
|
|
|
sigprocmask(SIG_SETMASK, &oset, NULL);
|
2020-04-28 10:33:50 +08:00
|
|
|
|
|
|
|
# ifdef __aarch64__
|
|
|
|
if (OPENSSL_armcap_P & ARMV8_CPUID)
|
|
|
|
OPENSSL_arm_midr = _armv8_cpuid_probe();
|
2021-03-19 14:45:57 +08:00
|
|
|
|
|
|
|
if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) ||
|
|
|
|
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)) &&
|
|
|
|
(OPENSSL_armcap_P & ARMV7_NEON)) {
|
|
|
|
OPENSSL_armv8_rsa_neonized = 1;
|
|
|
|
}
|
2022-05-18 10:27:55 +08:00
|
|
|
if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) ||
|
|
|
|
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2)) &&
|
2021-06-09 14:35:46 +08:00
|
|
|
(OPENSSL_armcap_P & ARMV8_SHA3))
|
|
|
|
OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;
|
2020-04-28 10:33:50 +08:00
|
|
|
# endif
|
2015-01-22 11:40:55 +08:00
|
|
|
}
|
2014-11-08 05:48:22 +08:00
|
|
|
#endif
|