2016-05-18 02:51:26 +08:00
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/*
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2022-05-03 18:52:38 +08:00
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* Copyright 2011-2022 The OpenSSL Project Authors. All Rights Reserved.
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2016-05-18 02:51:26 +08:00
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*
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2018-12-06 21:03:01 +08:00
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* Licensed under the Apache License 2.0 (the "License"). You may not use
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2016-05-18 02:51:26 +08:00
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* this file except in compliance with the License. You can obtain a copy
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* in the file LICENSE in the source distribution or at
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* https://www.openssl.org/source/license.html
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*/
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2019-09-28 06:45:57 +08:00
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#ifndef OSSL_CRYPTO_ARM_ARCH_H
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# define OSSL_CRYPTO_ARM_ARCH_H
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2011-04-02 05:09:09 +08:00
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2015-01-22 11:40:55 +08:00
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# if !defined(__ARM_ARCH__)
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# if defined(__CC_ARM)
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# define __ARM_ARCH__ __TARGET_ARCH_ARM
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# if defined(__BIG_ENDIAN)
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2014-06-01 23:21:06 +08:00
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# define __ARMEB__
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# else
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# define __ARMEL__
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# endif
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2015-01-22 11:40:55 +08:00
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# elif defined(__GNUC__)
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# if defined(__aarch64__)
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# define __ARM_ARCH__ 8
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2011-04-02 05:09:09 +08:00
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/*
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* Why doesn't gcc define __ARM_ARCH__? Instead it defines
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2017-11-12 08:03:10 +08:00
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* bunch of below macros. See all_architectures[] table in
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2011-04-02 05:09:09 +08:00
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* gcc/config/arm/arm.c. On a side note it defines
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* __ARMEL__/__ARMEB__ for little-/big-endian.
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*/
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2015-01-22 11:40:55 +08:00
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# elif defined(__ARM_ARCH)
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# define __ARM_ARCH__ __ARM_ARCH
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# elif defined(__ARM_ARCH_8A__)
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# define __ARM_ARCH__ 8
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# elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
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defined(__ARM_ARCH_7R__)|| defined(__ARM_ARCH_7M__) || \
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defined(__ARM_ARCH_7EM__)
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# define __ARM_ARCH__ 7
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# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6K__)|| defined(__ARM_ARCH_6M__) || \
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defined(__ARM_ARCH_6Z__)|| defined(__ARM_ARCH_6ZK__) || \
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defined(__ARM_ARCH_6T2__)
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# define __ARM_ARCH__ 6
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# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || \
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defined(__ARM_ARCH_5E__)|| defined(__ARM_ARCH_5TE__) || \
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defined(__ARM_ARCH_5TEJ__)
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# define __ARM_ARCH__ 5
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# elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
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# define __ARM_ARCH__ 4
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# else
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# error "unsupported ARM architecture"
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# endif
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2011-04-02 05:09:09 +08:00
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# endif
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# endif
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2015-01-22 11:40:55 +08:00
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# if !defined(__ARM_MAX_ARCH__)
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# define __ARM_MAX_ARCH__ __ARM_ARCH__
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# endif
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2014-11-08 05:48:22 +08:00
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2015-01-22 11:40:55 +08:00
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# if __ARM_MAX_ARCH__<__ARM_ARCH__
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# error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
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# elif __ARM_MAX_ARCH__!=__ARM_ARCH__
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# if __ARM_ARCH__<7 && __ARM_MAX_ARCH__>=7 && defined(__ARMEB__)
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# error "can't build universal big-endian binary"
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# endif
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2014-11-08 05:48:22 +08:00
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# endif
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2018-04-20 02:56:46 +08:00
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# ifndef __ASSEMBLER__
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2011-07-18 01:40:29 +08:00
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extern unsigned int OPENSSL_armcap_P;
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2020-04-28 10:33:50 +08:00
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extern unsigned int OPENSSL_arm_midr;
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2021-05-11 17:37:22 +08:00
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extern unsigned int OPENSSL_armv8_rsa_neonized;
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2015-01-22 11:40:55 +08:00
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# endif
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# define ARMV7_NEON (1<<0)
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# define ARMV7_TICK (1<<1)
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# define ARMV8_AES (1<<2)
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# define ARMV8_SHA1 (1<<3)
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# define ARMV8_SHA256 (1<<4)
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# define ARMV8_PMULL (1<<5)
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2018-02-11 19:29:06 +08:00
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# define ARMV8_SHA512 (1<<6)
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2020-04-28 10:33:50 +08:00
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# define ARMV8_CPUID (1<<7)
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2021-05-20 02:54:20 +08:00
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# define ARMV8_RNG (1<<8)
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2021-12-24 16:29:04 +08:00
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# define ARMV8_SM3 (1<<9)
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2021-10-20 05:49:05 +08:00
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# define ARMV8_SM4 (1<<10)
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2021-06-09 14:35:46 +08:00
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# define ARMV8_SHA3 (1<<11)
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# define ARMV8_UNROLL8_EOR3 (1<<12)
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2022-02-07 18:17:06 +08:00
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# define ARMV8_SVE (1<<13)
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# define ARMV8_SVE2 (1<<14)
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2011-07-18 01:40:29 +08:00
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2020-04-28 10:33:50 +08:00
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/*
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* MIDR_EL1 system register
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*
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* 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
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* | | | | | | |
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* |RES0 | Implementer | Variant | Arch | PartNum |Revision|
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* |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
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*
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*/
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# define ARM_CPU_IMP_ARM 0x41
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2022-10-31 11:28:15 +08:00
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# define HISI_CPU_IMP 0x48
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2020-04-28 10:33:50 +08:00
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# define ARM_CPU_PART_CORTEX_A72 0xD08
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# define ARM_CPU_PART_N1 0xD0C
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2021-06-09 14:35:46 +08:00
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# define ARM_CPU_PART_V1 0xD40
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2022-05-18 10:27:55 +08:00
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# define ARM_CPU_PART_N2 0xD49
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2022-10-31 11:28:15 +08:00
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# define HISI_CPU_PART_KP920 0xD01
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2023-01-29 14:22:43 +08:00
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# define ARM_CPU_PART_V2 0xD4F
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2020-04-28 10:33:50 +08:00
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# define MIDR_PARTNUM_SHIFT 4
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2022-07-18 17:24:47 +08:00
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# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
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2020-04-28 10:33:50 +08:00
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# define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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# define MIDR_IMPLEMENTER_SHIFT 24
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2022-07-18 17:24:47 +08:00
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# define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
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2020-04-28 10:33:50 +08:00
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# define MIDR_IMPLEMENTER(midr) \
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(((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
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# define MIDR_ARCHITECTURE_SHIFT 16
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2022-07-18 17:24:47 +08:00
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# define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
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2020-04-28 10:33:50 +08:00
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# define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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# define MIDR_CPU_MODEL_MASK \
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(MIDR_IMPLEMENTER_MASK | \
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MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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# define MIDR_CPU_MODEL(imp, partnum) \
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(((imp) << MIDR_IMPLEMENTER_SHIFT) | \
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2022-07-18 17:24:47 +08:00
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(0xfU << MIDR_ARCHITECTURE_SHIFT) | \
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2020-04-28 10:33:50 +08:00
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((partnum) << MIDR_PARTNUM_SHIFT))
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# define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
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(((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
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aarch64: support BTI and pointer authentication in assembly
This change adds optional support for
- Armv8.3-A Pointer Authentication (PAuth) and
- Armv8.5-A Branch Target Identification (BTI)
features to the perl scripts.
Both features can be enabled with additional compiler flags.
Unless any of these are enabled explicitly there is no code change at
all.
The extensions are briefly described below. Please read the appropriate
chapters of the Arm Architecture Reference Manual for the complete
specification.
Scope
-----
This change only affects generated assembly code.
Armv8.3-A Pointer Authentication
--------------------------------
Pointer Authentication extension supports the authentication of the
contents of registers before they are used for indirect branching
or load.
PAuth provides a probabilistic method to detect corruption of register
values. PAuth signing instructions generate a Pointer Authentication
Code (PAC) based on the value of a register, a seed and a key.
The generated PAC is inserted into the original value in the register.
A PAuth authentication instruction recomputes the PAC, and if it matches
the PAC in the register, restores its original value. In case of a
mismatch, an architecturally unmapped address is generated instead.
With PAuth, mitigation against ROP (Return-oriented Programming) attacks
can be implemented. This is achieved by signing the contents of the
link-register (LR) before it is pushed to stack. Once LR is popped,
it is authenticated. This way a stack corruption which overwrites the
LR on the stack is detectable.
The PAuth extension adds several new instructions, some of which are not
recognized by older hardware. To support a single codebase for both pre
Armv8.3-A targets and newer ones, only NOP-space instructions are added
by this patch. These instructions are treated as NOPs on hardware
which does not support Armv8.3-A. Furthermore, this patch only considers
cases where LR is saved to the stack and then restored before branching
to its content. There are cases in the code where LR is pushed to stack
but it is not used later. We do not address these cases as they are not
affected by PAuth.
There are two keys available to sign an instruction address: A and B.
PACIASP and PACIBSP only differ in the used keys: A and B, respectively.
The keys are typically managed by the operating system.
To enable generating code for PAuth compile with
-mbranch-protection=<mode>:
- standard or pac-ret: add PACIASP and AUTIASP, also enables BTI
(read below)
- pac-ret+b-key: add PACIBSP and AUTIBSP
Armv8.5-A Branch Target Identification
--------------------------------------
Branch Target Identification features some new instructions which
protect the execution of instructions on guarded pages which are not
intended branch targets.
If Armv8.5-A is supported by the hardware, execution of an instruction
changes the value of PSTATE.BTYPE field. If an indirect branch
lands on a guarded page the target instruction must be one of the
BTI <jc> flavors, or in case of a direct call or jump it can be any
other instruction. If the target instruction is not compatible with the
value of PSTATE.BTYPE a Branch Target Exception is generated.
In short, indirect jumps are compatible with BTI <j> and <jc> while
indirect calls are compatible with BTI <c> and <jc>. Please refer to the
specification for the details.
Armv8.3-A PACIASP and PACIBSP are implicit branch target
identification instructions which are equivalent with BTI c or BTI jc
depending on system register configuration.
BTI is used to mitigate JOP (Jump-oriented Programming) attacks by
limiting the set of instructions which can be jumped to.
BTI requires active linker support to mark the pages with BTI-enabled
code as guarded. For ELF64 files BTI compatibility is recorded in the
.note.gnu.property section. For a shared object or static binary it is
required that all linked units support BTI. This means that even a
single assembly file without the required note section turns-off BTI
for the whole binary or shared object.
The new BTI instructions are treated as NOPs on hardware which does
not support Armv8.5-A or on pages which are not guarded.
To insert this new and optional instruction compile with
-mbranch-protection=standard (also enables PAuth) or +bti.
When targeting a guarded page from a non-guarded page, weaker
compatibility restrictions apply to maintain compatibility between
legacy and new code. For detailed rules please refer to the Arm ARM.
Compiler support
----------------
Compiler support requires understanding '-mbranch-protection=<mode>'
and emitting the appropriate feature macros (__ARM_FEATURE_BTI_DEFAULT
and __ARM_FEATURE_PAC_DEFAULT). The current state is the following:
-------------------------------------------------------
| Compiler | -mbranch-protection | Feature macros |
+----------+---------------------+--------------------+
| clang | 9.0.0 | 11.0.0 |
+----------+---------------------+--------------------+
| gcc | 9 | expected in 10.1+ |
-------------------------------------------------------
Available Platforms
------------------
Arm Fast Model and QEMU support both extensions.
https://developer.arm.com/tools-and-software/simulation-models/fast-models
https://www.qemu.org/
Implementation Notes
--------------------
This change adds BTI landing pads even to assembly functions which are
likely to be directly called only. In these cases, landing pads might
be superfluous depending on what code the linker generates.
Code size and performance impact for these cases would be negligible.
Interaction with C code
-----------------------
Pointer Authentication is a per-frame protection while Branch Target
Identification can be turned on and off only for all code pages of a
whole shared object or static binary. Because of these properties if
C/C++ code is compiled without any of the above features but assembly
files support any of them unconditionally there is no incompatibility
between the two.
Useful Links
------------
To fully understand the details of both PAuth and BTI it is advised to
read the related chapters of the Arm Architecture Reference Manual
(Arm ARM):
https://developer.arm.com/documentation/ddi0487/latest/
Additional materials:
"Providing protection for complex software"
https://developer.arm.com/architectures/learn-the-architecture/providing-protection-for-complex-software
Arm Compiler Reference Guide Version 6.14: -mbranch-protection
https://developer.arm.com/documentation/101754/0614/armclang-Reference/armclang-Command-line-Options/-mbranch-protection?lang=en
Arm C Language Extensions (ACLE)
https://developer.arm.com/docs/101028/latest
Addional Notes
--------------
This patch is a copy of the work done by Tamas Petz in boringssl. It
contains the changes from the following commits:
aarch64: support BTI and pointer authentication in assembly
Change-Id: I4335f92e2ccc8e209c7d68a0a79f1acdf3aeb791
URL: https://boringssl-review.googlesource.com/c/boringssl/+/42084
aarch64: Improve conditional compilation
Change-Id: I14902a64e5f403c2b6a117bc9f5fb1a4f4611ebf
URL: https://boringssl-review.googlesource.com/c/boringssl/+/43524
aarch64: Fix name of gnu property note section
Change-Id: I6c432d1c852129e9c273f6469a8b60e3983671ec
URL: https://boringssl-review.googlesource.com/c/boringssl/+/44024
Change-Id: I2d95ebc5e4aeb5610d3b226f9754ee80cf74a9af
Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/16674)
2021-08-29 02:57:09 +08:00
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#if defined(__ASSEMBLER__)
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/*
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* Support macros for
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* - Armv8.3-A Pointer Authentication and
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* - Armv8.5-A Branch Target Identification
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* features which require emitting a .note.gnu.property section with the
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* appropriate architecture-dependent feature bits set.
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* Read more: "ELF for the Arm® 64-bit Architecture"
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*/
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# if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
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# define GNU_PROPERTY_AARCH64_BTI (1 << 0) /* Has Branch Target Identification */
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# define AARCH64_VALID_CALL_TARGET hint #34 /* BTI 'c' */
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# else
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# define GNU_PROPERTY_AARCH64_BTI 0 /* No Branch Target Identification */
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# define AARCH64_VALID_CALL_TARGET
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# endif
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# if defined(__ARM_FEATURE_PAC_DEFAULT) && \
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(__ARM_FEATURE_PAC_DEFAULT & 1) == 1 /* Signed with A-key */
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# define GNU_PROPERTY_AARCH64_POINTER_AUTH \
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(1 << 1) /* Has Pointer Authentication */
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# define AARCH64_SIGN_LINK_REGISTER hint #25 /* PACIASP */
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# define AARCH64_VALIDATE_LINK_REGISTER hint #29 /* AUTIASP */
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# elif defined(__ARM_FEATURE_PAC_DEFAULT) && \
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(__ARM_FEATURE_PAC_DEFAULT & 2) == 2 /* Signed with B-key */
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# define GNU_PROPERTY_AARCH64_POINTER_AUTH \
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(1 << 1) /* Has Pointer Authentication */
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# define AARCH64_SIGN_LINK_REGISTER hint #27 /* PACIBSP */
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# define AARCH64_VALIDATE_LINK_REGISTER hint #31 /* AUTIBSP */
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# else
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# define GNU_PROPERTY_AARCH64_POINTER_AUTH 0 /* No Pointer Authentication */
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# if GNU_PROPERTY_AARCH64_BTI != 0
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# define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
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# else
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# define AARCH64_SIGN_LINK_REGISTER
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# endif
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# define AARCH64_VALIDATE_LINK_REGISTER
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# endif
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# if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
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.pushsection .note.gnu.property, "a";
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.balign 8;
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.long 4;
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.long 0x10;
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.long 0x5;
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.asciz "GNU";
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.long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
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.long 4;
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.long (GNU_PROPERTY_AARCH64_POINTER_AUTH | GNU_PROPERTY_AARCH64_BTI);
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.long 0;
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.popsection;
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# endif
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# endif /* defined __ASSEMBLER__ */
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2021-06-09 14:35:46 +08:00
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# define IS_CPU_SUPPORT_UNROLL8_EOR3() \
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(OPENSSL_armcap_P & ARMV8_UNROLL8_EOR3)
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2011-04-02 05:09:09 +08:00
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|
#endif
|
