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openssl/include/crypto/riscv_arch.def

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Add basic RISC-V cpuid and OPENSSL_riscvcap RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to be enabled at runtime using OPENSSL_riscvcap environment variable. For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc" Architecture string parsing is still very primitive, but can be expanded in the future. Currently, only bitmanip extensions Zba, Zbb, Zbc and Zbs are supported. Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm, as well as OPENSSL_cleanse. Assembly implementations are written using perlasm. Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Henry Brausen <henry.brausen@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> (Merged from https://github.com/openssl/openssl/pull/17640)
2022-01-28 16:28:52 +08:00
/*
* Copyright 2022 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the Apache License 2.0 (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
/* X Macro Definitions for Specification of RISC-V Arch Capabilities */
/*
* Each RISC-V capability ends up encoded as a single set bit in an array of
* words. When specifying a new capability, write a new RISCV_DEFINE_CAP
* statement, with an argument as the extension name in all-caps,
* second argument as the index in the array where the capability will be stored
* and third argument as the index of the bit to be used to encode the
* capability.
* RISCV_DEFINE_CAP(EXTENSION NAME, array index, bit index) */
RISCV_DEFINE_CAP(ZBA, 0, 0)
RISCV_DEFINE_CAP(ZBB, 0, 1)
RISCV_DEFINE_CAP(ZBC, 0, 2)
RISCV_DEFINE_CAP(ZBS, 0, 3)
Add riscv scalar crypto extension capability Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/18197)
2022-04-30 00:18:29 +08:00
RISCV_DEFINE_CAP(ZBKB, 0, 4)
RISCV_DEFINE_CAP(ZBKC, 0, 5)
RISCV_DEFINE_CAP(ZBKX, 0, 6)
RISCV_DEFINE_CAP(ZKND, 0, 7)
RISCV_DEFINE_CAP(ZKNE, 0, 8)
RISCV_DEFINE_CAP(ZKNH, 0, 9)
RISCV_DEFINE_CAP(ZKSED, 0, 10)
RISCV_DEFINE_CAP(ZKSH, 0, 11)
RISCV_DEFINE_CAP(ZKR, 0, 12)
RISCV_DEFINE_CAP(ZKT, 0, 13)
riscv: Add basic vector extension support The RISC-V vector extension comes with an implementation-defined number of bits per vector register (VLEN), which can be read out at run-time using the CSR 'vlenb' (which returns VLEN/8) followed by a multiplication by 8 (to convert bytes to bits). This patch introduces a RISC-V capability 'V' to specify the availability of the vector extension. If this extension is found at run-time, then we read out VLEN as described above and cache it. Caching ensures that we only read the CSR once at startup. This is necessary because reading out CSR can be expensive (e.g. if CSR readout is implemented using trap-and-emulate). Follow-up patches can make use of VLEN and chose the best strategy based on the available length of the vector registers. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
2023-02-14 13:22:03 +08:00
RISCV_DEFINE_CAP(V, 0, 14)
riscv: GCM: Provide a Zvbb/Zvbc-based implementation The RISC-V vector crypto extensions features a Zvbc extension that provides a carryless multiplication ('vclmul.vv') instruction. This patch provides an implementation that utilizes this extension if available. Tested on QEMU and no regressions observed. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
2023-01-18 20:11:19 +08:00
RISCV_DEFINE_CAP(ZVBB, 0, 15)
RISCV_DEFINE_CAP(ZVBC, 0, 16)
Update for Zvkb extension. https://github.com/riscv/riscv-crypto/blob/c8ddeb7e64a3444dda0438316af1238aeed72041/doc/vector/riscv-crypto-vector-zvkb.adoc Create `RISCV_HAS_ZVKB()` macro. Use zvkb for SM4 instead of zvbb. Use zvkb for ghash instead of zvbb. We could just use the zvbb's subset `zvkb` for flexibility. Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
2023-09-28 13:51:17 +08:00
RISCV_DEFINE_CAP(ZVKB, 0, 17)
RISCV_DEFINE_CAP(ZVKG, 0, 18)
RISCV_DEFINE_CAP(ZVKNED, 0, 19)
RISCV_DEFINE_CAP(ZVKNHA, 0, 20)
RISCV_DEFINE_CAP(ZVKNHB, 0, 21)
RISCV_DEFINE_CAP(ZVKSED, 0, 22)
RISCV_DEFINE_CAP(ZVKSH, 0, 23)
Add basic RISC-V cpuid and OPENSSL_riscvcap RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to be enabled at runtime using OPENSSL_riscvcap environment variable. For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc" Architecture string parsing is still very primitive, but can be expanded in the future. Currently, only bitmanip extensions Zba, Zbb, Zbc and Zbs are supported. Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm, as well as OPENSSL_cleanse. Assembly implementations are written using perlasm. Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Henry Brausen <henry.brausen@vrull.eu> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> (Merged from https://github.com/openssl/openssl/pull/17640)
2022-01-28 16:28:52 +08:00
/*
* In the future ...
* RISCV_DEFINE_CAP(ZFOO, 0, 31)
* RISCV_DEFINE_CAP(ZBAR, 1, 0)
* ... and so on.
*/
#undef RISCV_DEFINE_CAP
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