Add basic RISC-V cpuid and OPENSSL_riscvcap
RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to
be enabled at runtime using OPENSSL_riscvcap environment variable.
For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc
extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc"
Architecture string parsing is still very primitive, but can be
expanded in the future. Currently, only bitmanip extensions Zba, Zbb,
Zbc and Zbs are supported.
Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm,
as well as OPENSSL_cleanse. Assembly implementations are written using
perlasm.
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Henry Brausen <henry.brausen@vrull.eu>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17640)
2022-01-28 16:28:52 +08:00
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/*
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* Copyright 2022 The OpenSSL Project Authors. All Rights Reserved.
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*
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* Licensed under the Apache License 2.0 (the "License"). You may not use
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* this file except in compliance with the License. You can obtain a copy
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* in the file LICENSE in the source distribution or at
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* https://www.openssl.org/source/license.html
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*/
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/* X Macro Definitions for Specification of RISC-V Arch Capabilities */
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/*
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* Each RISC-V capability ends up encoded as a single set bit in an array of
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* words. When specifying a new capability, write a new RISCV_DEFINE_CAP
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* statement, with an argument as the extension name in all-caps,
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* second argument as the index in the array where the capability will be stored
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* and third argument as the index of the bit to be used to encode the
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* capability.
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2024-04-17 17:21:53 +08:00
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*
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* The fourth and the fifth arguments are copied from linux header asm/hwprobe.h.
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* Directly coping values instead of macro names comes from the fact
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* that an old version may lack definition of some macro.
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* When there is no hwprobe key/value pair for a capability, the key is set to -1
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* and the value is set to 0, as when the hwprobe syscall returns a key of -1,
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* the value is set to 0 and the corresponding capability would not be enabled.
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*
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* RISCV_DEFINE_CAP(EXTENSION NAME, array index, bit index, hwprobe key, hwprobe value) */
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Add basic RISC-V cpuid and OPENSSL_riscvcap
RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to
be enabled at runtime using OPENSSL_riscvcap environment variable.
For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc
extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc"
Architecture string parsing is still very primitive, but can be
expanded in the future. Currently, only bitmanip extensions Zba, Zbb,
Zbc and Zbs are supported.
Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm,
as well as OPENSSL_cleanse. Assembly implementations are written using
perlasm.
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Henry Brausen <henry.brausen@vrull.eu>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17640)
2022-01-28 16:28:52 +08:00
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2024-04-17 17:21:53 +08:00
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RISCV_DEFINE_CAP(ZBA, 0, 0, 4, (1 << 3))
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RISCV_DEFINE_CAP(ZBB, 0, 1, 4, (1 << 4))
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RISCV_DEFINE_CAP(ZBC, 0, 2, 4, (1 << 7))
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RISCV_DEFINE_CAP(ZBS, 0, 3, 4, (1 << 5))
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RISCV_DEFINE_CAP(ZBKB, 0, 4, 4, (1 << 8))
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RISCV_DEFINE_CAP(ZBKC, 0, 5, 4, (1 << 9))
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RISCV_DEFINE_CAP(ZBKX, 0, 6, 4, (1 << 10))
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RISCV_DEFINE_CAP(ZKND, 0, 7, 4, (1 << 11))
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RISCV_DEFINE_CAP(ZKNE, 0, 8, 4, (1 << 12))
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RISCV_DEFINE_CAP(ZKNH, 0, 9, 4, (1 << 13))
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RISCV_DEFINE_CAP(ZKSED, 0, 10, 4, (1 << 14))
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RISCV_DEFINE_CAP(ZKSH, 0, 11, 4, (1 << 15))
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RISCV_DEFINE_CAP(ZKR, 0, 12, -1, 0)
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RISCV_DEFINE_CAP(ZKT, 0, 13, 4, (1 << 16))
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RISCV_DEFINE_CAP(V, 0, 14, 4, (1 << 2))
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RISCV_DEFINE_CAP(ZVBB, 0, 15, 4, (1 << 17))
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RISCV_DEFINE_CAP(ZVBC, 0, 16, 4, (1 << 18))
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RISCV_DEFINE_CAP(ZVKB, 0, 17, 4, (1 << 19))
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RISCV_DEFINE_CAP(ZVKG, 0, 18, 4, (1 << 20))
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RISCV_DEFINE_CAP(ZVKNED, 0, 19, 4, (1 << 21))
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RISCV_DEFINE_CAP(ZVKNHA, 0, 20, 4, (1 << 22))
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RISCV_DEFINE_CAP(ZVKNHB, 0, 21, 4, (1 << 23))
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RISCV_DEFINE_CAP(ZVKSED, 0, 22, 4, (1 << 24))
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RISCV_DEFINE_CAP(ZVKSH, 0, 23, 4, (1 << 25))
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Add basic RISC-V cpuid and OPENSSL_riscvcap
RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to
be enabled at runtime using OPENSSL_riscvcap environment variable.
For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc
extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc"
Architecture string parsing is still very primitive, but can be
expanded in the future. Currently, only bitmanip extensions Zba, Zbb,
Zbc and Zbs are supported.
Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm,
as well as OPENSSL_cleanse. Assembly implementations are written using
perlasm.
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Henry Brausen <henry.brausen@vrull.eu>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17640)
2022-01-28 16:28:52 +08:00
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/*
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* In the future ...
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2024-04-17 17:21:53 +08:00
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* RISCV_DEFINE_CAP(ZFOO, 0, 31, ..., ...)
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* RISCV_DEFINE_CAP(ZBAR, 1, 0, ..., ...)
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Add basic RISC-V cpuid and OPENSSL_riscvcap
RISC-V cpuid implementation allows bitmanip extensions Zb[abcs] to
be enabled at runtime using OPENSSL_riscvcap environment variable.
For example, to specify 64-bit RISC-V with the G,C,Zba,Zbb,Zbc
extensions, one could write: OPENSSL_riscvcap="rv64gc_zba_zbb_zbc"
Architecture string parsing is still very primitive, but can be
expanded in the future. Currently, only bitmanip extensions Zba, Zbb,
Zbc and Zbs are supported.
Includes implementation of constant-time CRYPTO_memcmp in riscv64 asm,
as well as OPENSSL_cleanse. Assembly implementations are written using
perlasm.
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Henry Brausen <henry.brausen@vrull.eu>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17640)
2022-01-28 16:28:52 +08:00
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* ... and so on.
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*/
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#undef RISCV_DEFINE_CAP
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