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More for MIPS
Do a cacheflush after writing data pages, separate from meta's cacheflush
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commit
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@ -3110,6 +3110,12 @@ mdb_page_flush(MDB_txn *txn, int keep)
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#endif /* _WIN32 */
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}
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/* MIPS has cache coherency issues, this is a no-op everywhere else
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* Note: for any size >= on-chip cache size, entire on-chip cache is
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* flushed.
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*/
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CACHEFLUSH(env->me_map, txn->mt_next_pgno * env->me_psize, DCACHE);
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for (i = keep; ++i <= pagecount; ) {
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dp = dl[i].mptr;
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/* This is a page we skipped above */
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@ -3583,7 +3589,7 @@ fail:
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done:
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/* MIPS has cache coherency issues, this is a no-op everywhere else */
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if (!(env->me_flags & MDB_WRITEMAP)) {
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CACHEFLUSH(env->me_map, txn->mt_next_pgno * env->me_psize, DCACHE);
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CACHEFLUSH(env->me_map + off, len, DCACHE);
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}
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/* Memory ordering issues are irrelevant; since the entire writer
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* is wrapped by wmutex, all of these changes will become visible
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