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Fix MIPS cache coherency on Linux

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MIPS chips require manual control of on-chip caches. The cacheflush
syscall being used here only exists on MIPS Linux, other OSs will
require revisiting.
This commit is contained in:
Howard Chu 2014-07-26 18:16:02 -07:00
parent d098184f61
commit 3630066843
1 changed files with 14 additions and 0 deletions
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14
libraries/liblmdb/mdb.c
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@ -70,6 +70,15 @@
#include <fcntl.h>
#endif
#if defined(__mips) && defined(__linux)
/* MIPS has cache coherency issues, requires explicit cache control */
#include <asm/cachectl.h>
extern int cacheflush(char *addr, int nbytes, int cache);
#define CACHEFLUSH(addr, bytes, cache) cacheflush(addr, bytes, cache)
#else
#define CACHEFLUSH(addr, bytes, cache)
#endif
#include <errno.h>
#include <limits.h>
#include <stddef.h>
@ -3581,6 +3590,11 @@ done:
if (env->me_txns)
env->me_txns->mti_txnid = txn->mt_txnid;
/* MIPS has cache coherency issues, this is a no-op everywhere else */
if (!(env->me_flags & MDB_WRITEMAP)) {
CACHEFLUSH(env->me_map, txn->mt_next_pgno * env->me_psize, DCACHE);
}
return MDB_SUCCESS;
}