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https://github.com/netwide-assembler/nasm.git
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b106ba161f
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6c437c50452c4997aa2e3de5a0e0299
and reverted in:
d279fbbd80aab6f79584249629a4aea90b851458
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
16 lines
214 B
NASM
16 lines
214 B
NASM
bits 64
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movd r8d, mm1
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movd r8, mm1
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movq r8, mm1
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movd [rax], mm1
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movq [rax], mm1
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movd dword [rax], mm1
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; movq dword [rax], mm1
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movd qword [rax], mm1
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movq qword [rax], mm1
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; movd mm2, mm1
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movq mm2, mm1
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