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https://github.com/netwide-assembler/nasm.git
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02b60ddd1c
The memory operand size of LEA doesn't matter in any way as it isn't "real memory". Add an ANYSIZE option to ignore sizes entirely. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
125 lines
5.0 KiB
Perl
125 lines
5.0 KiB
Perl
# -*- perl -*-
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#
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# dword bound, index 0 - specific flags
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#
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if_align('IGEN');
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if_("SM", "Size match");
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if_("SM2", "Size match first two operands");
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if_("SB", "Unsized operands can't be non-byte");
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if_("SW", "Unsized operands can't be non-word");
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if_("SD", "Unsized operands can't be non-dword");
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if_("SQ", "Unsized operands can't be non-qword");
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if_("SO", "Unsized operands can't be non-oword");
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if_("SY", "Unsized operands can't be non-yword");
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if_("SZ", "Unsized operands can't be non-zword");
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if_("SIZE", "Unsized operands must match the bitsize");
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if_("SX", "Unsized operands not allowed");
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if_("ANYSIZE", "Ignore operand size even if explicit");
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if_("AR0", "SB, SW, SD applies to argument 0");
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if_("AR1", "SB, SW, SD applies to argument 1");
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if_("AR2", "SB, SW, SD applies to argument 2");
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if_("AR3", "SB, SW, SD applies to argument 3");
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if_("AR4", "SB, SW, SD applies to argument 4");
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if_("OPT", "Optimizing assembly only");
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#
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# dword bound - instruction feature filtering flags
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#
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if_align('FEATURE');
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if_("PRIV", "Privileged instruction");
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if_("SMM", "Only valid in SMM");
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if_("PROT", "Protected mode only");
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if_("LOCK", "Lockable if operand 0 is memory");
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if_("NOLONG", "Not available in long mode");
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if_("LONG", "Long mode");
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if_("NOHLE", "HLE prefixes forbidden");
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if_("MIB", "disassemble with split EA");
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if_("BND", "BND (0xF2) prefix available");
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if_("UNDOC", "Undocumented");
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if_("HLE", "HLE prefixed");
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if_("FPU", "FPU");
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if_("MMX", "MMX");
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if_("3DNOW", "3DNow!");
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if_("SSE", "SSE (KNI, MMX2)");
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if_("SSE2", "SSE2");
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if_("SSE3", "SSE3 (PNI)");
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if_("VMX", "VMX");
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if_("SSSE3", "SSSE3");
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if_("SSE4A", "AMD SSE4a");
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if_("SSE41", "SSE4.1");
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if_("SSE42", "SSE4.2");
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if_("SSE5", "SSE5");
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if_("AVX", "AVX (256-bit floating point)");
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if_("AVX2", "AVX2 (256-bit integer)");
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if_("FMA", "");
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if_("BMI1", "");
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if_("BMI2", "");
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if_("TBM", "");
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if_("RTM", "");
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if_("INVPCID", "");
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if_("AVX512", "AVX-512F (512-bit base architecture)");
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if_("AVX512CD", "AVX-512 Conflict Detection");
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if_("AVX512ER", "AVX-512 Exponential and Reciprocal");
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if_("AVX512PF", "AVX-512 Prefetch");
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if_("MPX", "MPX");
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if_("SHA", "SHA");
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if_("PREFETCHWT1", "PREFETCHWT1");
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if_("AVX512VL", "AVX-512 Vector Length Orthogonality");
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if_("AVX512DQ", "AVX-512 Dword and Qword");
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if_("AVX512BW", "AVX-512 Byte and Word");
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if_("AVX512IFMA", "AVX-512 IFMA instructions");
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if_("AVX512VBMI", "AVX-512 VBMI instructions");
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if_("AES", "AES instructions");
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if_("VAES", "AES AVX instructions");
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if_("VPCLMULQDQ", "AVX Carryless Multiplication");
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if_("GFNI", "Galois Field instructions");
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if_("AVX512VBMI2", "AVX-512 VBMI2 instructions");
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if_("AVX512VNNI", "AVX-512 VNNI instructions");
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if_("AVX512BITALG", "AVX-512 Bit Algorithm instructions");
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if_("AVX512VPOPCNTDQ", "AVX-512 VPOPCNTD/VPOPCNTQ");
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if_("AVX5124FMAPS", "AVX-512 4-iteration multiply-add");
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if_("AVX5124VNNIW", "AVX-512 4-iteration dot product");
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if_("SGX", "Intel Software Guard Extensions (SGX)");
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# Put these last [hpa: why?]
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if_("OBSOLETE", "Instruction removed from architecture");
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if_("NEVER", "Instruction never implemented");
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if_("NOP", "Instruction is always a (nonintentional) NOP");
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if_("VEX", "VEX or XOP encoded instruction");
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if_("EVEX", "EVEX encoded instruction");
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#
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# dword bound - cpu type flags
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#
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# The CYRIX and AMD flags should have the highest bit values; the
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# disassembler selection algorithm depends on it.
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#
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if_align('CPU');
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if_("8086", "8086");
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if_("186", "186+");
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if_("286", "286+");
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if_("386", "386+");
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if_("486", "486+");
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if_("PENT", "Pentium");
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if_("P6", "P6");
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if_("KATMAI", "Katmai");
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if_("WILLAMETTE", "Willamette");
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if_("PRESCOTT", "Prescott");
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if_("X86_64", "x86-64 (long or legacy mode)");
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if_("NEHALEM", "Nehalem");
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if_("WESTMERE", "Westmere");
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if_("SANDYBRIDGE", "Sandy Bridge");
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if_("FUTURE", "Ivy Bridge or newer");
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if_("IA64", "IA64 (in x86 mode)");
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# Must be the last CPU definition
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if_("ANY", "Any x86 CPU");
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# These must come after the CPU defitions proper
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if_("CYRIX", "Cyrix-specific");
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if_("AMD", "AMD-specific");
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