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https://github.com/netwide-assembler/nasm.git
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fa3833db81
As far as the disassembler is concerned, the segment register push/pop bytecodes can be collapsed to a simple expression; the remaining differences are handled by the filter expressions in insns.pl. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
1433 lines
35 KiB
C
1433 lines
35 KiB
C
/* disasm.c where all the _work_ gets done in the Netwide Disassembler
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*
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* The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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* Julian Hall. All rights reserved. The software is
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* redistributable under the license given in the file "LICENSE"
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* distributed in the NASM archive.
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*
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* initial version 27/iii/95 by Simon Tatham
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*/
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#include "compiler.h"
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#include <stdio.h>
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#include <string.h>
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#include <limits.h>
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#include <inttypes.h>
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#include "nasm.h"
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#include "disasm.h"
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#include "sync.h"
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#include "insns.h"
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#include "tables.h"
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#include "regdis.h"
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/*
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* Flags that go into the `segment' field of `insn' structures
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* during disassembly.
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*/
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#define SEG_RELATIVE 1
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#define SEG_32BIT 2
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#define SEG_RMREG 4
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#define SEG_DISP8 8
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#define SEG_DISP16 16
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#define SEG_DISP32 32
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#define SEG_NODISP 64
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#define SEG_SIGNED 128
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#define SEG_64BIT 256
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/*
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* Prefix information
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*/
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struct prefix_info {
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uint8_t osize; /* Operand size */
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uint8_t asize; /* Address size */
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uint8_t osp; /* Operand size prefix present */
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uint8_t asp; /* Address size prefix present */
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uint8_t rep; /* Rep prefix present */
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uint8_t seg; /* Segment override prefix present */
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uint8_t lock; /* Lock prefix present */
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uint8_t vex[3]; /* VEX prefix present */
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uint8_t vex_m; /* VEX.M field */
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uint8_t vex_v;
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uint8_t vex_lp; /* VEX.LP fields */
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uint32_t rex; /* REX prefix present */
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};
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#define getu8(x) (*(uint8_t *)(x))
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#if X86_MEMORY
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/* Littleendian CPU which can handle unaligned references */
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#define getu16(x) (*(uint16_t *)(x))
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#define getu32(x) (*(uint32_t *)(x))
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#define getu64(x) (*(uint64_t *)(x))
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#else
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static uint16_t getu16(uint8_t *data)
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{
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return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
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}
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static uint32_t getu32(uint8_t *data)
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{
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return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
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}
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static uint64_t getu64(uint8_t *data)
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{
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return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
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}
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#endif
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#define gets8(x) ((int8_t)getu8(x))
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#define gets16(x) ((int16_t)getu16(x))
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#define gets32(x) ((int32_t)getu32(x))
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#define gets64(x) ((int64_t)getu64(x))
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/* Important: regval must already have been adjusted for rex extensions */
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static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
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{
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if (!(regflags & (REGISTER|REGMEM)))
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return 0; /* Registers not permissible?! */
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regflags |= REGISTER;
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if (!(REG_AL & ~regflags))
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return R_AL;
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if (!(REG_AX & ~regflags))
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return R_AX;
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if (!(REG_EAX & ~regflags))
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return R_EAX;
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if (!(REG_RAX & ~regflags))
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return R_RAX;
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if (!(REG_DL & ~regflags))
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return R_DL;
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if (!(REG_DX & ~regflags))
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return R_DX;
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if (!(REG_EDX & ~regflags))
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return R_EDX;
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if (!(REG_RDX & ~regflags))
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return R_RDX;
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if (!(REG_CL & ~regflags))
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return R_CL;
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if (!(REG_CX & ~regflags))
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return R_CX;
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if (!(REG_ECX & ~regflags))
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return R_ECX;
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if (!(REG_RCX & ~regflags))
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return R_RCX;
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if (!(FPU0 & ~regflags))
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return R_ST0;
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if (!(XMM0 & ~regflags))
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return R_XMM0;
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if (!(YMM0 & ~regflags))
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return R_YMM0;
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if (!(REG_CS & ~regflags))
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return (regval == 1) ? R_CS : 0;
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if (!(REG_DESS & ~regflags))
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return (regval == 0 || regval == 2
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|| regval == 3 ? nasm_rd_sreg[regval] : 0);
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if (!(REG_FSGS & ~regflags))
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return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
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if (!(REG_SEG67 & ~regflags))
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return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
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/* All the entries below look up regval in an 16-entry array */
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if (regval < 0 || regval > 15)
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return 0;
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if (!(REG8 & ~regflags)) {
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if (rex & REX_P)
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return nasm_rd_reg8_rex[regval];
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else
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return nasm_rd_reg8[regval];
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}
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if (!(REG16 & ~regflags))
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return nasm_rd_reg16[regval];
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if (!(REG32 & ~regflags))
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return nasm_rd_reg32[regval];
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if (!(REG64 & ~regflags))
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return nasm_rd_reg64[regval];
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if (!(REG_SREG & ~regflags))
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return nasm_rd_sreg[regval & 7]; /* Ignore REX */
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if (!(REG_CREG & ~regflags))
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return nasm_rd_creg[regval];
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if (!(REG_DREG & ~regflags))
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return nasm_rd_dreg[regval];
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if (!(REG_TREG & ~regflags)) {
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if (rex & REX_P)
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return 0; /* TR registers are ill-defined with rex */
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return nasm_rd_treg[regval];
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}
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if (!(FPUREG & ~regflags))
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return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
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if (!(MMXREG & ~regflags))
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return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
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if (!(XMMREG & ~regflags))
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return nasm_rd_xmmreg[regval];
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if (!(YMMREG & ~regflags))
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return nasm_rd_ymmreg[regval];
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return 0;
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}
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/*
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* Process a DREX suffix
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*/
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static uint8_t *do_drex(uint8_t *data, insn *ins)
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{
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uint8_t drex = *data++;
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operand *dst = &ins->oprs[ins->drexdst];
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if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
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return NULL; /* OC0 mismatch */
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ins->rex = (ins->rex & ~7) | (drex & 7);
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dst->segment = SEG_RMREG;
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dst->basereg = drex >> 4;
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return data;
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}
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/*
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* Process an effective address (ModRM) specification.
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*/
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static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
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int segsize, operand * op, insn *ins)
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{
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int mod, rm, scale, index, base;
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int rex;
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uint8_t sib = 0;
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mod = (modrm >> 6) & 03;
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rm = modrm & 07;
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if (mod != 3 && rm == 4 && asize != 16)
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sib = *data++;
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if (ins->rex & REX_D) {
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data = do_drex(data, ins);
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if (!data)
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return NULL;
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}
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rex = ins->rex;
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if (mod == 3) { /* pure register version */
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op->basereg = rm+(rex & REX_B ? 8 : 0);
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op->segment |= SEG_RMREG;
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return data;
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}
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op->disp_size = 0;
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op->eaflags = 0;
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if (asize == 16) {
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/*
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* <mod> specifies the displacement size (none, byte or
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* word), and <rm> specifies the register combination.
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* Exception: mod=0,rm=6 does not specify [BP] as one might
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* expect, but instead specifies [disp16].
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*/
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op->indexreg = op->basereg = -1;
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op->scale = 1; /* always, in 16 bits */
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switch (rm) {
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case 0:
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op->basereg = R_BX;
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op->indexreg = R_SI;
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break;
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case 1:
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op->basereg = R_BX;
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op->indexreg = R_DI;
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break;
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case 2:
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op->basereg = R_BP;
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op->indexreg = R_SI;
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break;
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case 3:
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op->basereg = R_BP;
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op->indexreg = R_DI;
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break;
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case 4:
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op->basereg = R_SI;
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break;
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case 5:
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op->basereg = R_DI;
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break;
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case 6:
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op->basereg = R_BP;
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break;
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case 7:
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op->basereg = R_BX;
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break;
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}
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if (rm == 6 && mod == 0) { /* special case */
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op->basereg = -1;
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if (segsize != 16)
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op->disp_size = 16;
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mod = 2; /* fake disp16 */
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}
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switch (mod) {
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case 0:
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op->segment |= SEG_NODISP;
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break;
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case 1:
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op->segment |= SEG_DISP8;
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op->offset = (int8_t)*data++;
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break;
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case 2:
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op->segment |= SEG_DISP16;
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op->offset = *data++;
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op->offset |= ((unsigned)*data++) << 8;
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break;
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}
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return data;
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} else {
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/*
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* Once again, <mod> specifies displacement size (this time
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* none, byte or *dword*), while <rm> specifies the base
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* register. Again, [EBP] is missing, replaced by a pure
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* disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
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* and RIP-relative addressing in 64-bit mode.
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*
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* However, rm=4
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* indicates not a single base register, but instead the
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* presence of a SIB byte...
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*/
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int a64 = asize == 64;
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op->indexreg = -1;
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if (a64)
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op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
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else
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op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
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if (rm == 5 && mod == 0) {
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if (segsize == 64) {
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op->eaflags |= EAF_REL;
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op->segment |= SEG_RELATIVE;
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mod = 2; /* fake disp32 */
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}
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if (asize != 64)
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op->disp_size = asize;
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op->basereg = -1;
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mod = 2; /* fake disp32 */
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}
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if (rm == 4) { /* process SIB */
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scale = (sib >> 6) & 03;
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index = (sib >> 3) & 07;
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base = sib & 07;
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op->scale = 1 << scale;
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if (index == 4 && !(rex & REX_X))
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op->indexreg = -1; /* ESP/RSP cannot be an index */
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else if (a64)
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op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
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else
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op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
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if (base == 5 && mod == 0) {
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op->basereg = -1;
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mod = 2; /* Fake disp32 */
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} else if (a64)
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op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
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else
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op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
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if (segsize == 16)
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op->disp_size = 32;
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}
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switch (mod) {
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case 0:
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op->segment |= SEG_NODISP;
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break;
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case 1:
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op->segment |= SEG_DISP8;
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op->offset = gets8(data);
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data++;
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break;
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case 2:
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op->segment |= SEG_DISP32;
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op->offset = gets32(data);
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data += 4;
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break;
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}
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return data;
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}
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}
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/*
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* Determine whether the instruction template in t corresponds to the data
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* stream in data. Return the number of bytes matched if so.
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*/
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#define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
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static int matches(const struct itemplate *t, uint8_t *data,
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const struct prefix_info *prefix, int segsize, insn *ins)
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{
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uint8_t *r = (uint8_t *)(t->code);
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uint8_t *origdata = data;
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bool a_used = false, o_used = false;
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enum prefixes drep = 0;
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uint8_t lock = prefix->lock;
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int osize = prefix->osize;
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int asize = prefix->asize;
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int i, c;
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struct operand *opx;
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int s_field_for = -1; /* No 144/154 series code encountered */
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bool vex_ok = false;
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int regmask = (segsize == 64) ? 15 : 7;
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for (i = 0; i < MAX_OPERANDS; i++) {
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ins->oprs[i].segment = ins->oprs[i].disp_size =
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(segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
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}
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ins->condition = -1;
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ins->rex = prefix->rex;
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memset(ins->prefixes, 0, sizeof ins->prefixes);
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if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
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return false;
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if (prefix->rep == 0xF2)
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drep = P_REPNE;
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else if (prefix->rep == 0xF3)
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drep = P_REP;
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while ((c = *r++) != 0) {
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opx = &ins->oprs[c & 3];
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switch (c) {
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case 01:
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case 02:
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case 03:
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while (c--)
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if (*r++ != *data++)
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return false;
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break;
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case4(010):
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{
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int t = *r++, d = *data++;
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if (d < t || d > t + 7)
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return false;
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else {
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opx->basereg = (d-t)+
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(ins->rex & REX_B ? 8 : 0);
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opx->segment |= SEG_RMREG;
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}
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break;
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}
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case4(014):
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case4(0274):
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opx->offset = (int8_t)*data++;
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opx->segment |= SEG_SIGNED;
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break;
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case4(020):
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opx->offset = *data++;
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break;
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case4(024):
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opx->offset = *data++;
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break;
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case4(030):
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opx->offset = getu16(data);
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data += 2;
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break;
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case4(034):
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if (osize == 32) {
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opx->offset = getu32(data);
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data += 4;
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} else {
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opx->offset = getu16(data);
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data += 2;
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}
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if (segsize != asize)
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opx->disp_size = asize;
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break;
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case4(040):
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case4(0254):
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opx->offset = getu32(data);
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data += 4;
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break;
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case4(044):
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switch (asize) {
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case 16:
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opx->offset = getu16(data);
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data += 2;
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if (segsize != 16)
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opx->disp_size = 16;
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break;
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case 32:
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opx->offset = getu32(data);
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data += 4;
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if (segsize == 16)
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opx->disp_size = 32;
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break;
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case 64:
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opx->offset = getu64(data);
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opx->disp_size = 64;
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data += 8;
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break;
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}
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break;
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case4(050):
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opx->offset = gets8(data++);
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opx->segment |= SEG_RELATIVE;
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break;
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case4(054):
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opx->offset = getu64(data);
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data += 8;
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break;
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case4(060):
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opx->offset = gets16(data);
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data += 2;
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opx->segment |= SEG_RELATIVE;
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opx->segment &= ~SEG_32BIT;
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break;
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case4(064):
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opx->segment |= SEG_RELATIVE;
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if (osize == 16) {
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opx->offset = gets16(data);
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data += 2;
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opx->segment &= ~(SEG_32BIT|SEG_64BIT);
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} else if (osize == 32) {
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opx->offset = gets32(data);
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data += 4;
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opx->segment &= ~SEG_64BIT;
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opx->segment |= SEG_32BIT;
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}
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if (segsize != osize) {
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opx->type =
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(opx->type & ~SIZE_MASK)
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| ((osize == 16) ? BITS16 : BITS32);
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}
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break;
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case4(070):
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opx->offset = gets32(data);
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data += 4;
|
|
opx->segment |= SEG_32BIT | SEG_RELATIVE;
|
|
break;
|
|
|
|
case4(0100):
|
|
case4(0110):
|
|
case4(0120):
|
|
case4(0130):
|
|
{
|
|
int modrm = *data++;
|
|
opx->segment |= SEG_RMREG;
|
|
data = do_ea(data, modrm, asize, segsize,
|
|
&ins->oprs[(c >> 3) & 3], ins);
|
|
if (!data)
|
|
return false;
|
|
opx->basereg = ((modrm >> 3)&7)+
|
|
(ins->rex & REX_R ? 8 : 0);
|
|
break;
|
|
}
|
|
|
|
case4(0140):
|
|
if (s_field_for == (c & 3)) {
|
|
opx->offset = gets8(data);
|
|
data++;
|
|
} else {
|
|
opx->offset = getu16(data);
|
|
data += 2;
|
|
}
|
|
break;
|
|
|
|
case4(0144):
|
|
case4(0154):
|
|
s_field_for = (*data & 0x02) ? c & 3 : -1;
|
|
if ((*data++ & ~0x02) != *r++)
|
|
return false;
|
|
break;
|
|
|
|
case4(0150):
|
|
if (s_field_for == (c & 3)) {
|
|
opx->offset = gets8(data);
|
|
data++;
|
|
} else {
|
|
opx->offset = getu32(data);
|
|
data += 4;
|
|
}
|
|
break;
|
|
|
|
case4(0160):
|
|
ins->rex |= REX_D;
|
|
ins->drexdst = c & 3;
|
|
break;
|
|
|
|
case4(0164):
|
|
ins->rex |= REX_D|REX_OC;
|
|
ins->drexdst = c & 3;
|
|
break;
|
|
|
|
case 0171:
|
|
data = do_drex(data, ins);
|
|
if (!data)
|
|
return false;
|
|
break;
|
|
|
|
case 0172:
|
|
{
|
|
uint8_t ximm = *data++;
|
|
c = *r++;
|
|
ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
|
|
ins->oprs[c >> 3].segment |= SEG_RMREG;
|
|
ins->oprs[c & 7].offset = ximm & 15;
|
|
}
|
|
break;
|
|
|
|
case 0173:
|
|
{
|
|
uint8_t ximm = *data++;
|
|
c = *r++;
|
|
|
|
if ((c ^ ximm) & 15)
|
|
return false;
|
|
|
|
ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
|
|
ins->oprs[c >> 4].segment |= SEG_RMREG;
|
|
}
|
|
break;
|
|
|
|
case 0174:
|
|
{
|
|
uint8_t ximm = *data++;
|
|
c = *r++;
|
|
|
|
ins->oprs[c].basereg = (ximm >> 4) & regmask;
|
|
ins->oprs[c].segment |= SEG_RMREG;
|
|
}
|
|
break;
|
|
|
|
case4(0200):
|
|
case4(0204):
|
|
case4(0210):
|
|
case4(0214):
|
|
case4(0220):
|
|
case4(0224):
|
|
case4(0230):
|
|
case4(0234):
|
|
{
|
|
int modrm = *data++;
|
|
if (((modrm >> 3) & 07) != (c & 07))
|
|
return false; /* spare field doesn't match up */
|
|
data = do_ea(data, modrm, asize, segsize,
|
|
&ins->oprs[(c >> 3) & 07], ins);
|
|
if (!data)
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
case4(0260):
|
|
{
|
|
int vexm = *r++;
|
|
int vexwlp = *r++;
|
|
ins->rex |= REX_V;
|
|
if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
|
|
return false;
|
|
|
|
if ((vexm & 0x1f) != prefix->vex_m)
|
|
return false;
|
|
|
|
switch (vexwlp & 030) {
|
|
case 000:
|
|
if (prefix->rex & REX_W)
|
|
return false;
|
|
break;
|
|
case 010:
|
|
if (!(prefix->rex & REX_W))
|
|
return false;
|
|
ins->rex &= ~REX_W;
|
|
break;
|
|
case 020: /* VEX.W is a don't care */
|
|
ins->rex &= ~REX_W;
|
|
break;
|
|
case 030:
|
|
break;
|
|
}
|
|
|
|
if ((vexwlp & 007) != prefix->vex_lp)
|
|
return false;
|
|
|
|
opx->segment |= SEG_RMREG;
|
|
opx->basereg = prefix->vex_v;
|
|
vex_ok = true;
|
|
break;
|
|
}
|
|
|
|
case 0270:
|
|
{
|
|
int vexm = *r++;
|
|
int vexwlp = *r++;
|
|
ins->rex |= REX_V;
|
|
if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
|
|
return false;
|
|
|
|
if ((vexm & 0x1f) != prefix->vex_m)
|
|
return false;
|
|
|
|
switch (vexwlp & 030) {
|
|
case 000:
|
|
if (ins->rex & REX_W)
|
|
return false;
|
|
break;
|
|
case 010:
|
|
if (!(ins->rex & REX_W))
|
|
return false;
|
|
break;
|
|
default:
|
|
break; /* Need to do anything special here? */
|
|
}
|
|
|
|
if ((vexwlp & 007) != prefix->vex_lp)
|
|
return false;
|
|
|
|
if (prefix->vex_v != 0)
|
|
return false;
|
|
|
|
vex_ok = true;
|
|
break;
|
|
}
|
|
|
|
case 0310:
|
|
if (asize != 16)
|
|
return false;
|
|
else
|
|
a_used = true;
|
|
break;
|
|
|
|
case 0311:
|
|
if (asize == 16)
|
|
return false;
|
|
else
|
|
a_used = true;
|
|
break;
|
|
|
|
case 0312:
|
|
if (asize != segsize)
|
|
return false;
|
|
else
|
|
a_used = true;
|
|
break;
|
|
|
|
case 0313:
|
|
if (asize != 64)
|
|
return false;
|
|
else
|
|
a_used = true;
|
|
break;
|
|
|
|
case 0314:
|
|
if (prefix->rex & REX_B)
|
|
return false;
|
|
break;
|
|
|
|
case 0315:
|
|
if (prefix->rex & REX_X)
|
|
return false;
|
|
break;
|
|
|
|
case 0316:
|
|
if (prefix->rex & REX_R)
|
|
return false;
|
|
break;
|
|
|
|
case 0317:
|
|
if (prefix->rex & REX_W)
|
|
return false;
|
|
break;
|
|
|
|
case 0320:
|
|
if (osize != 16)
|
|
return false;
|
|
else
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0321:
|
|
if (osize != 32)
|
|
return false;
|
|
else
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0322:
|
|
if (osize != (segsize == 16) ? 16 : 32)
|
|
return false;
|
|
else
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0323:
|
|
ins->rex |= REX_W; /* 64-bit only instruction */
|
|
osize = 64;
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0324:
|
|
if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
|
|
return false;
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0330:
|
|
{
|
|
int t = *r++, d = *data++;
|
|
if (d < t || d > t + 15)
|
|
return false;
|
|
else
|
|
ins->condition = d - t;
|
|
break;
|
|
}
|
|
|
|
case 0331:
|
|
if (prefix->rep)
|
|
return false;
|
|
break;
|
|
|
|
case 0332:
|
|
if (prefix->rep != 0xF2)
|
|
return false;
|
|
drep = 0;
|
|
break;
|
|
|
|
case 0333:
|
|
if (prefix->rep != 0xF3)
|
|
return false;
|
|
drep = 0;
|
|
break;
|
|
|
|
case 0334:
|
|
if (lock) {
|
|
ins->rex |= REX_R;
|
|
lock = 0;
|
|
}
|
|
break;
|
|
|
|
case 0335:
|
|
if (drep == P_REP)
|
|
drep = P_REPE;
|
|
break;
|
|
|
|
case 0336:
|
|
case 0337:
|
|
break;
|
|
|
|
case 0340:
|
|
return false;
|
|
|
|
case4(0344):
|
|
ins->oprs[0].basereg = (*data++ >> 3) & 7;
|
|
break;
|
|
|
|
case 0360:
|
|
if (prefix->osp || prefix->rep)
|
|
return false;
|
|
break;
|
|
|
|
case 0361:
|
|
if (!prefix->osp || prefix->rep)
|
|
return false;
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0362:
|
|
if (prefix->osp || prefix->rep != 0xf2)
|
|
return false;
|
|
drep = 0;
|
|
break;
|
|
|
|
case 0363:
|
|
if (prefix->osp || prefix->rep != 0xf3)
|
|
return false;
|
|
drep = 0;
|
|
break;
|
|
|
|
case 0364:
|
|
if (prefix->osp)
|
|
return false;
|
|
break;
|
|
|
|
case 0365:
|
|
if (prefix->asp)
|
|
return false;
|
|
break;
|
|
|
|
case 0366:
|
|
if (!prefix->osp)
|
|
return false;
|
|
o_used = true;
|
|
break;
|
|
|
|
case 0367:
|
|
if (!prefix->asp)
|
|
return false;
|
|
a_used = true;
|
|
break;
|
|
|
|
default:
|
|
return false; /* Unknown code */
|
|
}
|
|
}
|
|
|
|
if (!vex_ok && (ins->rex & REX_V))
|
|
return false;
|
|
|
|
/* REX cannot be combined with DREX or VEX */
|
|
if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
|
|
return false;
|
|
|
|
/*
|
|
* Check for unused rep or a/o prefixes.
|
|
*/
|
|
for (i = 0; i < t->operands; i++) {
|
|
if (ins->oprs[i].segment != SEG_RMREG)
|
|
a_used = true;
|
|
}
|
|
|
|
if (lock) {
|
|
if (ins->prefixes[PPS_LREP])
|
|
return false;
|
|
ins->prefixes[PPS_LREP] = P_LOCK;
|
|
}
|
|
if (drep) {
|
|
if (ins->prefixes[PPS_LREP])
|
|
return false;
|
|
ins->prefixes[PPS_LREP] = drep;
|
|
}
|
|
if (!o_used) {
|
|
if (osize != ((segsize == 16) ? 16 : 32)) {
|
|
enum prefixes pfx = 0;
|
|
|
|
switch (osize) {
|
|
case 16:
|
|
pfx = P_O16;
|
|
break;
|
|
case 32:
|
|
pfx = P_O32;
|
|
break;
|
|
case 64:
|
|
pfx = P_O64;
|
|
break;
|
|
}
|
|
|
|
if (ins->prefixes[PPS_OSIZE])
|
|
return false;
|
|
ins->prefixes[PPS_OSIZE] = pfx;
|
|
}
|
|
}
|
|
if (!a_used && asize != segsize) {
|
|
if (ins->prefixes[PPS_ASIZE])
|
|
return false;
|
|
ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
|
|
}
|
|
|
|
/* Fix: check for redundant REX prefixes */
|
|
|
|
return data - origdata;
|
|
}
|
|
|
|
/* Condition names for disassembly, sorted by x86 code */
|
|
static const char * const condition_name[16] = {
|
|
"o", "no", "c", "nc", "z", "nz", "na", "a",
|
|
"s", "ns", "pe", "po", "l", "nl", "ng", "g"
|
|
};
|
|
|
|
int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
|
|
int32_t offset, int autosync, uint32_t prefer)
|
|
{
|
|
const struct itemplate * const *p, * const *best_p;
|
|
const struct disasm_index *ix;
|
|
uint8_t *dp;
|
|
int length, best_length = 0;
|
|
char *segover;
|
|
int i, slen, colon, n;
|
|
uint8_t *origdata;
|
|
int works;
|
|
insn tmp_ins, ins;
|
|
uint32_t goodness, best;
|
|
int best_pref;
|
|
struct prefix_info prefix;
|
|
bool end_prefix;
|
|
|
|
memset(&ins, 0, sizeof ins);
|
|
|
|
/*
|
|
* Scan for prefixes.
|
|
*/
|
|
memset(&prefix, 0, sizeof prefix);
|
|
prefix.asize = segsize;
|
|
prefix.osize = (segsize == 64) ? 32 : segsize;
|
|
segover = NULL;
|
|
origdata = data;
|
|
|
|
ix = itable;
|
|
|
|
end_prefix = false;
|
|
while (!end_prefix) {
|
|
switch (*data) {
|
|
case 0xF2:
|
|
case 0xF3:
|
|
prefix.rep = *data++;
|
|
break;
|
|
|
|
case 0xF0:
|
|
prefix.lock = *data++;
|
|
break;
|
|
|
|
case 0x2E:
|
|
segover = "cs", prefix.seg = *data++;
|
|
break;
|
|
case 0x36:
|
|
segover = "ss", prefix.seg = *data++;
|
|
break;
|
|
case 0x3E:
|
|
segover = "ds", prefix.seg = *data++;
|
|
break;
|
|
case 0x26:
|
|
segover = "es", prefix.seg = *data++;
|
|
break;
|
|
case 0x64:
|
|
segover = "fs", prefix.seg = *data++;
|
|
break;
|
|
case 0x65:
|
|
segover = "gs", prefix.seg = *data++;
|
|
break;
|
|
|
|
case 0x66:
|
|
prefix.osize = (segsize == 16) ? 32 : 16;
|
|
prefix.osp = *data++;
|
|
break;
|
|
case 0x67:
|
|
prefix.asize = (segsize == 32) ? 16 : 32;
|
|
prefix.asp = *data++;
|
|
break;
|
|
|
|
case 0xC4:
|
|
case 0xC5:
|
|
if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
|
|
prefix.vex[0] = *data++;
|
|
prefix.vex[1] = *data++;
|
|
|
|
prefix.rex = REX_V;
|
|
|
|
if (prefix.vex[0] == 0xc4) {
|
|
prefix.vex[2] = *data++;
|
|
prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
|
|
prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
|
|
prefix.vex_m = prefix.vex[1] & 0x1f;
|
|
prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
|
|
prefix.vex_lp = prefix.vex[2] & 7;
|
|
} else {
|
|
prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
|
|
prefix.vex_m = 1;
|
|
prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
|
|
prefix.vex_lp = prefix.vex[1] & 7;
|
|
}
|
|
|
|
ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
|
|
}
|
|
end_prefix = true;
|
|
break;
|
|
|
|
case REX_P + 0x0:
|
|
case REX_P + 0x1:
|
|
case REX_P + 0x2:
|
|
case REX_P + 0x3:
|
|
case REX_P + 0x4:
|
|
case REX_P + 0x5:
|
|
case REX_P + 0x6:
|
|
case REX_P + 0x7:
|
|
case REX_P + 0x8:
|
|
case REX_P + 0x9:
|
|
case REX_P + 0xA:
|
|
case REX_P + 0xB:
|
|
case REX_P + 0xC:
|
|
case REX_P + 0xD:
|
|
case REX_P + 0xE:
|
|
case REX_P + 0xF:
|
|
if (segsize == 64) {
|
|
prefix.rex = *data++;
|
|
if (prefix.rex & REX_W)
|
|
prefix.osize = 64;
|
|
}
|
|
end_prefix = true;
|
|
break;
|
|
|
|
default:
|
|
end_prefix = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
best = -1; /* Worst possible */
|
|
best_p = NULL;
|
|
best_pref = INT_MAX;
|
|
|
|
if (!ix)
|
|
return 0; /* No instruction table at all... */
|
|
|
|
dp = data;
|
|
ix += *dp++;
|
|
while (ix->n == -1) {
|
|
ix = (const struct disasm_index *)ix->p + *dp++;
|
|
}
|
|
|
|
p = (const struct itemplate * const *)ix->p;
|
|
for (n = ix->n; n; n--, p++) {
|
|
if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
|
|
works = true;
|
|
/*
|
|
* Final check to make sure the types of r/m match up.
|
|
* XXX: Need to make sure this is actually correct.
|
|
*/
|
|
for (i = 0; i < (*p)->operands; i++) {
|
|
if (!((*p)->opd[i] & SAME_AS) &&
|
|
(
|
|
/* If it's a mem-only EA but we have a
|
|
register, die. */
|
|
((tmp_ins.oprs[i].segment & SEG_RMREG) &&
|
|
!(MEMORY & ~(*p)->opd[i])) ||
|
|
/* If it's a reg-only EA but we have a memory
|
|
ref, die. */
|
|
(!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
|
|
!(REG_EA & ~(*p)->opd[i]) &&
|
|
!((*p)->opd[i] & REG_SMASK)) ||
|
|
/* Register type mismatch (eg FS vs REG_DESS):
|
|
die. */
|
|
((((*p)->opd[i] & (REGISTER | FPUREG)) ||
|
|
(tmp_ins.oprs[i].segment & SEG_RMREG)) &&
|
|
!whichreg((*p)->opd[i],
|
|
tmp_ins.oprs[i].basereg, tmp_ins.rex))
|
|
)) {
|
|
works = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Note: we always prefer instructions which incorporate
|
|
* prefixes in the instructions themselves. This is to allow
|
|
* e.g. PAUSE to be preferred to REP NOP, and deal with
|
|
* MMX/SSE instructions where prefixes are used to select
|
|
* between MMX and SSE register sets or outright opcode
|
|
* selection.
|
|
*/
|
|
if (works) {
|
|
int i, nprefix;
|
|
goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
|
|
nprefix = 0;
|
|
for (i = 0; i < MAXPREFIX; i++)
|
|
if (tmp_ins.prefixes[i])
|
|
nprefix++;
|
|
if (nprefix < best_pref ||
|
|
(nprefix == best_pref && goodness < best)) {
|
|
/* This is the best one found so far */
|
|
best = goodness;
|
|
best_p = p;
|
|
best_pref = nprefix;
|
|
best_length = length;
|
|
ins = tmp_ins;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!best_p)
|
|
return 0; /* no instruction was matched */
|
|
|
|
/* Pick the best match */
|
|
p = best_p;
|
|
length = best_length;
|
|
|
|
slen = 0;
|
|
|
|
/* TODO: snprintf returns the value that the string would have if
|
|
* the buffer were long enough, and not the actual length of
|
|
* the returned string, so each instance of using the return
|
|
* value of snprintf should actually be checked to assure that
|
|
* the return value is "sane." Maybe a macro wrapper could
|
|
* be used for that purpose.
|
|
*/
|
|
for (i = 0; i < MAXPREFIX; i++)
|
|
switch (ins.prefixes[i]) {
|
|
case P_LOCK:
|
|
slen += snprintf(output + slen, outbufsize - slen, "lock ");
|
|
break;
|
|
case P_REP:
|
|
slen += snprintf(output + slen, outbufsize - slen, "rep ");
|
|
break;
|
|
case P_REPE:
|
|
slen += snprintf(output + slen, outbufsize - slen, "repe ");
|
|
break;
|
|
case P_REPNE:
|
|
slen += snprintf(output + slen, outbufsize - slen, "repne ");
|
|
break;
|
|
case P_A16:
|
|
slen += snprintf(output + slen, outbufsize - slen, "a16 ");
|
|
break;
|
|
case P_A32:
|
|
slen += snprintf(output + slen, outbufsize - slen, "a32 ");
|
|
break;
|
|
case P_A64:
|
|
slen += snprintf(output + slen, outbufsize - slen, "a64 ");
|
|
break;
|
|
case P_O16:
|
|
slen += snprintf(output + slen, outbufsize - slen, "o16 ");
|
|
break;
|
|
case P_O32:
|
|
slen += snprintf(output + slen, outbufsize - slen, "o32 ");
|
|
break;
|
|
case P_O64:
|
|
slen += snprintf(output + slen, outbufsize - slen, "o64 ");
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
i = (*p)->opcode;
|
|
if (i >= FIRST_COND_OPCODE)
|
|
slen += snprintf(output + slen, outbufsize - slen, "%s%s",
|
|
nasm_insn_names[i], condition_name[ins.condition]);
|
|
else
|
|
slen += snprintf(output + slen, outbufsize - slen, "%s",
|
|
nasm_insn_names[i]);
|
|
|
|
colon = false;
|
|
length += data - origdata; /* fix up for prefixes */
|
|
for (i = 0; i < (*p)->operands; i++) {
|
|
opflags_t t = (*p)->opd[i];
|
|
const operand *o = &ins.oprs[i];
|
|
int64_t offs;
|
|
|
|
if (t & SAME_AS) {
|
|
o = &ins.oprs[t & ~SAME_AS];
|
|
t = (*p)->opd[t & ~SAME_AS];
|
|
}
|
|
|
|
output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
|
|
|
|
offs = o->offset;
|
|
if (o->segment & SEG_RELATIVE) {
|
|
offs += offset + length;
|
|
/*
|
|
* sort out wraparound
|
|
*/
|
|
if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
|
|
offs &= 0xffff;
|
|
else if (segsize != 64)
|
|
offs &= 0xffffffff;
|
|
|
|
/*
|
|
* add sync marker, if autosync is on
|
|
*/
|
|
if (autosync)
|
|
add_sync(offs, 0L);
|
|
}
|
|
|
|
if (t & COLON)
|
|
colon = true;
|
|
else
|
|
colon = false;
|
|
|
|
if ((t & (REGISTER | FPUREG)) ||
|
|
(o->segment & SEG_RMREG)) {
|
|
enum reg_enum reg;
|
|
reg = whichreg(t, o->basereg, ins.rex);
|
|
if (t & TO)
|
|
slen += snprintf(output + slen, outbufsize - slen, "to ");
|
|
slen += snprintf(output + slen, outbufsize - slen, "%s",
|
|
nasm_reg_names[reg-EXPR_REG_START]);
|
|
} else if (!(UNITY & ~t)) {
|
|
output[slen++] = '1';
|
|
} else if (t & IMMEDIATE) {
|
|
if (t & BITS8) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "byte ");
|
|
if (o->segment & SEG_SIGNED) {
|
|
if (offs < 0) {
|
|
offs *= -1;
|
|
output[slen++] = '-';
|
|
} else
|
|
output[slen++] = '+';
|
|
}
|
|
} else if (t & BITS16) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "word ");
|
|
} else if (t & BITS32) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "dword ");
|
|
} else if (t & BITS64) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "qword ");
|
|
} else if (t & NEAR) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "near ");
|
|
} else if (t & SHORT) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "short ");
|
|
}
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
|
|
offs);
|
|
} else if (!(MEM_OFFS & ~t)) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen,
|
|
"[%s%s%s0x%"PRIx64"]",
|
|
(segover ? segover : ""),
|
|
(segover ? ":" : ""),
|
|
(o->disp_size == 64 ? "qword " :
|
|
o->disp_size == 32 ? "dword " :
|
|
o->disp_size == 16 ? "word " : ""), offs);
|
|
segover = NULL;
|
|
} else if (!(REGMEM & ~t)) {
|
|
int started = false;
|
|
if (t & BITS8)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "byte ");
|
|
if (t & BITS16)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "word ");
|
|
if (t & BITS32)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "dword ");
|
|
if (t & BITS64)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "qword ");
|
|
if (t & BITS80)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "tword ");
|
|
if (t & BITS128)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "oword ");
|
|
if (t & BITS256)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "yword ");
|
|
if (t & FAR)
|
|
slen += snprintf(output + slen, outbufsize - slen, "far ");
|
|
if (t & NEAR)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "near ");
|
|
output[slen++] = '[';
|
|
if (o->disp_size)
|
|
slen += snprintf(output + slen, outbufsize - slen, "%s",
|
|
(o->disp_size == 64 ? "qword " :
|
|
o->disp_size == 32 ? "dword " :
|
|
o->disp_size == 16 ? "word " :
|
|
""));
|
|
if (o->eaflags & EAF_REL)
|
|
slen += snprintf(output + slen, outbufsize - slen, "rel ");
|
|
if (segover) {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "%s:",
|
|
segover);
|
|
segover = NULL;
|
|
}
|
|
if (o->basereg != -1) {
|
|
slen += snprintf(output + slen, outbufsize - slen, "%s",
|
|
nasm_reg_names[(o->basereg-EXPR_REG_START)]);
|
|
started = true;
|
|
}
|
|
if (o->indexreg != -1) {
|
|
if (started)
|
|
output[slen++] = '+';
|
|
slen += snprintf(output + slen, outbufsize - slen, "%s",
|
|
nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
|
|
if (o->scale > 1)
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "*%d",
|
|
o->scale);
|
|
started = true;
|
|
}
|
|
|
|
|
|
if (o->segment & SEG_DISP8) {
|
|
const char *prefix;
|
|
uint8_t offset = offs;
|
|
if ((int8_t)offset < 0) {
|
|
prefix = "-";
|
|
offset = -offset;
|
|
} else {
|
|
prefix = "+";
|
|
}
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
|
|
prefix, offset);
|
|
} else if (o->segment & SEG_DISP16) {
|
|
const char *prefix;
|
|
uint16_t offset = offs;
|
|
if ((int16_t)offset < 0 && started) {
|
|
offset = -offset;
|
|
prefix = "-";
|
|
} else {
|
|
prefix = started ? "+" : "";
|
|
}
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen,
|
|
"%s0x%"PRIx16"", prefix, offset);
|
|
} else if (o->segment & SEG_DISP32) {
|
|
if (prefix.asize == 64) {
|
|
const char *prefix;
|
|
uint64_t offset = (int64_t)(int32_t)offs;
|
|
if ((int32_t)offs < 0 && started) {
|
|
offset = -offset;
|
|
prefix = "-";
|
|
} else {
|
|
prefix = started ? "+" : "";
|
|
}
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen,
|
|
"%s0x%"PRIx64"", prefix, offset);
|
|
} else {
|
|
const char *prefix;
|
|
uint32_t offset = offs;
|
|
if ((int32_t) offset < 0 && started) {
|
|
offset = -offset;
|
|
prefix = "-";
|
|
} else {
|
|
prefix = started ? "+" : "";
|
|
}
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen,
|
|
"%s0x%"PRIx32"", prefix, offset);
|
|
}
|
|
}
|
|
output[slen++] = ']';
|
|
} else {
|
|
slen +=
|
|
snprintf(output + slen, outbufsize - slen, "<operand%d>",
|
|
i);
|
|
}
|
|
}
|
|
output[slen] = '\0';
|
|
if (segover) { /* unused segment override */
|
|
char *p = output;
|
|
int count = slen + 1;
|
|
while (count--)
|
|
p[count + 3] = p[count];
|
|
strncpy(output, segover, 2);
|
|
output[2] = ' ';
|
|
}
|
|
return length;
|
|
}
|
|
|
|
int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
|
|
{
|
|
snprintf(output, outbufsize, "db 0x%02X", *data);
|
|
return 1;
|
|
}
|