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cb9b690ae6
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the previous \332 flag changed to \335). This is necessary to get the REX prefix in the right place for instructions that use it. We are going to have to go in and change existing instruction patterns which use these, as well.
113 lines
5.2 KiB
C
113 lines
5.2 KiB
C
/* insns.h header file for insns.c
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*
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* The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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* Julian Hall. All rights reserved. The software is
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* redistributable under the licence given in the file "Licence"
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* distributed in the NASM archive.
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*/
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#ifndef NASM_INSNS_H
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#define NASM_INSNS_H
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#include "insnsi.h" /* instruction opcode enum */
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/* max length of any instruction, register name etc. */
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#if MAX_INSLEN > 9 /* MAX_INSLEN defined in insnsi.h */
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#define MAX_KEYWORD MAX_INSLEN
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#else
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#define MAX_KEYWORD 9
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#endif
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struct itemplate {
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enum opcode opcode; /* the token, passed from "parser.c" */
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int operands; /* number of operands */
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int32_t opd[3]; /* bit flags for operand types */
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const char *code; /* the code it assembles to */
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uint32_t flags; /* some flags */
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};
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/* Tables for the assembler and disassembler, respectively */
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extern const struct itemplate * const nasm_instructions[];
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extern const struct itemplate * const * const itable[];
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/*
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* this define is used to signify the end of an itemplate
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*/
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#define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0}
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/*
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* Instruction template flags. These specify which processor
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* targets the instruction is eligible for, whether it is
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* privileged or undocumented, and also specify extra error
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* checking on the matching of the instruction.
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*
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* IF_SM stands for Size Match: any operand whose size is not
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* explicitly specified by the template is `really' intended to be
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* the same size as the first size-specified operand.
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* Non-specification is tolerated in the input instruction, but
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* _wrong_ specification is not.
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*
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* IF_SM2 invokes Size Match on only the first _two_ operands, for
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* three-operand instructions such as SHLD: it implies that the
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* first two operands must match in size, but that the third is
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* required to be _unspecified_.
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*
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* IF_SB invokes Size Byte: operands with unspecified size in the
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* template are really bytes, and so no non-byte specification in
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* the input instruction will be tolerated. IF_SW similarly invokes
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* Size Word, and IF_SD invokes Size Doubleword.
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*
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* (The default state if neither IF_SM nor IF_SM2 is specified is
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* that any operand with unspecified size in the template is
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* required to have unspecified size in the instruction too...)
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*/
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#define IF_SM 0x00000001UL /* size match */
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#define IF_SM2 0x00000002UL /* size match first two operands */
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#define IF_SB 0x00000004UL /* unsized operands can't be non-byte */
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#define IF_SW 0x00000008UL /* unsized operands can't be non-word */
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#define IF_SD 0x00000010UL /* unsized operands can't be non-dword */
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#define IF_SQ 0x00000020UL /* unsized operands can't be non-qword */
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#define IF_AR0 0x00000040UL /* SB, SW, SD applies to argument 0 */
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#define IF_AR1 0x00000080UL /* SB, SW, SD applies to argument 1 */
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#define IF_AR2 0x000000C0UL /* SB, SW, SD applies to argument 2 */
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#define IF_ARMASK 0x000000C0UL /* mask for unsized argument spec */
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#define IF_PRIV 0x00000100UL /* it's a privileged instruction */
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#define IF_SMM 0x00000200UL /* it's only valid in SMM */
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#define IF_PROT 0x00000400UL /* it's protected mode only */
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#define IF_NOLONG 0x00000800UL /* it's not available in long mode */
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#define IF_UNDOC 0x00001000UL /* it's an undocumented instruction */
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#define IF_FPU 0x00002000UL /* it's an FPU instruction */
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#define IF_MMX 0x00004000UL /* it's an MMX instruction */
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#define IF_3DNOW 0x00008000UL /* it's a 3DNow! instruction */
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#define IF_SSE 0x00010000UL /* it's a SSE (KNI, MMX2) instruction */
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#define IF_SSE2 0x00020000UL /* it's a SSE2 instruction */
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#define IF_SSE3 0x00040000UL /* it's a SSE3 (PNI) instruction */
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#define IF_VMX 0x00080000UL /* it's a VMX instruction */
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#define IF_LONG 0x00100000UL /* long mode instruction */
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#define IF_SSSE3 0x00200000UL /* it's an SSSE3 instruction */
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#define IF_SSE41 0x00400000UL /* it's an SSE4.1 instruction */
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#define IF_SSE42 0x00800000UL /* it's an SSE4.2 instruction */
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#define IF_PMASK 0xFF000000UL /* the mask for processor types */
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#define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
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/* also the highest possible processor */
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#define IF_PFMASK 0xF01FFF00UL /* the mask for disassembly "prefer" */
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#define IF_8086 0x00000000UL /* 8086 instruction */
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#define IF_186 0x01000000UL /* 186+ instruction */
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#define IF_286 0x02000000UL /* 286+ instruction */
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#define IF_386 0x03000000UL /* 386+ instruction */
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#define IF_486 0x04000000UL /* 486+ instruction */
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#define IF_PENT 0x05000000UL /* Pentium instruction */
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#define IF_P6 0x06000000UL /* P6 instruction */
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#define IF_KATMAI 0x07000000UL /* Katmai instructions */
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#define IF_WILLAMETTE 0x08000000UL /* Willamette instructions */
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#define IF_PRESCOTT 0x09000000UL /* Prescott instructions */
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#define IF_X86_64 0x0A000000UL /* x86-64 instruction (long or legacy mode) */
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#define IF_NEHALEM 0x0B000000UL /* Nehalem instruction */
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#define IF_X64 (IF_LONG|IF_X86_64)
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#define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */
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#define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */
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#define IF_AMD 0x20000000UL /* AMD-specific instruction */
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#endif
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