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128 lines
3.2 KiB
NASM
128 lines
3.2 KiB
NASM
;Testname=test; Arguments=-fbin -ofpu.bin; Files=.stdout .stderr fpu.bin
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; relaxed encodings for FPU instructions, which NASM should support
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; -----------------------------------------------------------------
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%define void
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%define reg_fpu0 st0
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%define reg_fpu st1
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; no operands instead of one operand:
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; F(U)COM(P), FCOM2, FCOMP3, FCOMP5
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FCOM void
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FCOMP void
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FUCOM void
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FUCOMP void
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; FCOM2 void
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; FCOMP3 void
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; FCOMP5 void
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; FLD, FST, FSTP, FSTP1, FSTP8, FSTP9
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FLD void
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FST void
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FSTP void
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; FSTP1 void
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; FSTP8 void
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; FSTP9 void
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; FXCH, FXCH4, FXCH7, FFREE, FFREEP
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FXCH void
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; FXCH4 void
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; FXCH7 void
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FFREE void
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FFREEP void
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; no operands instead of two operands:
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; FADD(P), FMUL(P), FSUBR(P), FSUB(P), FDIVR(P), FDIV(P)
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FADD void
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FADDP void
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FMUL void
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FMULP void
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FSUBR void
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FSUBRP void
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FSUB void
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FSUBP void
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FDIVR void
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FDIVRP void
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FDIV void
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FDIVP void
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; one operand instead of two operands:
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; FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR
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FADD reg_fpu
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FMUL reg_fpu
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FSUB reg_fpu
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FSUBR reg_fpu
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FDIV reg_fpu
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FDIVR reg_fpu
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; FADD, FMUL, FSUBR, FSUB, FDIVR, FDIV (with TO qualifier)
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FADD to reg_fpu
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FMUL to reg_fpu
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FSUBR to reg_fpu
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FSUB to reg_fpu
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FDIVR to reg_fpu
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FDIV to reg_fpu
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; FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP
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FADDP reg_fpu
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FMULP reg_fpu
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FSUBRP reg_fpu
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FSUBP reg_fpu
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FDIVRP reg_fpu
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FDIVP reg_fpu
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; FCMOV(N)B, FCMOV(N)E, FCMOV(N)BE, FCMOV(N)U, and F(U)COMI(P)
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FCMOVB reg_fpu
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FCMOVNB reg_fpu
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FCMOVE reg_fpu
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FCMOVNE reg_fpu
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FCMOVBE reg_fpu
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FCMOVNBE reg_fpu
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FCMOVU reg_fpu
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FCMOVNU reg_fpu
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FCOMI reg_fpu
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FCOMIP reg_fpu
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FUCOMI reg_fpu
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FUCOMIP reg_fpu
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; two operands instead of one operand:
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; these don't really exist, and thus are _NOT_ supported:
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; FCOM reg_fpu,reg_fpu0
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; FCOM reg_fpu0,reg_fpu
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; FUCOM reg_fpu,reg_fpu0
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; FUCOM reg_fpu0,reg_fpu
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; FCOMP reg_fpu,reg_fpu0
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; FCOMP reg_fpu0,reg_fpu
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; FUCOMP reg_fpu,reg_fpu0
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; FUCOMP reg_fpu0,reg_fpu
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; FCOM2 reg_fpu,reg_fpu0
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; FCOM2 reg_fpu0,reg_fpu
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; FCOMP3 reg_fpu,reg_fpu0
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; FCOMP3 reg_fpu0,reg_fpu
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; FCOMP5 reg_fpu,reg_fpu0
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; FCOMP5 reg_fpu0,reg_fpu
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; FXCH reg_fpu,reg_fpu0
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; FXCH reg_fpu0,reg_fpu
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; FXCH4 reg_fpu,reg_fpu0
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; FXCH4 reg_fpu0,reg_fpu
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; FXCH7 reg_fpu,reg_fpu0
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; FXCH7 reg_fpu0,reg_fpu
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; EOF
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