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https://github.com/netwide-assembler/nasm.git
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99c4ecd18f
Implement "REL" and "ABS" modifiers for offsets in 64-bit mode. This replaces "rip+XXX" type addressing. The infrastructure to set the default mode is there, but there is nothing to throw the switch just yet.
83 lines
1.6 KiB
Plaintext
83 lines
1.6 KiB
Plaintext
# $Id$
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#
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# List of registers and their classes; classes are defined in nasm.h
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#
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# The columns are:
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#
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# register name, assembler class, disassembler class(es), x86 register number
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#
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# If the register name ends in two numbers separated by a dash, then it is
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# repeated as many times as indicated, and the register number is
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# updated with it.
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#
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# General-purpose registers
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al REG_AL reg8,reg8_rex 0
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ah REG_HIGH reg8 4
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ax REG_AX reg16 0
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eax REG_EAX reg32 0
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rax REG_RAX reg64 0
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bl REG8 reg8,reg8_rex 3
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bh REG_HIGH reg8 7
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bx REG16 reg16 3
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ebx REG32 reg32 3
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rbx REG64 reg64 3
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cl REG_CL reg8,reg8_rex 1
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ch REG_HIGH reg8 5
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cx REG_CX reg16 1
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ecx REG_ECX reg32 1
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rcx REG_RCX reg64 1
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dl REG_DL reg8,reg8_rex 2
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dh REG_HIGH reg8 6
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dx REG_DX reg16 2
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edx REG_EDX reg32 2
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rdx REG_RDX reg64 2
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spl REG8 reg8_rex 4
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sp REG16 reg16 4
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esp REG32 reg32 4
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rsp REG64 reg64 4
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bpl REG8 reg8_rex 5
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bp REG16 reg16 5
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ebp REG32 reg32 5
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rbp REG64 reg64 5
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sil REG8 reg8_rex 6
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si REG16 reg16 6
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esi REG32 reg32 6
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rsi REG64 reg64 6
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dil REG8 reg8_rex 7
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di REG16 reg16 7
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edi REG32 reg32 7
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rdi REG64 reg64 7
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r8-15b REG8 reg8_rex 8
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r8-15w REG16 reg16 8
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r8-15d REG32 reg32 8
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r8-15 REG64 reg64 8
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# Segment registers
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cs REG_CS sreg 1
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ds REG_DESS sreg 3
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es REG_DESS sreg 0
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ss REG_DESS sreg 2
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fs REG_FSGS sreg 4
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gs REG_FSGS sreg 5
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segr6-7 REG_SEG67 sreg 6
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# Control registers
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cr0-15 REG_CREG creg 0
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# Debug registers
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dr0-15 REG_DREG dreg 0
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# Test registers
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tr0-7 REG_TREG treg 0
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# Floating-point registers
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st0 FPU0 fpureg 0
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st1-7 FPUREG fpureg 1
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# MMX registers
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mm0-7 MMXREG mmxreg 0
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# SSE registers
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xmm0-15 XMMREG xmmreg 0
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