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https://github.com/netwide-assembler/nasm.git
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164d60740f
Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
136 lines
3.9 KiB
Plaintext
136 lines
3.9 KiB
Plaintext
## --------------------------------------------------------------------------
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##
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## Copyright 1996-2009 The NASM Authors - All Rights Reserved
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## See the file AUTHORS included with the NASM distribution for
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## the specific copyright holders.
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##
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## Redistribution and use in source and binary forms, with or without
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## modification, are permitted provided that the following
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## conditions are met:
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##
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## * Redistributions of source code must retain the above copyright
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## notice, this list of conditions and the following disclaimer.
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## * Redistributions in binary form must reproduce the above
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## copyright notice, this list of conditions and the following
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## disclaimer in the documentation and/or other materials provided
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## with the distribution.
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##
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## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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##
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## --------------------------------------------------------------------------
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#
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# List of registers and their classes; classes are defined in nasm.h
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#
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# The columns are:
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#
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# register name, assembler class, disassembler class(es), x86 register number[, token flag]
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#
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# If the register name ends in two numbers separated by a dash, then it is
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# repeated as many times as indicated, and the register number is
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# updated with it.
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#
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# If 'token flag' is present, this value will be assigned to tokflag field in
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# 'struct tokendata tokendata[]' table. Token flag can be used for specifying
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# special usage of corresponding register. E.g. opmask registers can be either
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# enclosed by curly braces or standalone operand depending on the usage.
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#
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# General-purpose registers
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al REG_AL reg8,reg8_rex 0
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ah REG_HIGH reg8 4
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ax REG_AX reg16 0
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eax REG_EAX reg32 0
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rax REG_RAX reg64 0
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bl REG8NA reg8,reg8_rex 3
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bh REG_HIGH reg8 7
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bx REG16NA reg16 3
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ebx REG32NA reg32 3
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rbx REG64NA reg64 3
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cl REG_CL reg8,reg8_rex 1
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ch REG_HIGH reg8 5
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cx REG_CX reg16 1
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ecx REG_ECX reg32 1
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rcx REG_RCX reg64 1
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dl REG_DL reg8,reg8_rex 2
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dh REG_HIGH reg8 6
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dx REG_DX reg16 2
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edx REG_EDX reg32 2
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rdx REG_RDX reg64 2
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spl REG8NA reg8_rex 4
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sp REG16NA reg16 4
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esp REG32NA reg32 4
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rsp REG64NA reg64 4
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bpl REG8NA reg8_rex 5
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bp REG16NA reg16 5
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ebp REG32NA reg32 5
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rbp REG64NA reg64 5
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sil REG8NA reg8_rex 6
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si REG16NA reg16 6
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esi REG32NA reg32 6
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rsi REG64NA reg64 6
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dil REG8NA reg8_rex 7
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di REG16NA reg16 7
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edi REG32NA reg32 7
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rdi REG64NA reg64 7
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r8-15b REG8NA reg8_rex 8
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r8-15w REG16NA reg16 8
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r8-15d REG32NA reg32 8
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r8-15 REG64NA reg64 8
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# Segment registers
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es REG_ES sreg 0
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cs REG_CS sreg 1
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ss REG_SS sreg 2
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ds REG_DS sreg 3
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fs REG_FS sreg 4
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gs REG_GS sreg 5
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segr6-7 REG_SEG67 sreg 6
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# Control registers
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cr0-15 REG_CREG creg 0
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# Debug registers
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dr0-15 REG_DREG dreg 0
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# Test registers
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tr0-7 REG_TREG treg 0
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# Floating-point registers
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st0 FPU0 fpureg 0
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st1-7 FPUREG fpureg 1
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# MMX registers
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mm0-7 MMXREG mmxreg 0
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# SSE registers
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xmm0 XMM0 xmmreg 0
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xmm1-31 XMMREG xmmreg 1
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# AVX registers
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ymm0 YMM0 ymmreg 0
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ymm1-31 YMMREG ymmreg 1
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# AVX512 registers
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zmm0 ZMM0 zmmreg 0
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zmm1-31 ZMMREG zmmreg 1
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# Opmask registers
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k0 OPMASK0 opmaskreg 0
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k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT
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# Bounds registers
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bnd0-3 BNDREG bndreg 0
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