mirror of
https://github.com/netwide-assembler/nasm.git
synced 2024-11-21 03:14:19 +08:00
b106ba161f
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6
and reverted in:
d279fbbd80
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
16 lines
214 B
NASM
16 lines
214 B
NASM
bits 64
|
|
|
|
movd r8d, mm1
|
|
movd r8, mm1
|
|
movq r8, mm1
|
|
|
|
movd [rax], mm1
|
|
movq [rax], mm1
|
|
movd dword [rax], mm1
|
|
; movq dword [rax], mm1
|
|
movd qword [rax], mm1
|
|
movq qword [rax], mm1
|
|
|
|
; movd mm2, mm1
|
|
movq mm2, mm1
|