H. Peter Anvin 7f688841ce insns.dat: accept explicit ax/eax/rax operand to CLZERO ... AMD documents this instruction with an rax operand. The error behavior implies this is an address-size-sensitive instruction. Add support for specifying the explicit operand, but consistent with normal ndisasm behavior, don't disassemble the implicit operand. Signed-off-by: H. Peter Anvin <hpa@zytor.com>		2018-12-22 17:52:27 -08:00
..
disp8.c	disp8: make constant arrays in get_disp8N() static	2016-08-25 17:40:13 -07:00
insns-iflags.ph	insns.dat: add Intel Software Guard Extensions (SGX) instructions	2018-06-25 23:09:38 -07:00
insns.dat	insns.dat: accept explicit ax/eax/rax operand to CLZERO	2018-12-22 17:52:27 -08:00
insns.pl	Don't sort opcodes; move all pseudo-ops to the beginning	2017-05-01 21:44:24 -07:00
regs.dat	Reorganize the source code into subdirectories	2016-05-25 12:06:29 -07:00
regs.pl	perl: change to the new, safer 3-operand form of open()	2017-04-02 19:36:41 -07:00