The 256-bit form of the VORPD instruction was deleted in checkin
89a38dac363c45d5309001a710f8cf44e7833f81, apparently by mistake.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The 82h opcodes are undocumented aliases for the 80h opcodes, except
in 64-bit mode. We don't generate them, but let the disassembler
handle them correctly.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The moffset opcodes A2 and A3 do not support HLE. Unfortunately
checkin
fb3f4e6d HLE: Change NOHLE to be an instruction flag
... inadvertently lost the NOHLE flag for opcode A2.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add norexw to the 32-bit versions of instructions with only 32- and
64-bit forms (66 ignored as a size override.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
New instructions (ADCX, ADOX, RDSEED) from the 013 AVX spec
(Intel® Architecture Instruction Set Extensions Programming
Reference).
Note: ADCX in 64-bit mode disassembles incorrectly with a 64-bit
argument. This still needs to be fixed before a 2.10.02 release.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6c437c50452c4997aa2e3de5a0e0299
and reverted in:
d279fbbd80aab6f79584249629a4aea90b851458
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The way our matching system works we have to make NOHLE an instruction
flag rather than an byte code; by the time we run the byte code
interpreter we have already picked an instruction pattern once and for
all.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Clean up JMP/CALL patterns so they don't disassemble quite so uglily.
Fix a CALL pattern which would have incorrectly generated a (harmless)
REX.W prefix.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Get rid of the last vestiges of the explicit byte codes in insns.dat.
The only files that now depend on actual byte code numbers are
insns.pl, assemble.c and disasm.c.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This reverts commit 70712c0df6c437c50452c4997aa2e3de5a0e0299.
Conflicts:
insns.dat
Our instructions matcher fuzzy logic fails to handle it at moment.
Reported-by: KO Myung-Hun <komh@chollian.net>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AMD has MOVD for both 32bit and 64bit GPRs so in a sake of
compatibility bring them into insns.dat.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
As being spotted by nasm64developer the memory
operands size is incorrect. Fix it.
Reported-by: nasm64developer
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
