Since we are back to three bytecodes, move them back to the \271-\273
slot to free up the \264 complete quad.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The way our matching system works we have to make NOHLE an instruction
flag rather than an byte code; by the time we run the byte code
interpreter we have already picked an instruction pattern once and for
all.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Get rid of the last vestiges of the explicit byte codes in insns.dat.
The only files that now depend on actual byte code numbers are
insns.pl, assemble.c and disasm.c.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add an LOCK flag to the instruction template, and make the presence of
a LOCK prefix trigger a warning if it is not set. Simplify the LOCK
and HLE logic by hard-coding the knowledge that operand 0 has to be
memory.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The a2/a3 mem_offs MOV opcodes are invalid with XRELEASE; those
instructions instead have to use a modrm form. Therefore give a way
to annotate those instruction patters so the pattern matcher will move
on to the next pattern, rather than selecting them and then issue a
warning.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This implements the mechanism for XACQUIRE/XRELEASE. It does not
include the necessary annotations in insns.dat.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
insn->prefixes might contain not only values from
'enum prefixes' but from 'enum reg_enum' as well so
make it generic 'int' instead.
This calms down the compiler about enum's mess and
eliminates a wrong assumption that we always have
values by particular type in this field.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
- GEN_SIB and GEN_MODRM helpers added
- a number of tabs vs space fixs
- more use of is_class() helper
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
When we don't have an immediate for the i-field in /is4, then use a
normal quad-bytecode encoding for it to save some small amount of
space and re-use existing machinery.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
The DREX encoding never hit production silicon, and has been replaced
by VEX/XOP encoding, so remove support for it.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
It is more logical, it cleans up the code and it makes implicit
operand size override prefixes come out in the same order as explicit
ones instead of after all other prefixes.
Suggested-by: H. Peter Anvin <hpa@zytor.com>
calcsize() had the wrong criterion for when C5 prefixes are permitted
(REX.R is permitted, REX.X is forbidden.) assemble() had the right
test already. This caused symbol value errors.
The implicit operand size override code didn't set the operand size
prefix, which confused the size calculation code for the range check.
The BITS 64 operand size calculation is still off, but "fixing" it by
making it 32-bit unless REX.W is set breaks PUSH and maybe others.
Change the .wx (ignore the W field) to .wig, to match the latest
version of the AVX specification. This is not a functional change,
but just makes instruction patterns a little easier to write.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Two fixes:
1. Optimization of [bx+0xFFFF] etc
0xFFFF is an sbyte under 16-bit semantics,
so make sure to check it right.
2. Don't optimize displacements in -O0
Displacements that fit into an sbyte or
can be removed should *not* be optimized in -O0.
Implicit zero displacements are still optimized, e.g.:
[eax] -> 0 bit displacement, [ebp] -> 8 bit displacement.
However explicit displacements are not optimized:
[eax+0] -> 32 bit displacement, [ebp+0] -> 32 bit displacement.
Because #2 breaks compatibility with 0.98,
I introduced a new optimization level: -OL, legacy.
Add OUT_REL1ADR (one-byte relative address) and support for
OUT_ADDRESs with size == 1. Add support for it in
outbin and outdbg. *It still needs to be added to other backends*,
both the OUT_REL*ADR and OUT_ADDRESS codepaths need to be handled.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Check if the offset and the representation are equivalent.
Disallow REL on absolute addresses.
I'm not sure what that would mean and the output formats don't support it.
Warn about ignored displacement size modifiers.
We may throw out j variable (since we break anyway)
and don't assign asize for free (since we don't
use it after).
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Hopefully this should catch all of them... but please keep an eye out
for any other uses of int32_t for the operand flags.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
is_class does not checking flags "strictly". Which means
it may fail if type is specified to REGMEM and you check for
is_class(MEMORY, ...).
Anyway in current patch we check for REGISTER which doesn't
overlap and it is safe to use is_class here.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Do an "exclusive" test for a REGISTER operand when deciding to treat
sizes as wildcards. "Exclusive" meaning don't just accept any class
that could be REGISTER, but something that is strictly a part of the
REGISTER class.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Register with no size are a bit special: we don't honor extrinsic
register sizes in the first place ("oword xmm1" gives a warning,
even), and they should match any xmmrm size. As such, explicitly
handle sizeless register operands as a hard match, instead of relying
on the fuzzy-matching mechanism to handle them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Consolidate I_none opcode to be used everywhere
instead of mix (-1,I_none).
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
