The UMOV opcodes have been recycled; tag UMOV as ND until we have a
better way to specify to the disassembler exactly how it wants
instructions interpreted.
Document that %+ needs a space after it due to collision with %+1
syntax for multiline macro arguments; make it issue an error message
rather than crashing.
The current version of "git tag" seems to demand that the options
precede arguments; the name is an argument, but the -m option and its
parameter is an option.
Update nasm.spec.in to match modern conventions, and make it handle rc
releases by using the "mangled" version of the name (1.99.99.91
instead of 2.0rc1).
Support version numbers of the form X.Y[.Z]rcW where X, Y, Z and W are
numbers. For the numeric macros, drop them down to a lower level, so
2.0rc1 is treated as version 1.99.99.91.
Instead of returning -1 from nasm_token_hash, set tv->t_type to
TOKEN_ID and return TOKEN_ID, since that's what stdscan.c wants to do
with it anyway. This allows us to simply tailcall nasm_token_hash().
Unify all the standard IEEE formats into one function, add support for
IEEE standard 128-bit floating point numbers.
The 80-bit format is still special since it explicitly represents the
integer portion.
0F 1F /0 is documented as an EA-taking NOP since the P6.
0F 18..1F + EA are all "hinting nops" (instructions which, when
unimplemented, have no effect rather than #UD) but 0F 1F /0
specifically has no operation whatsoever.
0FC2 is not really an instruction prefix; it's the opcode for
CMPPS/CMPSS, which takes a control immediate which Intel chose to have
opcode aliases for. However, we can't dispatch on a tail byte, so
it's useless.
Modify the disassembler so that we can have separate instruction
tables for prefixed instructions. As it was, all instructions which
started with 0F were linearly searched, and that is by now more than
half the instruction set.
Implement oword, reso, do, as well as the SO flag to instructions. No
instructions are actually flagged with SO yet, but this allows us to
specify 128-bit sizes in instruction patterns.
Combining arithmetric (add) and bitwise (xor) mixing seems to give
better result than either.
With the new prehash function, we find a valid hash much quicker.
This checkin completes what is required to actually generate SSE5
instructions. No support in the disassembler yet.
This checkin covers:
- Support for actually generating DREX prefixes.
- Support for matching operand "operand X must match Y"
