INVLPGA is defined as taking rax,ecx but "the portion of rax used to
form the address is determined by the effective address size", so it
is really ax/eax/rax.
Auto-generate 0x67 prefixes without the need for \30x codes; the
prefix is automatically added when there is a memory operand with
address size differing from the current address size (and impossible
combinations checked for.)
The UMOV opcodes have been recycled; tag UMOV as ND until we have a
better way to specify to the disassembler exactly how it wants
instructions interpreted.
0F 1F /0 is documented as an EA-taking NOP since the P6.
0F 18..1F + EA are all "hinting nops" (instructions which, when
unimplemented, have no effect rather than #UD) but 0F 1F /0
specifically has no operation whatsoever.
Implement oword, reso, do, as well as the SO flag to instructions. No
instructions are actually flagged with SO yet, but this allows us to
specify 128-bit sizes in instruction patterns.
This checkin completes what is required to actually generate SSE5
instructions. No support in the disassembler yet.
This checkin covers:
- Support for actually generating DREX prefixes.
- Support for matching operand "operand X must match Y"
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be
a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the
previous \332 flag changed to \335). This is necessary to get the REX
prefix in the right place for instructions that use it.
We are going to have to go in and change existing instruction patterns
which use these, as well.
Use a script to find \321's that should be \324's. This is not in any
way guaranteed to be an exhaustive list, however, I have manually verified
that all the items that *were* changed *should* be changed.
- MOV gpr,CRx or MOV CRx,gpr can access high control registers with a LOCK
prefix; handle that in both the assembler and disassembler.
- Get a saner error message when trying to access high resources in
non-64-bit mode.
The assembler doesn't seem to care, but for the disassembler, it's
vitally important that we get our operand-size hints correctly. We
probably need to audit insns.dat for this kinds of errors.
CR8 is not special in any way as far as the assembler is concerned. It's
listed as having a special form in the Intel documentation, but that is
only because there are no other CRs which require a REX prefix.
MOV to CR8 is special in the sense that it's a non-serializing
instruction, but that's irrelevant to the assembler.
Furthermore, it's totally unclear how TRs should be handled in long mode;
there are no CPUs which uses TRs which also have long mode, so the easiest
is to simply mark those instructions NOLONG.
Finally, add PRIV to some privileged instructions.
