Change \40 class opcodes which need to be changed to \254. IMUL will
need a separate audit; I'm not convinced we are really sure what all
the IMUL conditions should be.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add a new opcode for 32->64 bit sign-extended immediate, with warning
on the number not matching.
This unfortunately calls for an audit of all the \4[0123] opcodes, if
they should be replaced by \25[4567]. This only replaces one
instruction (MOV reg64,imm32); other instructions need to be
considered.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
New opcodes to deal with 8-bit immediates which are then sign-extended
to the operand size. These allow us to warn appropriately.
Not sure I'm using these in all the proper places; need audit of all
uses of the \14..\17 opcodes.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Issue better warnings for out-of-range values. This is not yet
complete.
In particular, note we may have out-of-range for values that end up
being subject to optimization. That is because the optimization takes
place on the *truncated* value, not the pre-truncated value.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The official mnemonic for 32-to-64-bit sign extension is MOVSXD for
some idiotic reason. Add support for it while continue to recognize
MOVSX for this as an alias.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Handle SLDT with a 64-bit register operand. Don't generate a REX.W
prefix in the assembler, since zero-extending is just fine, but do
support it in the disassembler.
BR 1974170: VCVTPD2PS, VCVTPD2DQ, VCVTTPD2DQ with a memory operand are
ambiguous without a specific operand size, so force one to be added.
Split the instruction pattern due to our current clunky handling of
MMX/XMM/YMM registers together with sizes. Fix in the future, please!
For the versions of VCMPxx which already embed their condition code,
we do not want an extra immediate argument.
Todo: fix bytecode compiler to complain more about these.
Make our way through the AVX instructions: conversions.
This is all I have time for now... hopefully this can service as a
generous source of examples.
Accept the gas mnemonics "ud2a" and "ud2b" for the instructions we
call ud2 and ud1 respectively, and Intel call ud2 and undocumented :)
Also, 0F FF is ud0 regardless of prefixes, at least as far as we know.
Use compiler-generated bytecodes for the AVX instruction demos. This
should make it a lot easier for other people (HINT, HINT) to add the
instruction table.
First cut at AVX machinery support. The only instruction implemented
is VPERMIL2PS, and it's probably buggy. I'm checking this in with the
hope that other people can start helping out with (a) testing this,
and (b) adding instructions.
NDISASM support is not there yet.
Add "MOV reg64,imm32" as a special rule, to handle the case of
"mov rax,dword <foo>", where <foo> is sign-extended; this is a 7-byte
form, as opposed to "mov eax,<foo>" (5 bytes) and "mov rax,<foo>" (10
bytes).
At some point, the optimizer needs to be able to handle these.
Add the XSAVE group of instructions: XSAVE, XRSTOR, XGETBV, XSETBV.
The CPU feature information is bogus, but so is our entire handling of
CPU feature sets for anything but the bare necessities (long jump
emulation, etc.)
1. Allow included files in rdsrc.pl
2. New program inslist.pl to generate instruction list from insns.dat
3. Mark certain comments in insns.dat as documentation subheaders
4. Add Instruction List appendix to nasmdoc.src
5. Update build process to invoke inslist.pl
Mark MMX instructions with \323 (do not add REX.W) unless they involve
the integer instruction file.
Change SM -> SQ for MMX instructions.
Something not complete attached, so my understanding is
mmxreg,mmxrm needs SQ
Something like xmmreg,reg32 needs SD
xmmreg,xmmrm needs SO
The CMPSW/CMPSD/CMPSQ instructions were broken by checkin
a30cc07224 due to an incorrect removal
of \1 (should only have been removed after \144-147 and \154-157). I
have verified that no other instructions were affected.
- Correct the building on the disassembler decision tree.
- Handle SSE instructions with F2 prefix (\332) correctly.
- Mark instructions which are now used as prefixes with ND.
(In a future version when we have better CPU version handling,
we should probably build the decision tree at runtime based on
the selected CPU feature sets.)
- Sanitize the handling of \144-147 and \154-157 in both the assembler
and disassembler. They take an opcode byte as argument; don't
pretend they don't.
Support the zero-operand form of floating-point instructions. Note
that in most cases, the form generated is actually the "popping" form,
e.g. "FADD" becomes "FADDP st0,st1". This is in accordance with the
Intel documentation. "FADDP" is also supported.
Un-special-case "xchg rax,rax"; allow it to be encoded as 48 90 for
orthogonality's sake. It's a no-op, to be sure, but so are many other
instructions.
"xchg eax,eax" is still special-cased in 64-bit mode since it is not a
no-op; unadorned opcode 90 is now simply "nop" and nothing else.
Make the disassembler detect unused REX.W and display them as an "o64"
prefix.
Revamp the address- and prefix-handling code to make more sense in
64-bit mode. We are now a lot closer to where we want to be, but
we're not quite there yet.
ndisasm may very well have problems, or give counterintuitive output.
However, checking it in so we can make forward progress.
0F 18-1F are reserved for hinting NOPs; they all take a single memory
operand which may be sized. Allow the use of systematic names; this
also makes sure they get sensibly disassembled.
INVLPGA is defined as taking rax,ecx but "the portion of rax used to
form the address is determined by the effective address size", so it
is really ax/eax/rax.
Auto-generate 0x67 prefixes without the need for \30x codes; the
prefix is automatically added when there is a memory operand with
address size differing from the current address size (and impossible
combinations checked for.)
