Test case from bug 3392538 for double free in the listing module.
This is the test case only, not a fix.
Reported-by: <russyz@comcast.net>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
AMD documents this instruction with an rax operand. The error behavior
implies this is an address-size-sensitive instruction. Add support for
specifying the explicit operand, but consistent with normal ndisasm
behavior, don't disassemble the implicit operand.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Support the +n syntax for multiple contiguous registers, and emit it
in the output from ndisasm as well.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
absolute.asm is useful even for other backends, so explicitly test to
see if ORG is possible for this format.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Add a simple test case for context-local (%$) labels not disturbing
the local variable namespace, and extern labels getting promoted to
global.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
There are cases where we may want to implement generic pragmas, while
still make them selective based on output and/or debug formats.
Initially, use this for the prefix/suffix options.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: Chang Seok Bae <chang.seok.bae@intel.com>
It is quite likely we may want to build the same input with multiple
output formats; make it so we don't lose the list file.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
In order to support Mach-O better, add support for subsections, as
used by Mach-O "subsections_via_symbols". We also want to add
infrastructure to support this by downcalling to the backend to
indicate if a new subsection is needed.
Currently this supports a maximum of 2^14 subsections per section for
Mach-O; this can be addressed by adding a level of indirection (or
cleaning up the handling of sections so we have an actual data
structure.)
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
"output" and "debug" are supposed to redirect to the current output
and debug formats. Fix it so it actually does.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Make it possible to generate variants of RET(F) with explicit operand
size specified without having to use o16/o32/o64.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Automatically assign values to the instruction flags; we ended up with
a case where pushing flags into the next dword caused comparison
failures due to other places in the code explicitly comparing
field[3].
This creates necessary defines for this not to happen; it also cleans
up a fair bit of the iflag code.
This resolves BR 3392454.
Reported-by: Thomasz Kantecki <tomasz.kantecki@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
The calculation of vmin in overflow_general() was bogus, causing
silliness like ~80h being warned about in a byte context.
Reported-by: C. Masloch <pushbx@38.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
We could generate the MRI version (SSE 4.1) instead of the RMI
(SSE 2) version of these instructions if a 64-bit register was given
as the destination.
Reported-by: Vasiliy Olekhov <olekhov@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
We need to always define the end symbol, otherwise we might find
ourselves in a situation where the alignment code grows (common!) and
then the symbol is defined late.
Reported-by: ig <glucksmann@avast.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Issue a diagnostic and don't panic for invalid TIMES values.
Reported-by: C. Masloch <pushbx@38.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Support 16-character section names, and support the debug section
flag.
Reported-by: Andrey Timofeyev <timofeyev@bk.ru>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Make the internal handling of segment numbers just a little more
sane. The whole use of when we have done ofmt->segbase or not is
crazy, though...
In the meantime, add a few more hacks to the dbg output format to make
it more useful.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
a) Fix a number of missing instances of DZ and ZWORD.
b) NASM would crash if TIMES was used on an instruction which varies
in size, e.g. JMP. Fix this by moving the handling of TIMES at a
higher level, so we generate the instruction "de novo" for each
iteration. The exception is INCBIN, so we can avoid reading the
included file over and over.
c) When using the RESx instructions, just fold TIMES into the reserved
space size; there is absolutely no point to iterate over it.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The fvm: annotation to generate the correct EVEX compressed
displacements had inadvertently gotten dropped from a handful of
instructions in checkin c33d95fde9:
BR 3392370: {z} decorator allowed on MOVDQ* memory operands
Put them back, and verify they work.
Reported-by: Henrik <henrik@gramner.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
It turns out that the calculation of "twopwr" in ieee_flconvert_bin()
was more complex than necessary, and wrong in the case of a pure
fraction.
Reported-by: Roel <roelsuidgeest@zonnet.nl>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Distribute the file generation rules to auxiliary Makefiles via
syncfiles.pl. These rules are OS- and Make-dialect-generic enough
that our mangling script handles them well enough.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Remove the list file before running the first pass, so in case we
die before running pass 2 then there won't be a stale list file
sitting around.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Checkin c33d95fde9:
BR 3392370: {z} decorator allowed on MOVDQ* memory operands
... inadvertently broke broadcast operations, which only apply to
memory operands and therefore were only handled in one of the two
brace-parser implementations. Fix that.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
When we make an artificial RESB instructions (due to isolated
prefixes) we need to make sure there isn't any crap left in the
operands structure. The easiest way to guarantee that is to force it
to zero.
Reported-by: Henrik <henrik@gramner.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Update the debug output format to dump (most of) the information that
is available via the new backend format, as well as the legacy backend
format -- probably the only backend ever which will ever want both!
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Handle, hopefully correctly, self-relative expressions (that is,
expressions of the form X - Y where Y is a symbol in the current
segment, possibly $ or $$) used as offsets or immediates, as opposed
to arguments to Dx statements (which have already been supported for a
while.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Allow constructs like:
dd foo - $
... where foo is an external symbol. Currently this is only
implemented for extops, i.e. dx opcodes.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
If we can't mmap a file and instead have to fread(), if the data is
small enough that we can reasonably accomodate it in a memory buffer,
then just read it once.
It seems rather unlikely that very large files would be used with
TIMES anyway.
Also note: the previous comment about nasm_file_size[_by_path]() being
invoked twice was spurious; it does not actually happen.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
A number of fairly common operations are invoked way too many times,
especially when using incbin. Drastically reduce the number of system
calls that need to be executed, and use memory mapping to reduce
unnecessary double buffering.
We could improve this further by leaving files open once used;
however, that might run into file count problems on some systems.
Still unclear is why we seem to invoke nasm_file_size() twice per pass
for incbin.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Fix the printing of the macro stack: we need to follow the
mstk->next_active list, not mstk->next, and we need to reverse the
order so that the highest-level inclusion comes first.
Since this should be a rare or at least performance-insensitive
operation, do it using simple function recursion.
Finally, add an ellipsis before the "from macro" message; it greatly
enhances readability.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
It can be hard to find errors inside potentially nested macros.
Show the mmacro expansion stack when printing diagnostics.
Note that a list file doesn't help for errors that are detected
before the code-generation pass.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Issue a specific suppressible warning if we encounter the PTR keyword.
This usually indicates someone mistakenly using MASM syntax in NASM.
This introduces a generic infrastructure for issuing warnings for such
keywords.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
When a local label was seen, the debug backend would not receive the
full label name! In order to both simplify the code and avoid this
kind of discrepancy again, make both the output and debug format calls
from a common static function.
However, none of the current debug format backends want to see NASM
special symbols (that start with .. but not ..@) so filter those from
the debug backend.
Finally, fix an incorrect comment in nasm.h: the debug format is
called *after* the output format.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Jim Kukunas <james.t.kukunas@linux.intel.com>
The fix for BR 3392278:
aa29b1d93f assemble.c: Don't drop rex prefix from instruction itself
... would cause multiple REX prefixes to be emitted for some
instructions. Create a new flag to indicate that REX has already been
emitted, which can be cleared for each instance of an instruction.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
BR 3392275 complains about xmm0 having to be explicitly included in
the assembly syntax when it is implicit in the encoding. In the
interest of "be liberal in what you accept", accept either form in the
input.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Allow specifying {vex3} or {vex2} (the latter is currently always
redundant, unless we end up with instructions at some point can be
specified with legacy prefixes or VEX) to select a specific encoding
of VEX-encoded instructions.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Since the multi-line macro preprocessor is modified to expand
grouped parameter with braces. The escape character is not needed
any more.
The testcase converter script is also modified not to generate '\'.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Only generate a signed relocation if the displacement size is less
than the address size. This matters when involving address size
overrides.
It is technically impossible to do this one perfectly, because it is
never really knowable if the displacement offset is used as a base or
an index.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Reverted the redundant branch instruction patterns for bnd prefix.
And when a relaxed jmp instruction becomes a short (Jb) form,
bnd prefix is not needed because it does not initialize bnd registers.
So in that case, bnd prefix is silently dropped.
BND JMP foo -> drops bnd prefix
BND JMP short foo -> shows an explicit error
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
GAS uses *1 multiplier for explicitly marking an index register in mib operand.
e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format
So only for mib operands, this is encoded same as gas does.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
MPX test asm files are added. These include all three different styles of
mib syntax (NASM, ICC and gas).
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Mostly intended for the "mib" expressions in BNDLDX/BNDSTX.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
test/avx512*.asm files are now tested by using perfomtest.pl
Refer to pefomtest help message for the usage.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Added Prefetch (AVX-512PF) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1.
CPUID feature flag for PREFETCHWT1 is TBD
but PREFETCHWT1 is included in this commit.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Added Exponential and Reciprocal (AVX-512ER) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1.
IF_AVX512 is now shared by all AVX-512* instructions as a bit mask.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Added Conflict Detection (AVX-512CD) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on.
Test case is also updated to validate them.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Added K* instructions test cases in test/avx512f.asm.
The previous test case from GNU AS were repeating the same instruction twice,
so the repeated half part is removed.
Changed the python script (gas2nasm.py) to include opmask instructions.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Fixed or purged some old comments and added a comment for a previous patch.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
From gas testsuite file, a text file containing raw bytecodes
is useful when verifying the output of NASM.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This was converted from a gas testsuite.
(gas/testsuite/gas/i386/x86-64-avx512f-intel.d)
A python script that is used for converting is also included.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
There are two instructions (VGATHERQPS, VPGATHERQD) where the only
separation between two forms is the vector length given to the vector
SIB. This means the *matcher* has to be able to distinguish
instructions by vector SIB length and the matcher only operates on the
operands and the instruction flags, not on the bytecode.
Export the vector index-ness into the operand flags and add to the
matcher.
This resolves BR 3392260.
Reported-by: Agner <agner@anger.org>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
The moffset opcodes A2 and A3 do not support HLE. Unfortunately
checkin
fb3f4e6d HLE: Change NOHLE to be an instruction flag
... inadvertently lost the NOHLE flag for opcode A2.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6
and reverted in:
d279fbbd80
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The way our matching system works we have to make NOHLE an instruction
flag rather than an byte code; by the time we run the byte code
interpreter we have already picked an instruction pattern once and for
all.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Clean up JMP/CALL patterns so they don't disassemble quite so uglily.
Fix a CALL pattern which would have incorrectly generated a (harmless)
REX.W prefix.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
