There are two instructions (VGATHERQPS, VPGATHERQD) where the only
separation between two forms is the vector length given to the vector
SIB. This means the *matcher* has to be able to distinguish
instructions by vector SIB length and the matcher only operates on the
operands and the instruction flags, not on the bytecode.
Export the vector index-ness into the operand flags and add to the
matcher.
This resolves BR 3392260.
Reported-by: Agner <agner@anger.org>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This patch is getting rid of the following bytecodes
'pushseg','popseg','pushseg2','popseg2' and simplifies
overall code.
[gorcunov@: a few style fixes]
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
It doesn't seem worth >200 lines of C and Perl to save ~50 lines in insns.dat.
In order to make this work I had to rename sbyte16/sbyte32 so that
they can take an ordinary size suffix (their size suffix was formerly
treated specially).
This fixes one disassembly bug: 48C7C000000080 disassembles to mov
rax,0x80000000, which reassembles to B800000080, which loads a
different value.
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Acked-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AMD CPUs do support SVM instructions in 32-bit mode thus drop X64
restriction from instructions template where appropriate.
Signed-off-by: Andrew Nayenko <resver@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
In long mode relative offsets are always 32 bits sign-extended to 64
bits and absolute near addresses are always 64 bits, regardless of the
operand size.
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This adds "np" to a bunch of SSE-style instructions that should have
it, "norep" (which was implemented but unused) on quasi-SSE instructions
that use F2 and F3 as instruction extensions but 66 for operand size,
"nof3" (newly implemented) on a few instructions, "norexw" on some
instructions that have only 32-bit and 64-bit versions, and one NOLONG.
It also removes some incorrect "np"s, changes some "f3"s to "f3i"s,
and fixes the decoding of the XCHG/NOP/PAUSE mess: F390 is always
PAUSE even when rex.b=1 (at least according to XED).
Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Allow the form:
mov <rm>,byte 1
... to generate the explicit byte form. An unfortunate side effect is
that disassembly is ugly; this could be fixed by making a special byte
code that acts the same for the assembler but disassembles specially.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Remove the SB flag from the rm,imm forms of the shift/rotate
instructions; presumably the intent was to mark the immediate as a
byte immediate, but it instead caused the memory operand to be
accepted without a size, but generate the incorrect code as a result.
Note: it would be good to modify the UNITY filter so that the explicit
form:
shl eax,byte 1
... forces the imm form rather than the ,1 form.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The 82h opcodes are undocumented aliases for the 80h opcodes, except
in 64-bit mode. We don't generate them, but let the disassembler
handle them correctly.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The moffset opcodes A2 and A3 do not support HLE. Unfortunately
checkin
fb3f4e6d HLE: Change NOHLE to be an instruction flag
... inadvertently lost the NOHLE flag for opcode A2.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Add norexw to the 32-bit versions of instructions with only 32- and
64-bit forms (66 ignored as a size override.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
New instructions (ADCX, ADOX, RDSEED) from the 013 AVX spec
(Intel® Architecture Instruction Set Extensions Programming
Reference).
Note: ADCX in 64-bit mode disassembles incorrectly with a 64-bit
argument. This still needs to be fixed before a 2.10.02 release.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6
and reverted in:
d279fbbd80
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
The way our matching system works we have to make NOHLE an instruction
flag rather than an byte code; by the time we run the byte code
interpreter we have already picked an instruction pattern once and for
all.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Clean up JMP/CALL patterns so they don't disassemble quite so uglily.
Fix a CALL pattern which would have incorrectly generated a (harmless)
REX.W prefix.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
