Users who wish to control the level of optimization can
continue to specify -O0, -O1, or -Ox,
where x can be the letter itself, or any number > 1.
However, even with optimization turned off,
NASM will always make enough passes to resolve
forward references. As a result, INCBIN is now the only
item left in the critical expressions list, although TIMES
still has its own constant value check.
We added the length of VEX prefixes twice in calcsize(); this resulted
in the wrong symbol addresses when compiling without the optimizer.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Any use of ins->forw_ref that isn't related to control of the
optimizer is fundamentally broken. Use
operand->opflags & OPERAND_FORWARD instead. This even has the nice
side benefit of simplifying the code.
Introduce new preprocessor directives %depend and %pathsearch, and
make incbin a standard macro using these filenames. This lets us
remove the code that makes incbin search the path.
Support is4 bytes without meaningful information in the bottom bits.
This is equivalent to /is4=0 for the assembler, but makes the bottom
bits don't care for the disassembler.
Properly done, all SSE instructions which has the 66/F2/F3 opcode
multiplex need two prefixes: one to control the use of OSP and one to
control the use of REP. However, it's a four-way select: np/66/F2/F3;
so introduce shorthand bytecodes for that purpose.
Generate a byte array instead of using C compiler strings for the byte
codes. This has a few advantages:
- No need to special-case zero due to broken C compilers.
- Only insns.pl only ever reads the string, so we can invent our own
syntax.
- Compaction.
- We can give it the proper, unsigned type.
First cut at AVX machinery support. The only instruction implemented
is VPERMIL2PS, and it's probably buggy. I'm checking this in with the
hope that other people can start helping out with (a) testing this,
and (b) adding instructions.
NDISASM support is not there yet.
In particular, we'd miss issuing warnings for out-of-range dword
values, and the message for constants too large (we can't deal with >
64 bits) said 32 bits, not 64.
- Correct the building on the disassembler decision tree.
- Handle SSE instructions with F2 prefix (\332) correctly.
- Mark instructions which are now used as prefixes with ND.
(In a future version when we have better CPU version handling,
we should probably build the decision tree at runtime based on
the selected CPU feature sets.)
- Sanitize the handling of \144-147 and \154-157 in both the assembler
and disassembler. They take an opcode byte as argument; don't
pretend they don't.
Address data is always int64_t even if the size itself is smaller;
this was broken on bigendian hosts (still need testing!)
Create simple "write sized object" macros.
Don't combine type and size into a single argument; *every* backend
immediately breaks them apart, so it's really just a huge waste of
effort. Additionally, it avoids using short immediates in the
resulting code, which is a bad thing.
assemble.c was full of code containing ins->oprs[c - 0xxx] where 0xxx
was the base of the particular code block. Verbose and error prone
when code is moved around. Now we precompute opx = &ins->oprs[c & 3]
before dispatching, resulting in less code.
Don't warn for overflow in segmented references; those are linker
references and it is up to the backend or the linker to warn if they
overflow their permitted size.
Revamp the address- and prefix-handling code to make more sense in
64-bit mode. We are now a lot closer to where we want to be, but
we're not quite there yet.
ndisasm may very well have problems, or give counterintuitive output.
However, checking it in so we can make forward progress.
Both C and C++ have "bool", "true" and "false" in lower case; C
requires <stdbool.h> for this, in C++ it is an inherent type built
into the compiler. Use those instead of the old macros; emulate with
a simple typedef enum if unavailable.
Concentrate compiler dependencies to compiler.h; make sure compiler.h
is included first in every .c file (since some prototypes may depend
on the presence of feature request macros.)
Actually use the conditional inclusion of various functions (totally
broken in previous releases.)
Remove bogus "treat labels different from immediates" code, which
would result in generating of a relative mod/rm but without adjusting
the address accordingly.
Update addressing mode test.
Auto-generate 0x67 prefixes without the need for \30x codes; the
prefix is automatically added when there is a memory operand with
address size differing from the current address size (and impossible
combinations checked for.)
Implement oword, reso, do, as well as the SO flag to instructions. No
instructions are actually flagged with SO yet, but this allows us to
specify 128-bit sizes in instruction patterns.
This checkin completes what is required to actually generate SSE5
instructions. No support in the disassembler yet.
This checkin covers:
- Support for actually generating DREX prefixes.
- Support for matching operand "operand X must match Y"
Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be
a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the
previous \332 flag changed to \335). This is necessary to get the REX
prefix in the right place for instructions that use it.
We are going to have to go in and change existing instruction patterns
which use these, as well.
We have a lot of enumerations; by declaring fields as such, we make it
easier when debugging, since the debugger can display the enumerations
in cleartext. However, make sure exceptional values (like -1) are
included in the enumeration, since the compiler otherwise may not
include it in the valid range of the enumeration.
Implement "REL" and "ABS" modifiers for offsets in 64-bit mode. This
replaces "rip+XXX" type addressing. The infrastructure to set the default
mode is there, but there is nothing to throw the switch just yet.
\313 indicates a fixed 64-bit address size. It was incorrectly
documented and incorrectly implemented in the assembler, and was
unimplemented in the disassembler.
The recent switch from register numbers (with -1 meaning "none") to
register flags (with 0 meaning "none") broke the generation of 67
prefixes, especially in 64-bit mode.
Remove tests that are bogus (they trigger for legitimate instructions.)
The failure cases are okay anyway since they will be trapped by the
REX generation logic.
Remove a bogus check for 64-bit operands. If appropriate, we will
detect this during REX generation and will bail then. However, there
are other instructions (floating point, MMX, ...) which are legitimately
64 bits in non-64-bit mode.
Get rid of magic open-coded register numbers. We now keep track of
a total of three different kinds of register numbers: the register
enumeration (regs.h), the x86 register value, and the register flags.
That has all the information we need.
Additionally, do massive revamping of the EA generation code and the
REX generation logic.
- MOV gpr,CRx or MOV CRx,gpr can access high control registers with a LOCK
prefix; handle that in both the assembler and disassembler.
- Get a saner error message when trying to access high resources in
non-64-bit mode.
a) Automatically generate dependencies for all Makefiles;
b) Move register definitions to a separate .dat file;
c) Add support for "unimplemented but there in theory" registers.
